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* ec.tasklist: Consolidate duplicate commentsDaisuke Nojiri2019-04-081-11/+1
| | | | | | | | | | | | | | | | | | | | | | | It's simply a bad idea to describe a macro in multiple locations. It'll make it hard to change. It'll be difficult to keep all locations in sync. This patch replaces the comment duplicated in all ec.tasklist with a pointer to the CONFIG_TASK_LIST definition. The macro will be described in a single place (just like all/most other macros). Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Id658b9d68e742e4334c692b804d9c98c8de21313 Reviewed-on: https://chromium-review.googlesource.com/1551579 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* eCTS: Expedite flashing timeDaisuke Nojiri2017-06-281-0/+6
| | | | | | | | | | | | | | | eCTS tests are small. We can use smaller flash size to expedite tests. This patch reduces flashing time for stm32l476 from 24 sec to 6 sec. BUG=chromium:736020 BRANCH=none TEST=python util/run_ects.py Change-Id: I829ee2c947664f2d7ed373f52ff336e9a9580817 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/553580 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eCTS: Add nested interrupt test (Low->High)Daisuke Nojiri2016-11-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | Add a nested interrupt test to eCTS. Lower priority IRQ is fired, followed by higher priority IRQ. Handler executions should be nested. P1 *-----* / \ P2 *----* *----* / \ task_cts ----* *---- A B C D BUG=chromium:653195 BRANCH=none TEST=cts.py -m gpio, interrupt, timer; make buildall Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f Reviewed-on: https://chromium-review.googlesource.com/408797 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Add I2C tests for read8/16/32 and write8/16/32Daisuke Nojiri2016-10-053-1/+21
| | | | | | | | | | | | | | This patch adds tests for i2c_read8/16/32 and i2c_write8/16/32. BUG=chromium:653183 BRANCH=none TEST=make buildall. Run cts.py -m i2c for 100kHz with 10k ohms pull-up registers on SCL and SDA. TH=stm32l476g-eval DUT=nucleo-f072rb. Change-Id: I8121b1c5dc7542da45141543e35036ef41364c38 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393331 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: CONFIG_FLASH should be optionalBill Richardson2016-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The application may need to read/write/erase the flash memory, but we not want console users to do so. This CL adds CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH to be undefined while still providing the chip-specific flash_physical_* accessor functions. There aren't many board.h files that needed changes, since CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; try on Gru with and without CR50_DEV=1 See that it still boots, updates, wipes, restores, etc. without linking common/flash.o in the production image; and that the flash commands are still there in the dev build. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93 Reviewed-on: https://chromium-review.googlesource.com/391188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cts: Add timer testDaisuke Nojiri2016-07-292-0/+20
| | | | | | | | | | | | | | | | | | | | | The timer test checks the accuracy of the internal timer. After sync, DUT and TH start counting down one second. After one second, DUT raises GPIO level. TH determines whether the test passes or not based on how much more or less time elapsed than one second, assuming its clock is calibrated. This test takes advantage of TH running on a bare chip. If the host were measuring (instead of TH), the timing would be affected by many software and hardware layers (e.g. UART drivers on DUT and host, python interpreter, etc.). BUG=chromium:624520 BRANCH=none TEST=cts.py --module timer && cts.py --module gpio && make buildall Change-Id: I535e7772b4d93f1f5d248506f7ea167429a50174 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361384
* cts: Added GPIO test suiteChris Chen2016-07-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Contains code for all the gpio tests so far. Code in cts_task for th and dut is for testing purposes and test result reporting will be updated in the next patch. BRANCH=None BUG=None TEST=Manual - Connect handshake and gpio test lines between th and dut - Build tests - run 'cat /dev/ttyACM0' in one terminal - run 'cat /def/ttyACM1' in another - Flash boards - All test results should print either passed or unknown Change-Id: I7142fb87a6ce0a20c571cde608fbbe60e35898ea Reviewed-on: https://chromium-review.googlesource.com/359935 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cts: Added sync() functionChris Chen2016-07-121-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | sync() involves 2 gpios on each board, each labeled GPIO_HANDSHAKE_OUTPUT and GPIO_HANDSHAKE_INPUT on their respective boards. They both start low, then the th wiggles his line up and down, waiting for the dut to mimic it. BRANCH=None BUG=None TEST=manual - Connect handshake lines to appropriate pins on each board (pins found in board's gpio.inc) - Build tests - Flash boards - run 'cat /dev/ttyACM0' in one terminal - run 'cat /dev/ttyACM1' in another - They should each have printed 'successful sync' Change-Id: I61233bca9605ba89c3628c2a65ca9013c56365ea Reviewed-on: https://chromium-review.googlesource.com/359355 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Add cts.tasklistDaisuke Nojiri2016-07-111-2/+1
| | | | | | | | | | | | | | | | | | | | | | cts.tasklist contains tasks run only for CTS. These tasks are added to the tasks registered in ec.tasklist with higher priority. This design allows board directories to be free from CTS stuff. cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist). If a suite does not define its own cts.tasklist, the common list is used (i.e. cts/cts.tasklist). BUG=chromium:624520 BRANCH=none TEST=Ran the followings: make buildall make CTS_MODULE=gpio BOARD=nucleo-f072rb make CTS_MODULE=gpio BOARD=stm32l476g-eval Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359445 Reviewed-by: Chris Chen <twothreecc@google.com>
* cts: First patch flashes blank testsChris Chen2016-07-091-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The first time you use this with a particular th, connect only th and run ./cts.py --th Then connect both boards and you can run ./cts.py to build/flash both boards. BRANCH=None BUG=None TEST=manual - Enter chroot - Navigate to ec/cts - Connect only th - 'sudo ./cts.py --th' - './cts.py -b' - Exit chroot - Connect both boards - './cts.py -f' Each board should flash successfully Change-Id: Ib14fccabcd9fdad04f9b92817da597bc0dcb3d89 Reviewed-on: https://chromium-review.googlesource.com/358100 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Remove Makefile symlinks under board directoryDaisuke Nojiri2016-07-091-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | This feature is inconsistent. Not all boards have such a symlink (for a obvious reason). This feature is fragile. It's most likely not tested and going to be broken if not already. Developers won't like it if they have to test two different ways to build boards before submitting patches. This feature is not necessary. If you build EC in the standard way (e.g. make BOARD=samus), these symlinks are not needed. This feature is wasteful. Extra disk spaces are used and extra lines are added to Makefile (increasing code complexity slightly). BUG=chromium:626776 BRANCH=none TEST=make buildall Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/359321 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* STM32: Add HSE and PLL to clock source selectionDaisuke Nojiri2016-04-291-1/+12
| | | | | | | | | | | | | | | | | | | This patch adds HSE and PLL as a system clock oscillator for STM32L4. This allows us to drive the chip at a higher frequency (up to 80 MHz), which is necessary to big-bang GPIO ports accurately. BUG=none BRANCH=tot TEST=make buildall. Verified console works on STM32L476G-Eval using HSE, PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz. Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a Reviewed-on: https://chromium-review.googlesource.com/341275 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* STM32: Support LPUART consoleDaisuke Nojiri2016-04-252-3/+10
| | | | | | | | | | | | | | | This patch adds support for console on LPUART (low power UART). It is wired to the USB type B port on the board, which is also one of the power sources. So, using LPUART simplifies the set up. BUG=none BRANCH=tot TEST=Verified console works on stm32l476g-eval. make buildall Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340101 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Bring up STM32L476G-EvalDaisuke Nojiri2016-04-257-0/+134
This patch adds initial set of files to bring up STM32L476G-Eval board. BUG=none BRANCH=tot TEST=Tested console. make buildall && make tests Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340100 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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