| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Supoprt PPC SYV682X on Phaser-R series
BUG=b:160940803
BRANCH=firmware-octopus-11297.B
TEST=make buildall
Change-Id: I7e0c66cc0626eda92985ebc40430039ba2094ae8
Signed-off-by: jerry2.huang <jerry2.huang@lcfc.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2413972
Reviewed-by: Marco Chen <marcochen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=octopus
BUG=b:142953493
TEST=verify that later modification of gpio flag will no allow driving
signal high.
Change-Id: I0b8c1503ba8c03afa3eb6fa4f921b3480106f05b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869407
Commit-Queue: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
GMR sensors can be used to
(1) detect clamshell/tablet mode
(2) detect lid open/closed
But hall sensors can only do (2).
Therefore the naming related to "hall sensor" for tablet mode
application is incorrect.
This patch performs the following renaming to better reflect the reality:
config:
CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE
CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM
CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR ->
CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR
GPIO:
HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L
functions:
hall_sensor_disable() -> gmr_tablet_switch_disable()
hall_sensor_isr() -> gmr_tablet_switch_isr()
hall_sensor_int() -> gmr_tablet_switch_init()
variable:
hall_sensor_at_360 -> gmr_sensor_at_360
BUG=b:139378190
BRANCH=none
TEST=make buildall
Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
First wave projects don't have any board with keyboard backlight so the
GPIO - KB_BL_PWR_EN should be configured by macro of UNIMPLEMENTED
instead of output direction.
BRANCH=octopus
BUG=b:130329644
TEST=buildall
Change-Id: I5c37b4b5ec3eb3f629c6d494064a6a27a3a1417c
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1564493
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Recent kernel changes expect the EC to use a dedicated interrupt pin
from the EC to the AP to notify the AP of pending sensor data (instead
of using an eSPI "interrupt").
The octopus boards have this hardware support, we just need to enable
the EC use it.
BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=perform sensor tests on various octopus boards
Change-Id: I2bd3ffe14947d5f1ec71acbb53fcac962b007cf9
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1403103
Reviewed-by: Enrico Granata <egranata@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This will help with using the hardware support to reset the RTC on the
SoC.
BUG=b:119678692
BRANCH=octopus
TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to
trigger an RTC reset and ensure that EC does not get reset while the SoC
boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and
wake from ec hibernate (10 iterations each) and suspend_stress_test for
50 iterations successfully.
Change-Id: Ib79012b43e397d4c27ca829b135115bebf77dedb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1354493
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Set the unused pins as input with an internal pull-up if there is no
external pull-up/pull-down. This helps save some power. Update the
name for CCD_MODE_EC_L pin. Add configuration for TRACKPAD_INT_1V8_ODL
pin.
BRANCH=None
BUG=b:110192175
TEST=make -j buildall && Bootup to chromeos. Also verified that power
stayed the same or slightly lower(6.63mW on PP3300_ec_mw to 6.57 mW over
10 sec average on Phaser360).
Change-Id: I181bd718eb1d7915593e2185813590395fbea048
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1336732
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change performs the following renaming:
1. CONFIG_TABLET_SWITCH -> CONFIG_HALL_SENSOR
Indicates if a device has hall sensor
2. TABLET_MODE_GPIO_L -> HALL_SENSOR_GPIO_L
Provides the interrupt line from hall sensor to EC.
3. tablet_mode_isr -> hall_sensor_isr
Interrupt routine that gets control on hall sensor interrupt.
4. tablet_mode_init -> hall_sensor_init
Init routine for initializing hall sensor interrupt.
5. tablet_switch_disable -> hall_sensor_disable
Disable hall sensor interrupt and tablet mode sub-system.
This is done to separate hall sensor interrupt from tablet mode
handling. It is another step towards aligning tablet mode detection on
EC with Chrome. Hall sensor interrupt occurs when the lid is in
360-degree flipped mode. If tablet mode is not already triggered by
lid motion driver, then hall_sensor_isr will set tablet mode and take
necessary actions to disable input peripherals.
CQ-DEPEND=CL:1351518
BUG=b:120050761
BRANCH=octopus
TEST=make -j buildall
Change-Id: I5841f6875d538a624cb888bc048f252397ab457c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1350469
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The reset pin for ANX3447 was added. This pin used to be a 1.8V signal and
it now a 3.3V signal, so we need to take care to ensure that older
boards don't try to drive 3.3V into the SoC.
Other changes are just renames.
BRANCH=none
BUG=none
TEST=current phaser (ID=2) works
Change-Id: Ife0a1617f94e4f4a40d43b16328d5540ea35b3ff
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1334031
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change adds a call to the C0 TCPC reset for standalone TCPC boards
which have that pin hooked up in hardware, and adds the GPIO as
unimplemented for boards which do not have this yet.
BRANCH=None
BUG=b:112756630
TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset,
then verified that charging on C0 worked. Also imaged yorp proto 2 and
rebooted, verifying C0 reset was not attempted.
Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1257647
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change adds CCD_MODE_ODL as an input for all octopus boards so it
will be present in the "gpioget" output for debugging.
BRANCH=None
BUG=b:116849648
TEST=builds, confirmed net showed up on bip and yorp proto 2
Change-Id: I0da194e433444f160f10573c27e5e463694adf38
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1254923
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Measure the Vbus voltage of port 0 (USB_PD_PORT_ANX7447) via ADC 9,
measure the Vbus voltage of port 1 (USB_PD_PORT_PS8751) via ADC 4.
BUG=b:115997207
BRANCH=none
TEST=check log output of `ectool usbpdpower` for 4 cases are all correct
case1. Adapter plugged in only port0 (motherboard):
Port 0: SNK Charger PD 14932mV
Port 1: Disconnected
case2. Adapter plugged in only port1 (sub-board):
Port 0: Disconnected
Port 1: SNK Charger PD 14850mV
case3. Adapter plugged in both two ports (port0 first, then port1):
Port 0: SNK Charger PD 14877mV
Port 1: SNK (not charging) Charger PD 5000mV
case4. Adapter plugged in both two ports (port1 first, then port0):
Port 0: SNK (not charging) Charger Unknown 5000mV
Port 1: SNK Charger PD 14905mV
Change-Id: Icae0abecbcbee6af5f7167fcefd969c322947a26
Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1233094
Commit-Ready: Nick Chen <nickchen@ami.corp-partner.google.com>
Tested-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Tested-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The upcoming work to implement the fleex power LED will require slightly
different power LED behavior, so this refactors the power LED code to be
more flexible. This change also sets the phaser power LED GPIO name to
something more clear, and protects the code from a possible
divide-by-zero condition which can be hit with undefined states.
Currently, there will be prints 4 times per second that the board is in
the undefined state, which should draw a developer's attention to the
issue.
BRANCH=None
BUG=None
TEST=verified power LED behaved the same on phaser in all different
power states, verified that removing a state's entry in the table
results in an error print to the console in that state
Change-Id: I58733008e5e49d1e631d79a8631d2ca04127bd08
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1156872
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Remove the unnecessary GPIO_PULL_UP of volume up and down for phaser,
there are external pull up resistors (R185 & R229).
BUG=b:110013537
BRANCH=none
TEST=Press volume buttons, verified by OEM.
make buildall pass.
Change-Id: I316973e02a24cb8716da372e9bbd1f3ae7dfdfc7
Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1149775
Commit-Ready: Nick Chen <nickchen@ami.corp-partner.google.com>
Tested-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Reference LED behavior spec and implement it.
Add Power LED common code.
Yorp and bip also do some necessary charges.
BUG=b:80501031,b:110086152
BRANCH=none
TEST=Verify LED behavior at different power state.
Change-Id: I88dbad30101e7983304c15f88b52b31457607749
Signed-off-by: eddylu <eddylu@ami.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1116628
Commit-Ready: Eddy Lu <eddylu@ami.corp-partner.google.com>
Tested-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects USB2_DUALROLE
and USB2_VBUS_SNS to be 1.8V. Since there is an internal pull-up on
USB2_DUALROLE from the SoC side, this change configures USB2_OTG_ID to be
open drain so that it is actively driven from the EC when it wants to
pull it low. Otherwise, the pin would be tri-stated from the EC side
allowing it to be pulled up to 1.8V because of the SoC internal pull-up.
BUG=b:111102089
BRANCH=None
TEST=Verified that there is no more leakage of 1.8V rail.
Change-Id: I306e809f6b3ad31596f7f11da68311afcd1eac32
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1140498
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change enables EC_RST_ODL as wake source from PSL hibernate
mode. Since EC_RST_ODL does not need to be an interrupt during normal
EC operation, it is configured as GPIO_INPUT with wake on low-to-high
transition flag set to allow PSL common code to configure the input
pin correctly before going into PSL mode.
CQ-DEPEND=CL:1130853
BUG=b:109759558
BRANCH=None
TEST=Verified that phaser wakes up from PSL hibernate by toggling
EC_RST_ODL.
Change-Id: I0617eee154cabce946b6e9694f5d6f3a155027b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1130934
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This change enables PSL for phaser board by:
1. Selecting CONFIG_HIBERNATE_PSL
2. Configuring alternate functions for PSL_IN pins to allow wakeup
from PSL hibernate
BUG=b:109759558
BRANCH=None
TEST=None
Change-Id: I5747d4b0408e76eb234ccd6160ea7df36a765e7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1127454
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds internal PUs for unused pins on phaser in gpio.inc to
prevent leakage current since default GPIO functionality. These unused
pins which need internal PUs/PDs usage will be added in the section
3.5.1 in next version of the datasheet.
BRANCH=none
BUG=b:110170824
TEST=Passed "build BOARD=phaser"
Change-Id: I9f8584d98bbb7c67d0cacc94a3bb4fba81f1441c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1119606
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable CONFIG_DYNAMIC_MOTION_SENSOR_COUNT so that clamshell
skus and convertible skus get different sensor number. Enable
lid angle function to make peripherals get correct state on
convertible skus. Enable tablet mode for convertible skus as
well.
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
BRANCH=none
BUG=b:110604678
TEST=boot phaser360 sku, test keyboard function when hinge is
at 135, 180, 270, 360 degree. test tablet mode when 360 degree.
Change-Id: I8f15a2d3ea3ae7d0cf5d60333e079d1ffd8e906b
Reviewed-on: https://chromium-review.googlesource.com/1114667
Commit-Ready: Paul Ma <magf@bitland.corp-partner.google.com>
Tested-by: Paul Ma <magf@bitland.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add feature of volume up and down for phaser.
BUG=b:110013537
BRANCH=none
TEST= Press volume buttons, verified by OEM.
Change-Id: I4668281b163823a62fc39802f15245cd6e5b6b12
Signed-off-by: nickchen <nickchen@ami.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1114660
Commit-Ready: Nick Chen <nickchen@ami.corp-partner.google.com>
Tested-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Tested-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com>
Reviewed-by: Chao Ding <chao.ding@bitland.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch add phaser base and lid accel sensor support.
Lid sensor type is lis2de, it has the same register interface
as lis2dh, so they share the same driver. Since it has a very
small fifo, use it in forced mode.
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
BRANCH=none
BUG=b:110013316
TEST=boot phaser board, base and lid sensor can be inititalized
successfully. use console command "accelinfo on", both
sensors has valid output.
Change-Id: Ie8514ea449fec41c6b1e0b6be1f2ae88458d119c
Reviewed-on: https://chromium-review.googlesource.com/1105688
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The alternate mode for i2c still needs to set the 1.8V flag since it is
called when configuring the port initially and when it finishes
manually unwedging the port.
BRANCH=none
BUG=b:109884927
TEST=builds
Change-Id: Iafa87d3420a3605c0ad87bf8e1f5d69c3edb167a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096020
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- Correct pin assignment for EN_USB_A1_5V and LED_3_L
- Add TABLET_MODE_L signal although not hooking up tablet mode
functionality in this CL
- Remove unneeded USB-C PPC signal to port 1 since using TCPC to drive it
- Clean up formatting
BRANCH=none
BUG=b:109747361
TEST=builds
Change-Id: I40a59375c148a6d0666c71f6e5f401aba64ea95d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1087814
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Simple rename of gpio based on newest schematics for yorp and phaser
BRANCH=none
BUG=b:109747036,b:109747361
TEST=build
Change-Id: I08d9010f16e623ca41bb66363d568c4b5bd687e8
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1089040
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To enable device mode, set the gpio USB2_OTG_ID
in the respective boards to high.
Pull the gpio low to disable device mode.
BUG=b:79343083
BRANCH=NONE
TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high,
for DFP mode gpio USB2_OTG_ID should be low.
In OS console, lspci should list xdci.
(with chromiumos/third_party/coreboot/+/1064592)
Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1058832
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable trackpad when entering S3, and display backlight when entering S0
and disable them on the opposite transition. Moving common code to
baseboard.
BRANCH=none
BUG=b:79900266
TEST=bip trackpad works in S3 as wake source. backlight turns off in
S0ix and S3.
Change-Id: I0937771093d87c020b3c0d94a482d108c5a5c180
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1064693
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
|
BRANCH=none
BUG=b:78770036
TEST=build
Change-Id: I10ce1cc0196bc1e9b7d892834351bb9b3d27e3e1
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1042730
Reviewed-by: Scott Collyer <scollyer@chromium.org>
|