| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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Prepare the next hardware revision. It has a PPC chip which requires 5V
rail in S5. The 5V rail enable pin should be turned on whenever the
EC is powered.
Since the existing 5V rail enabling is done inside the qcom power
sequence. Trogdor and Herobrine both shares this qcom power sequence.
For Trogdor, this CL moves the 5V rail enabling from the qcom power
sequence to the board level hook.
For Herobrine, this CL updates the GPIO name and modifies the default
level to HIGH. The CONFIG of 5V control should be disabled. As no board
level hook to modify the 5V rail, the 5V is always on.
BRANCH=None
BUG=b:199804198
TEST=Booted both Zephyr and EC-OS images on Herobrine. Checked the 5V
rail is enabled in S0 and S5.
TEST=Booted both Zephyr and EC-OS images on Lazor. Checked the 5V rail
is enabled in S0 and disabled in S5.
Change-Id: Ifa98ee0c4e970dd89952e94cc6a0e289798e6a57
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3163918
Reviewed-by: Keith Short <keithshort@chromium.org>
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Since the drivers are now taking a mux_state_t set of flags to update,
go ahead and unify the usb_mux API this way as well. It makes the
parameters more apparent than the 1/0 inputs, and aligns the stack to
use the same parameters.
BRANCH=None
BUG=b:172222942
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ie943dbdf03818d8497c0e328adf2b9794585d96e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095438
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Enable the PSL mode for EC hibernate and define the PMU module.
After EC enters hibernate, the PSL_OUT is off and the PPC chip is
powered off. So the PPC chip can be woken up from the dead battery
mode when the external AC is plugged.
BRANCH=None
BUG=b:193583152, b:196405396
TEST=Entered EC hibernate, plugging AC can wake EC up.
Change-Id: I976d7fa7b7dfa57ee8e79501d5973710ef2192e7
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3115436
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Herobrine uses the SPI mux to separate the SPI bus from the AP when
programming the AP firmware. Overdriving signals on WARM_RESET is not
needed. Make the WARM_RESET and POWER_GOOD GPIOs like normal power
signals.
BRANCH=None
BUG=b:187098628
TEST=Booted AP properly. Flashed the AP firmware, even AP is off.
Change-Id: Ie8e42de8174bc71c29424697810e46a2367e3e54
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3105006
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Herobrine uses the Vivaldi keyboard. The Refresh key is at T2
(col:2, row:3), instead of T3 (col:2, row:2). The code filters out
the Refresh key and check any boot key remaining, like the Esc key.
Misconfiguring it fails the recovery boot, as EC detects a redundant
key pressed.
BRANCH=None
BUG=b:196885613
TEST=Pressed Refresh (T2) + Esc and booted EC. Checked the message:
[0.005749 KB boot key mask 1]
which showed the Esc key was recognized.
Without this CL, the message won't show up, as a redundant key
(T2 not recognized as Refresh) is pressed.
Both EC-OS and Zephyr images behave the same.
Change-Id: Iee82d7d4d6b3301ac342abc384488842a9858b7e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102287
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The AP_RST_L and WARM_RESET_L GPIOs are moved to the pins that are
already operate at 1.8V, which are not configurable. The 1.8 flags
are unnecessary.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: I0c5b64ea18b7eada57aca65374d88037e546a609
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3039385
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Each board defines its own callback lid_angle_peripheral_enable().
The implementation is very similar. Create a common implementation
and reduce the duplicated code.
This CL removes the board callbacks which are identifical to the
common callback. If it is slightly different, keep it and add
the __override tag.
The check of TEST_BUILD is unnecessary as the board callback is not
linked in the test build.
BRANCH=None
BUG=b:194922043
TEST=Build all the images.
Change-Id: I73d381730f35b80eff69399cdfc5fb54f839aee0
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069175
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Currently keyboard_scan_config is defined by each board using
CONFIG_KEYBOARD_BOARD_CONFIG. This patch makes it defined as
__override hence removes CONFIG_KEYBOARD_BOARD_CONFIG.
BUG=None
BRANCH=None
TEST=buildall
Change-Id: I53a356741ba4d00e829ca59b74ee6dc704188728
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044403
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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Switch the base accel/gyro sensor from BMI160 to BMI260.
BRANCH=None
BUG=b:194194887
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: I45b5ba072a787ae53f5f5158701dd61cb0c0410f
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3042984
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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BRANCH=none
BUG=b:186264627, b:193807794
TEST=build herobrine_npcx7 and herobrine_npcx9
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: If8870e33643f96658f4902d0fe26081712eb6cf7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3035787
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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Add the I2C bus for the RTC chip. The chip runs at 400KHz.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: Ibf5eec51a938b7a1ce1d1379ae8c2ede2b2f4b03
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993218
Reviewed-by: Keith Short <keithshort@chromium.org>
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Update the GPIOs to match the schematic. Also update the hibnerate
wake sources.
BRANCH=None
BUG=b:192253134, b:193583152
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: I4ed20de0f242f6c1f5fbddef6a59526482b970d1
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993217
Reviewed-by: Keith Short <keithshort@chromium.org>
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The board uses the PSL to enable the core power and the old HIBERNATE_L
rails, like TCPC, PPC, sensor, etc. Deprecate the related logic.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: I1f378126cdac478e335ce06e16835df200fe94ca
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993216
Reviewed-by: Keith Short <keithshort@chromium.org>
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The 3.3V rail is not controlled by EC. Remove the control.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: Id03f0b4943ce0cc19b7ac286e866d06339719223
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993215
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL copies the herobrine_npcx7 board and changes the chip
config to npcx9m3f.
Remove the CONFIG_FLASH_SIZE_BYTES from the board level as it
is moved to the chip level.
BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.
Change-Id: Ie970e1be9d863339869563031513af42c979aec5
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993214
Reviewed-by: Keith Short <keithshort@chromium.org>
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