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* ss-mux: remove unused port_addr initializationv2.0.0Jett Rink2018-09-171-2/+0
| | | | | | | | | | | | | | | | | | | We do not need to set the port_addr variable most places because the SS-MUX is also the TCPC and the tcpc_config_t information is used instead. Remove unused variable setting to avoid confusion. BRANCH=none BUG=none TEST=buildall. phaser USB-C communication (and muxs) still work which is a nominal case for all of these changes. Change-Id: I72ee5da251956eb133091974e8dce5ac7f8787c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1200064 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* usb-c: add high priority tasks for interruptsJett Rink2018-09-171-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To all boards that have space, add the PD tasks that handle interrupts in parallel. This is the last change for go/usb-pd-slow-response-time. BRANCH=none BUG=b:112088135 TEST=buildall. This works on grunt and octopus. This CL is more of a clean up for ToT to ensure that newly copied boards use the correct paradigm. Below is the space taken up by this change: build/atlas/RW/space_free_flash shrank by 212 bytes: (64796 to 64584) build/atlas/RW/space_free_ram shrank by 1408 bytes: (33568 to 32160) build/cheza/RW/space_free_flash shrank by 200 bytes: (205716 to 205516) build/cheza/RW/space_free_ram shrank by 1408 bytes: (38208 to 36800) build/coral/RW/space_free_flash shrank by 212 bytes: (87980 to 87768) build/coral/RW/space_free_ram shrank by 1400 bytes: (2564 to 1164) build/dragonegg/RW/space_free_flash shrank by 276 bytes: (142136 to 141860) build/dragonegg/RW/space_free_ram shrank by 1640 bytes: (24704 to 23064) build/elm/RW/space_free_flash shrank by 204 bytes: (24644 to 24440) build/elm/RW/space_free_ram shrank by 528 bytes: (8972 to 8444) build/eve/RW/space_free_flash shrank by 216 bytes: (83748 to 83532) build/eve/RW/space_free_ram shrank by 1408 bytes: (1824 to 416) build/fizz/RW/space_free_flash shrank by 184 bytes: (17576 to 17392) build/fizz/RW/space_free_ram shrank by 736 bytes: (11648 to 10912) build/glkrvp/RW/space_free_flash shrank by 248 bytes: (92432 to 92184) build/glkrvp/RW/space_free_ram shrank by 1408 bytes: (45088 to 43680) build/kukui/RW/space_free_flash shrank by 160 bytes: (32364 to 32204) build/kukui/RW/space_free_ram shrank by 520 bytes: (11260 to 10740) build/meowth/RW/space_free_flash shrank by 240 bytes: (72232 to 71992) build/meowth/RW/space_free_ram shrank by 1408 bytes: (34496 to 33088) build/nami/RW/space_free_flash shrank by 360 bytes: (82016 to 81656) build/nami/RW/space_free_ram shrank by 1408 bytes: (2656 to 1248) build/nocturne/RW/space_free_flash shrank by 216 bytes: (62756 to 62540) build/nocturne/RW/space_free_ram shrank by 1408 bytes: (34368 to 32960) build/rainier/RW/space_free_flash shrank by 180 bytes: (45468 to 45288) build/rainier/RW/space_free_ram shrank by 528 bytes: (13516 to 12988) build/rammus/RW/space_free_flash shrank by 200 bytes: (91284 to 91084) build/rammus/RW/space_free_ram shrank by 1408 bytes: (1920 to 512) build/reef_mchp/RW/space_free_flash shrank by 212 bytes: (51048 to 50836) build/reef_mchp/RW/space_free_ram shrank by 2120 bytes: (27420 to 25300) build/reef/RW/space_free_flash shrank by 224 bytes: (84564 to 84340) build/reef/RW/space_free_ram shrank by 1408 bytes: (2208 to 800) build/rowan/RW/space_free_flash shrank by 204 bytes: (29668 to 29464) build/rowan/RW/space_free_ram shrank by 528 bytes: (9300 to 8772) build/scarlet/RW/space_free_flash shrank by 156 bytes: (29464 to 29308) build/scarlet/RW/space_free_ram shrank by 520 bytes: (11100 to 10580) build/zoombini/RW/space_free_flash shrank by 276 bytes: (66816 to 66540) build/zoombini/RW/space_free_ram shrank by 2112 bytes: (37376 to 35264) Compared 208 of 208 files. 38 files changed. Total size change: -27484 bytes. Average size change: -723 bytes. Change-Id: Ifbea67ee4d460fb197a1601d0951169f2f2b5b3b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1220667 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* type: Rename matrix_3x3_t to mat33_fp_tYilun Lin2018-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Naming of many vector types and matrix types are not clear enough. For example, we have: vector_3_t, which is a vector of three int. vec3_t, which is a vector of three float. size4_t, which is a vector of four size_t. mat33_t, which is a 3x3 matrix of float. matrix_3x3_t, which is a 3x3 matrix of fixed point. Besides, we have types like int8_t, uint16_t types. To clearly distinguished types, the CL propose to, For vector types, naming should be `$type + 'v' + $num + '_t'`: vector_3_t becomes intv3_t vec3_t becomes floatv3_t vector 4 of uint16_t becomes uint16v4_t (which doesn't exist yet) For matrix types, naming should be `mat$N$N_` + $type + '_t', where $N is the matrix size: matrix_3x3_t becomes mat33_fp_t # fp: fixed point mat33_t becomes mat33_float_t TEST=make buildall -j BUG=b:114662791 Change-Id: I51d88d44252184e4b7b3564236833b0b892edc39 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1215449 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* atlas: add ACOK as wake-from-hibernate sourceCaveh Jalali2018-08-302-3/+3
| | | | | | | | | | | | | | | | | this enables the system to wake up from hibernate when charging power is applied over one of the USB-C ports. BUG=b:113543019 BRANCH=none TEST=verified atlas wakes from hibernate on 1st AC-in Change-Id: Ib9e724f38987c0a0798aef6d8fe6e6d73bb07809 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194998 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: add LID as wake-from-hibernate sourceCaveh Jalali2018-08-291-1/+4
| | | | | | | | | | | | | | | BUG=b:113045336 BRANCH=none TEST=put EC in hiberate using EC console, verified lid-open wakes atlas Change-Id: Ic0380b660978a3ca09935cadb1c581840883a1c9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194997 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: enable active discharge on 5V railCaveh Jalali2018-08-291-2/+2
| | | | | | | | | | | | | | | | this enables active discharge for the PP5000_A rail. BUG=b:112732855 BRANCH=none TEST=flashed atlas with new EC build Change-Id: Ib733eb6e649d9f22c7ce0d1e4bc565f9a2659520 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187900 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* bd99992: add some more register definitionsCaveh Jalali2018-08-241-6/+12
| | | | | | | | | | | | | | | | | this adds definitions for some additional PMIC registers we're using in our codebase. BUG=b:112732855 BRANCH=none TEST=flashed atlas with new EC build Change-Id: Ibad7b11b3770f00c925c2d8fc3b24109147aa643 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187899 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: update ALS scale factorCaveh Jalali2018-08-221-2/+2
| | | | | | | | | | | | | | | | | | this fixes the ALS reading scale factor so we actually get a decent range of values based on ambient light intensity. this scale factor still needs to be calibrated, but is a good guess based on nocturne. BUG=b:112784910,b:112863863 BRANCH=none TEST="accelinfo on" on EC console now reports sensible readings from the ALS Change-Id: I540b1557523a725786013155e276eafd5993e036 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1180613 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: control KB backlight GPIO on suspend/resumeCaveh Jalali2018-08-151-0/+2
| | | | | | | | | | | | | | | | | | | the atlas keyboard backlight has a discrete load switch controlled by a GPIO to enable/disable the keyboard backlight. this turns on the switch when the AP wakes up and disables it when the AP suspends. BUG=b:112619924 BRANCH=none TEST=keyboard light turns off with powerd_dbus_suspend and turns back on when we wake up system Change-Id: Ibbe904be55e0a3b2527f215f37fb1b530f58d9a0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1175545 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: update port LED colors to new specCaveh Jalali2018-08-141-0/+3
| | | | | | | | | | | | | | | | | | - only the LED next to the charging connection is on - "charging" is amber - full charge is white BUG=b:110505328 BRANCH=none TEST=flashed atlas, verified LEDs Change-Id: If4308b971980075305948c43980a2cd52192b7b5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1170575 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: fix order of LEDs to match portsCaveh Jalali2018-08-102-8/+16
| | | | | | | | | | | | | | | | | | | | | this updates the order in which LEDs are listed to match the order of the TCPCs. the charger and LED code use the same port index into the LED and TCPC tables, so we need to keep these tables in the same order. BUG=b:110505328 BRANCH=none TEST=ectool led right/left still controls the correct LED there is an implicit relationship between LEDs and USB-C ports. the ports and LEDs must be listed in the same order. Change-Id: I07c95cdd568f2d90643e1e502bd4698b334a95bf Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1170574 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: tune port LED colors for chassisCaveh Jalali2018-08-101-6/+6
| | | | | | | | | | | | | | | | | | this tunes the RGB LEDs associated with the chassis USB-C ports to better match their expected colors and brightness. BUG=b:110505328 BRANCH=none TEST=visual inspection on actual atlas unit Change-Id: Ibe28924a025957136c80b173f138d7bc7d7607ca Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1170573 Commit-Ready: Caveh Jalali <caveh@google.com> Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* atlas: Update temp sensor namesCaveh Jalali2018-08-101-4/+4
| | | | | | | | | | | | | | | | This updates the temp sensor names to reflect the sensor locations on the board. BUG=b:75070158 BRANCH=none TEST="temps" command on EC console prints new labels Change-Id: Ia4c0a88be68bf264147f65595e4a5d5275bb1d20 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1170313 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "atlas: do not fake power-on as reset-pin"Caveh Jalali2018-08-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit fc1496d1bb84f74d539bc11a205d90926dc79740. this change prevented us from entering recovery mode using the 3-finger salute. the keyboard_scan.c:check_boot_key() depends the reset pin being asserted as a prerequisite to checking the refresh key has been pressed. this means we never get as far as checking for the 3-finger salute key combo. BUG=b:75070158,b:111577561 BRANCH=stabilize-atlas.10819.B TEST=3-finger salute now gets us into recovery Original change's description: > atlas: do not fake power-on as reset-pin > > atlas can detect a power-on reset, so we don't need to fake it as a > reset-pin initiated reset. > > BUG=b:75070158 > BRANCH=none > TEST=EC now claims the reset cause was power-on instead of reset on > cold boot > > Change-Id: I0b0a58f79b605e768719249f1c139f6d46fec30b > Signed-off-by: Caveh Jalali <caveh@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1098531 > Commit-Ready: Caveh Jalali <caveh@google.com> > Tested-by: Caveh Jalali <caveh@google.com> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Bug: b:75070158 Change-Id: Ia3bb9ccecbb69e35b1cec48dabfc5e99b29a3b17 Reviewed-on: https://chromium-review.googlesource.com/1161226 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* espi: Rename CONFIG_HOSTCMD_ESPI_VW_SIGNALS to ↵Furquan Shaikh2018-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS This change renames CONFIG_HOSTCMD_ESPI_VW_SIGNALS to CONFIG_HOSTCMD_ESPI_VW_SIGNALS in order to make it clear that this config option indicates that chipset sleep signals (SLP_S3 and SLP_S4) are tranmitted over virtual wires instead of physical lines with eSPI. BUG=b:111859300 BRANCH=None TEST=make -j buildall Change-Id: Iab4423abc9102164d4f43296a279c24355445341 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1151048 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* atlas: enable ALS pollingCaveh Jalali2018-06-291-0/+3
| | | | | | | | | | | | | | | | | | | it looks like we were missing a config option on the EC to poll the ALS for readings, so just turn it on like on other platforms. BUG=b:110955363 BRANCH=none TEST="accelinfo on 100" on the EC console now reports non-zero ALS values. on linux, /sys/bus/iio/devices/iio:device1/in_illuminance_raw reads plausible values. Change-Id: Id4be964154efcbf021c3b781ff5dc5ba43e432db Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1119662 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: enable charge status LEDsCaveh Jalali2018-06-224-9/+108
| | | | | | | | | | | | | | | | | | | this enables the charge status LEDs. this is largely taken from the nocturne config. the color_map is tweaked to produce reasonable colors on atlas - at least as a 1st order approximation. BUG=b:110505328 BRANCH=none TEST=verified LEDs on a reworked board. color pattern is the same as nocturne. Change-Id: I4be4847e7a7d41ab83df8ab173bb3dba83297212 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1111576 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: update GPIO config for new LED PWM channelsCaveh Jalali2018-06-221-4/+2
| | | | | | | | | | | | | | | | | this reconfigures 2 unused pins to be LED PWM channels. we'll use these on the next version of the board. BUG=b:110505328 BRANCH=none TEST=none Change-Id: I2a25cc5c4e07865b38cc41ef4fa96fc7a41e2664 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1108885 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: config CPU_PROCHOT polarityCaveh Jalali2018-06-202-1/+2
| | | | | | | | | | | | | | | | | | | atlas's CPU_PROCHOT signal is active low which is inverted compared with previous designs. we recently added support for configuring PROCHOT polarity, so we can now configure this pin correctly. BUG=b:79266467 BRANCH=none TEST=prochot pin reads back correctly on EC and CPU is not throttled. explicitly asserting PROCHOT gpio on EC throttles CPU. Change-Id: Ie44352855d36f43f5767a99684dd17a509826190 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1107121 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: enable hibernate wake sources using PSLCaveh Jalali2018-06-191-4/+5
| | | | | | | | | | | | | | | | | this enables the PSL (power switch logic) on the EC to wake the system from hibernate. BUG=b:110237370,b:110062739 BRANCH=none TEST=verified atlas wakes up on AC-in Change-Id: Ifc0f5a73aeaca8f988afcc0f831fb062a92d8b28 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1098530 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* atlas: power down system at PMIC on hibernateCaveh Jalali2018-06-192-1/+27
| | | | | | | | | | | | | | | | this turns off most of the power rails at the PMIC in response to a system hibernate request. BUG=b:110237370 BRANCH=none TEST=verified both the AP and EC power down Change-Id: Ica830e15dfd2f80a3392afe29a079faa5e4d6ec9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096485 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* atlas: do not fake power-on as reset-pinCaveh Jalali2018-06-161-1/+0
| | | | | | | | | | | | | | | | | atlas can detect a power-on reset, so we don't need to fake it as a reset-pin initiated reset. BUG=b:75070158 BRANCH=none TEST=EC now claims the reset cause was power-on instead of reset on cold boot Change-Id: I0b0a58f79b605e768719249f1c139f6d46fec30b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1098531 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: configure GPIOC2 as PWM1Caveh Jalali2018-06-122-2/+2
| | | | | | | | | | | | | | | | | on the npcx7, GPIOC2 is a bit special because it has 2 alternate modes. we want the PWM1 mode instead of I2C6, and that's selected using a special #define. BUG=b:94613023,b:78309559 BRANCH=none TEST=apshutdown still works Change-Id: Ibd8baa15640344ce6c48b2c849e0d9fe6ce4239f Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090320 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: set PROCHOT# GPIO pin to 1.8vCaveh Jalali2018-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | set the input level for the PROCHOT# signal to 1.8v. the signal is actually pulled up to 1.0v on the board so it has always read as 0 with the default 3.3v GPIO setting now, with the 1.8v pin configuration, it actually reads as a 1: > gpioget ec_prochot_odl 1 EC_PROCHOT_ODL > BUG=b:109846359 BRANCH=none TEST=read back gpio pin state from EC console Change-Id: Ibd25fdb10b15e42a03e460a43c118d1bc8971281 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1090319 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: config PCH_PWR_BTN as push-pullCaveh Jalali2018-06-052-2/+2
| | | | | | | | | | | | | | | | | we don't have a pullup on PCH_PWR_BTN, so just configure it as push-pull. BUG=b:78309559 BRANCH=none TEST=able to power down/up the AP Change-Id: I791bfe3fb1c168ac72762f748f744cfbe771169b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1086470 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* atlas: fix GPIOC2/PWM1 functionCaveh Jalali2018-06-051-1/+1
| | | | | | | | | | | | | | | | | | we do not need to configure alt function on GPIOC2 to get PWM1 functionality. alt function here actually means I2C6_SCL0 and that also affects the function of GPIOC1/I2C6_SDA0 which is definitely not what we want. BUG=b:94613023 BRANCH=none TEST=able to power-off the AP Change-Id: I68abfb7e8c64faffbe0cea0a2cc8ca6a4a620ba3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1086469 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: board version 1 supportCaveh Jalali2018-06-014-49/+23
| | | | | | | | | | | | | | | | | | | these changes reflect the hardware changes made between version 0 and version 1 of the atlas board. note: these changes are not backward compatible - version 0 of atlas is no longer supported. BUG=b:78309559 BRANCH=none TEST=works fine on atlas version 1 Change-Id: Ia519f161c66066e02e9ddce7560a8fe2b7e74882 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1045730 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: improve discharged battery handlingCaveh Jalali2018-05-301-82/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | we normally try to find out a few things about a battery (like charge level) before actaully applying charging power to it. when the battery is completely discharged, the controller on the battery can't respond as it is not self-powered. so, we have to avoid all operations that depend on the battery responding in the battery discovery/initialization path. as long as we report that a battery is present and it is not responsive, the charger task will enter ST_PRECHARGE which means it'll provide a "precharge" current to the battery to try to talk to it. this allows the battery's controller to report battery parameters allowing our charger task can do the right thing. BUG=b:79354967 BRANCH=none TEST=atlas now discovers the discharged battery reliably Change-Id: I5e5a3abda07508eb791b712fb2f9b9f5fe383e07 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1065492 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* espi: rename remaining eSPI optionsJett Rink2018-05-231-1/+1
| | | | | | | | | | | | | Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067513 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* espi: convert all eSPI board to use CONFIG_HOSTCMD_ESPIJett Rink2018-05-221-2/+1
| | | | | | | | | | | | | | Convert all boards that use both CONFIG_ESPI and CONFIG_LPC to only use the CONFIG_HOSTCMD_ESPI option. BRANCH=none BUG=chromium:818804 TEST=entire stack works with lpc and espi Change-Id: Idd1519494a4f880b7b2018d059579d50c5461fcf Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067499 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* atlas: keep discharged battery powered during prechargeCaveh Jalali2018-05-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | when we wake up a discharged battery using the "precharge current", it briefly requests requests (0 vols, 0 amps) - presumably while its controller is trying to figure out what's going on... we respect this and stop charging, but that's probably a really bad idea since the battery has had very little chance to accept enough charge to self-power its controller. enabling "REQUESTS_NIL_WHEN_DEAD" gets around that. BUG=b:79354967 BRANCH=none TEST=instrumented code to verify we override the 0 amps request when battery is at 0% charge Change-Id: I1e15e5106ae5cdda94bd1bfd02132b300c9c4665 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067010 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* atlas: ignore unavailable battery temp readingsCaveh Jalali2018-05-211-1/+5
| | | | | | | | | | | | | | | | | | | | | the battery temperature field is only valid after we've actually managed to read the battery temperatore parameter. so, if the temp field is marked "BAD", don't even look at it. this addresses a case where we were removing charge current during the precharge phase - basically removing charge current from a battery that we're trying to power so we can talk to its I2C controller. BUG=b:79354967 BRANCH=none TEST=instrumented code to verify we don't request 0 amps in ST_PRECHARGE Change-Id: I3b40903506fa949c14ecaf577f134f31cfcf8fb7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1066789 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* atlas: add pullups to TCPC interrupt pinsCaveh Jalali2018-05-181-2/+2
| | | | | | | | | | | | | | | | there are no pullup resistors on the TCPC ALERT# pins and none on the board, so we need to turn on internal pullups on the EC side. BUG=b:75070158 BRANCH=none TEST=board still boots Change-Id: I15a7940d8b647b83c6ae304171c4a7c46b920529 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1059870 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: config PROCHOT GPIO as inputCaveh Jalali2018-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | we need to configure EC_PROCHOT_ODL as an input because the EC isn't driving it correctly. we changed the polarity of EC_PROCHOT for atlas and similar boards, but the EC codebase has this hard-coded as active-high. this is a short-term fix until we implement a more general PROCHOT "polarity" feature. BUG=b:78911901,b:79266467 BRANCH=none TEST=checked voltage drop across in-line resistor on EC_PROCHOT and AP can now run above 400MHz Change-Id: I8c3224c62ea7af4f386062d39c248d418e73fa53 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1045556 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* atlas: update GPIO names to match new schematicsCaveh Jalali2018-04-202-15/+15
| | | | | | | | | | | | | | | | | | the latest schematics have been updated to reflect the I2C bus numbering used in the chip datasheets. this updates the software to be consistent with the new datasheets. this is only a renaming exercise, there are no physical changes to the board. BUG=b:75070158,b:78309559 BRANCH=none TEST=it compiles Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020721 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: manage USB-C high speed muxesstabilize-10569.BCaveh Jalali2018-04-122-0/+23
| | | | | | | | | | | | | | | | | | this adds control over the USB high speed muxes as a function of DP HPD. this allows an external monitor to be added/removed with chromeos extending the display as appropriate. BUG=b:77151172 BRANCH=none TEST=chromeos detects external monitor plugin and extends display Change-Id: I7df7a8136ddaa4eeaca800d29b46350dafd8f838 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1009208 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* atlas: Add new boardDuncan Laurie2018-04-067-0/+1815
This is based on the initial code from Caveh here: https://chromium-review.googlesource.com/959861 Most things are functional, with some workarounds for P0 boards. The type-c hotplug is not working in this commit, the HPD will be run from the tcpm in the next board build. For now we might be able to get it working on P0 with some more tweaking.. The other known issue is that the battery takes ~2 seconds to come back online after a cutoff (the auto-power-on timeout is one second so the board will not power on like it should) and sometimes the battery is not responding properly on i2c and it requires an EC reset. BUG=b:75070158 BRANCH=none TEST=tested on P0 boards Change-Id: I438cb93b78d6f501426842d6cbe3d6a994563358 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982498 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
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