summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* rambi: use gpio for SCI# assertiontest-4980.Bstabilize-R33-4982.BAaron Durbin2013-11-182-1/+3
| | | | | | | | | | | | | | | | | | For some reason the SCI# is not working properly when the LPC module controls the pad. Instead, utilize CONFIG_SCI_GPIO option and put that GPIO pad into open-drain mode. BUG=chrome-os-partner:24003 BRANCH=None TEST=Built and booted rambi with dependency change. 'lidclose' and 'lidopen' cause ACPI interrupts. Change-Id: I5df455bc2fc9af4c43517a93c5a35dc598fd54e9 Reviewed-on: https://chromium-review.googlesource.com/176805 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org>
* lm4: allow the lpc module to use GPIO for SCIAaron Durbin2013-11-152-0/+9
| | | | | | | | | | | | | | | | | | The LPC module has a dedicated control for SCI#. However, certain situations require a dedicated GPIO for asserting the SCI# signal. Introduce CONFIG_SCI_GPIO to meet this requirement. BUG=chrome-os-partner:24003 BRANCH=None TEST=Built and booted rambi with dependency change. 'lidclose' and 'lidopen' cause ACPI interrupts. Change-Id: I34c5f0ba5ff60151972921f251c71d3769a9ef8b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176804 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: declare all host utils source dependencies in build.mkVincent Palatin2013-11-143-9/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of hardcoding the common files for host utils in the generic rules, let's declare them in the build.mk file using the same system as the Linux kernel build. if a binary "foo" declared in "host-util-bin" or "build-util-bin" has a matching "foo-objs" variable, it will be build from all objects declared in "foo-objs" else it uses directly "foo.o" (single source file). This is preparatory to add new "build" tools sharing common sources. note: the dependencies on the utils are a bit less fine-grained as a result of this change, but given the low number of tools, that should be acceptable. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=./util/make_all.sh Change-Id: Ieffce7ca6f5b685ffb7d1f4626b99aff07b61443 Reviewed-on: https://chromium-review.googlesource.com/176174 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Remove the printf prompt in idle task.Louis Yung-Chieh Lo2013-11-131-7/+0
| | | | | | | | | | | | | | A cprintf could increase 96+ bytes of stack usage and may overflow the stack of idle task, which is 256 bytes on stm32. BUG=chrome-os-partner:23982 BRANCH=nyan TEST=verified on nyan Change-Id: If96a1c51010116a2b4f3d67481ec0acc7bf78dd9 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176619 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus: Fix ACOK buffer on chipset state transitionsDuncan Laurie2013-11-132-0/+11
| | | | | | | | | | | | | | | | | | | | The ACOK buffer from EC to PCH was not being triggered when the chipset powers up or down, instead it was only triggering when AC state was changed. Since we want it to be driven in S5 I added HOOK_CHIPSET_PRE_INIT to the power sequence in the G3S5 state transition. BUG=chrome-os-partner:23752 BRANCH=none TEST=power on samus proto1b with AC inserted and see PCH_ACOK go high, power off and see it go low again. Ensure that it is also changed with AC state transitions. Change-Id: I4cbe123322e234dc07f10fd1cdff5a8b771a4e02 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176630 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add boardversion command to ectoolChromeOS Developer2013-11-132-0/+19
| | | | | | | | | | | BRANCH=none BUG=chromium:318342 TEST=Run "ectool boardversion" on device with and without support for board ID. Note, boards without support will return an error. Signed-off-by: Dave Parker <dparker@chromium.org> Change-Id: Ib7599570c84a7ed5cf70ce9d8336467785b35569 Reviewed-on: https://chromium-review.googlesource.com/176543
* samus: Fix backlight panel interruptDuncan Laurie2013-11-132-5/+7
| | | | | | | | | | | | | | | | | | The backlight_interrupt() function is defined to NULL if the magic CONFIG_BACKLIGHT_REQ_GPIO is not defined. Enabling that exposed an issue where the backlight workaround was attempted in interrupt context and should instead be deferred since it involves i2c transactions. BUG=chrome-os-partner:23752 BRANCH=none TEST=build and boot on samus proto1b and see recovery screen Change-Id: Id1377033c791a5c279fdb4faeecc4b2c0d142eaa Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176514 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Specify I2C channels physically, not arbitrarilytest-4824.BBill Richardson2013-11-118-33/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In board.c, we initialize this struct: struct i2c_port_t { const char *name; /* Port name */ int port; /* Port */ int kbps; /* Speed in kbps */ }; extern const struct i2c_port_t i2c_ports[]; The port field refers to the physical I2C bus on the EC. Meanwhile, in board.h, we've identified the bus where each I2C device is attached: Up until this CL, we've been picking one of those device-to-bus macros to initialize port fields of the i2c_ports[] array. That's wrong and confusing. This change specifies the physical channel with the physical number. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Renaming only. There should be no change in observed behavior. Change-Id: I5427c26290572133f060b6cf0d9ebea5015adba1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176176 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* Use explicit sizes for lightbar_params fields.Bill Richardson2013-11-111-9/+9
| | | | | | | | | | | | | | | | | | | | | | | The struct lightbar_params used to communicate lightbar settings between the AP and the EC uses just "int" for some of its fields. The AP currently uses 32-bit values for "int" in both 64-bit and 32-bit mode, but that's just luck since C only requires that "int" be at least 16 bits. This change makes the size explicit. BUG=none BRANCH=none TEST=manual There should be no visible change. ectool lightbar params > /tmp/foo ectool lightbar params /tmp/foo Change-Id: I4d77c16b3c68e179292b824938d2d012e917ad13 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176364 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* rambi: Add low power idle to rambiAlec Berg2013-11-093-5/+31
| | | | | | | | | | | | | | | | | | Added low power idle functionality to rambi but left it off by default. To turn it on, define CONFIG_LOW_POWER_IDLE in rambi's board.h file. BRANCH=none BUG=chrome-os-partner:23947 TEST=Verified that the EC does not go into deep sleep when in S0, and that it does go into deep sleep in S3, S5, and G3. Tested to make sure that flashec works when the EC is in low speed deep sleep. Also verified that the EC console times out after the timeout period and that it wakes up on the next command. Did not measure power usage. Change-Id: I0ab1a2dc7ca7ae4577fe5d0894c1bf82205dfea6 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176159 Reviewed-by: Todd Broch <tbroch@chromium.org>
* Take XPSHOLD back.Louis Yung-Chieh Lo2013-11-083-21/+5
| | | | | | | | | | | | | | | | | | | | | The XPSHOLD is not floated. It connects to +1.8V_VDDIO, which indicates high when AP is on. So, bring it back. Also remove the duplicated GPIO definition (GPIO_PWR_LED1). Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> BUG=chrome-os-partner:23929 BRANCH=nyan TEST=verified on nyan. successfully boot up the machine. Change-Id: I293a899bcdf255f36f6117627f66ed8231c9a70f Reviewed-on: https://chromium-review.googlesource.com/176046 Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Yung-chieh Lo <yjlou@chromium.org> Tested-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add EC_MEMMAP_ALS, update it once per secondBill Richardson2013-11-083-12/+44
| | | | | | | | | | | | | | | | | | | | | | This adds space for up to two ALS lux readings to be available to the AP through the memory-mapped LPC region. If enabled, the values are updated once a second. The ALS will be reinitialized at every AP resume, since it's typically unpowered otherwise. The reported value will be zero when the ALS is off. BUG=chrome-os-partner:23380 BRANCH=samus TEST=manual Boot the AP, then from the EC console run "als" or just monitor the memory-mapped region directly ("rw 0x40080780" on Samus), while pointing the sensor at bright and dim areas. The value should change. Change-Id: I705371fcd57345dc9adae1231ea30c7ff024aaf8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176142 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ite: Added functionality to ITE In-system programming tool.Alec Berg2013-11-081-84/+255
| | | | | | | | | | | | | | Added ability to erase and program flash to iteflash. BRANCH=none BUG=chrome-os-partner:23576 TEST=generate random 192kB file, write it to the ITE chip, read flash back and make sure file read in matches file written. Change-Id: Id525b43e523a3d710ee65b623fec07800cf7f347 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176022 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add ALS driver for light sensors connected to ECBill Richardson2013-11-079-0/+184
| | | | | | | | | | | | | | | | | This adds the driver and a console command to read an Intersil ISL29305 light sensor connected to the EC. BUG=chrome-os-partner:23380 BRANCH=samus TEST=manual Run the "als" command from the EC console, while pointing the sensor in various directions. It should give higher numbers when facing a light source. If you get "Error 1", it means the ALS isn't powered. Change-Id: I855ed64dab7fc60e29126ab3e97669be24dc6a64 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176056
* stm32: Don't use a stack buffer for i2c_read_string()Randall Spangler2013-11-072-17/+15
| | | | | | | | | | | | | | | | | | We read a counted string (byte 0 = count, bytes 1 - count = chars) and convert it to a null-terminated string. Since both have a 1-byte overhead, we can use the destination buffer instead of using a stack-based buffer. BUG=chrome-os-partner:23928 BRANCH=none (pit is affected, but battery console command isn't used on end user systems) TEST=battery command shows correct strings (SDI / 4302D40 / LiP), and doesn't stack overflow. Change-Id: Ic0f111cde2d57b41d6ce9287e0c771acc09a8869 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176116 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move core-specific toolchain configuration to core/ directoryVincent Palatin2013-11-077-5/+26
| | | | | | | | | | | | | | | | This is preparatory work to introduce a second core architecture. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=./util/make_all.sh Change-Id: Icae8a7e475a4ba2a13f0d8f95629e8498a5a61da Reviewed-on: https://chromium-review.googlesource.com/175419 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Enable stack overflow checking on all context switchesRandall Spangler2013-11-074-7/+50
| | | | | | | | | | | | | | | | | | | | | | | | Changes somewhere in the recent past have caused I2C operations to consume more stack space. The current failure mode is that after some debug command or infrequent battery operation, the system fails. Clean up and enable stack overflow detection by default, and add a debug command (disabled by default) to verify overflow detection works. This adds several instructions to each context switch, but it's still fairly inexpensive, and represents only a few percent increase in the size of svc_handler(). That's better than silent failures. BUG=chrome-os-partner:23938 BRANCH=none TEST=Enable CONFIG_CMD_STACKOVERFLOW, then run the 'stackoverflow' command. This should cause a stack overflow to be detected in the CONSOLE task. Change-Id: I9303aee5bd9318f1d92838b399d15fb8f6a2bbf9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176113 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ite: Add IT8380 In-system Programming toolVincent Palatin2013-11-072-1/+774
| | | | | | | | | | | | | | | | | | | | use the IT8380 SMB0 interface connected to the Servo FTDI chip to access the internal flash. The write-protect is not implemented. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Alec Berg <alecaberg@chromium.org> BRANCH=none BUG=chrome-os-partner:23576 TEST=check waveforms on the Logic analyzer. Change-Id: Ic3402e4e8def731fe4f2fe93be254f5fd0982abf Reviewed-on: https://chromium-review.googlesource.com/175677 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Cleanup: only compile battery_vendor_params() when enabledBill Richardson2013-11-051-34/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bolt uses Link's battery, but doesn't override the smart battery charge profile with CONFIG_BATTERY_VENDOR_PARAMS. But the image still compiles and includes the battery_vendor_params() function, although it's never called. This CL stops doing that. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build all targets. Confirm that Link still has battery_vendor_params(): $ make BOARD=link $ nm build/link/common/charge_state.o | grep vendor U battery_vendor_params $ nm build/link/driver/battery/link.o | grep vendor 00000009 T battery_vendor_params $ Confirm that Bolt does not have battery_vendor_params(): $ make BOARD=bolt $ nm build/bolt/common/charge_state.o | grep vendor $ nm build/bolt/driver/battery/link.o | grep vendor $ Change-Id: I48a535208bdcfd3d2cb26f6f15a28a728dbe4d0b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175731 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Show smart battery status with 'battery' commandBill Richardson2013-11-054-4/+33
| | | | | | | | | | | | | | | | | | | | | | | The smart battery status register holds some useful info. This displays it along with all the other stuff. This decodes the alarm and status bits, but not the error code, since that field is only valid immediately after a failed i2c transaction (that's how the battery indicates error). Since we do all sorts of automatic battery probing in other threads, that value will never be reliable when we run the "battery" console command. BUG=none BRANCH=none TEST=manual Run "battery". You should see a new line amongst the output: Status: 0x00c0 DCHG INIT Change-Id: I5e684198af2cf7767f89786c91a7d946ad95d4c2 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175659
* lm4: Fixed low power idle doesn't always wake up.stabilize-4920.6.Brelease-R32-4920.BAlec Berg2013-11-052-12/+32
| | | | | | | | | | | | | | | | | | | | | Temporary fix to the bug in which we miss wake events when in deep sleep with the LFIOSC (32kHz) clock and the EC is cold. This fix involves simply using a faster clock, 250kHz, when in low speed deep sleep. This fix consumes more power but solves the bug. Renamed EC console command dsleepmask to dsleep. BRANCH=none BUG=chrome-os-partner:23678 TEST=Go in to low speed deep sleep by going into either S3 or G3 and letting the EC console timeout. Then freeze-spray the EC chip. Wake up the EC via the console and make sure that the idlestats show that we have not missed a deadline. Change-Id: I4f9844f1937bc8c95cf1540502f7d8fb4cbc097e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175614 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rambi: Set correct input current limitRandall Spangler2013-11-051-2/+1
| | | | | | | | | | | | | | Rambi has a 65W adapter, so shouldn't be asking for 4A @ 19V. BUG=chrome-os-partner:23597 BRANCH=none TEST=charger command shows I_in = 3392 mA (which is the closest step below 3.42A that the charger can set). Change-Id: I4b044b594566a6abcb94c3f674a0d287c8fc2b30 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175611 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add TODO for TODO_XPSHOLD.Louis Yung-Chieh Lo2013-11-051-0/+1
| | | | | | | | | | | | | | | | The TODO line was accidentally removed in the last CL. BUG=None TEST=None BRANCH=None Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Change-Id: Ia37e0f6bf21e072c714512d2eaa7ad69ef5fad93 Reviewed-on: https://chromium-review.googlesource.com/175632 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Yung-chieh Lo <yjlou@chromium.org> Tested-by: Yung-chieh Lo <yjlou@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Pad jump tags to 4 bytes inside the system moduleRandall Spangler2013-11-058-15/+44
| | | | | | | | | | | | | | | | | | | | | | | That way all the users of jump tags don't need to know about the padding requirements. BUG=chrome-os-partner:23851 BRANCH=none TEST=enable CONFIG_CMD_JUMPTAGS, then 'jumptags'. Output should be something like this: 20007fbc: 0x5550 UP.1 2 20007fc4: 0x4b42 KB.2 3 20007fcc: 0x4c50 LP.1 12 20007fdc: 0x4d54 MT.1 8 All the addresses in the first column should be word-aligned. The sizes in the last column don't need to be a multiple of 4. Change-Id: I91f9c29701a007ef8a56b5b7e0ea09930dfbea31 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175591 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Clean up hook priorties on LM4Randall Spangler2013-11-045-4/+5
| | | | | | | | | | | | | | | | | | | | Fan no longer needs a special priority to wait for the host memmap to become available, since LPC inits earlier. I2C and PECI don't need explicit ordering on freq change. Thermal now uses the explicit prio for temp sensors done. Commented hook test. BUG=chromium:314768 BRANCH=none TEST=boot link; enable/disable PLL; verify fanset and temps commands work afterwards. Change-Id: I71766614dff2950dd307acd0635405e6b59e330a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175601 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Refine GPIO list of Nyan.Louis Yung-Chieh Lo2013-11-043-9/+31
| | | | | | | | | | | | | | Refine the GPIO list according to the schematic. Comment out the XPSHOLD in power/tegra.c for compiling. Will fix later. BUG=None BRANCH=None TEST=emerge-nyan chromeos-ec && make runtests -j 32 && make BOARD=nyan tests -j 32 Change-Id: Id0d682fd5d48e8a8a07785e86c07f45f07d866ab Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175534
* cleanup: Yes, even more TODO commentsRandall Spangler2013-11-049-34/+61
| | | | | | | | | | | | | Almost done. Comment changes only. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I974dfc12aa264e2035b3bae35a089c19344e7d45 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175484 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: configure both fansBill Richardson2013-11-022-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Modify board.h and board.c to describe both fans. BUG=chrome-os-partner:23530 BRANCH=samus TEST=manual Power things up, poke at the fans through the EC console. Observe that they're both working and controllable: faninfo fanset 0 2000 faninfo fanduty 1 30 faninfo fanauto 0 faninfo fanauto 1 faninfo Change-Id: I2ba9356f084be12dab0fe0b9a004f66feace1878 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175369
* cortex-m: ensure we use the right subset of the instruction setVincent Palatin2013-11-023-2/+6
| | | | | | | | | | | | | | | | | | | | | | | Cortex-M3 and Cortex-M4 are not using exactly the same instruction set. Cortex-M3 is using ARMv7-M ISA which is a subset of the ARMv7E-M used by the Cortex-M4 core (even though the delta is small). Let's restrict each core to the right subset of instruction by pushing the -mcpu/-march configuration in the chip specific area. Note: GCC 4.8 is now using the full ARMv7E-M instruction set and will emit "undefined instruction" on Cortex-M3 without this patch. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:314194 TEST=build *and* run on Spring and Link. Change-Id: I2f9b87fec689e8d1097809cab437a2bd32dfa194 Reviewed-on: https://chromium-review.googlesource.com/175487 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Provide multiple fan support within the EC itselfBill Richardson2013-11-028-105/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds explicit "int fan" args to the exported functions from common/fan.c: fan_set_percent_needed() and fan_percent_to_rpm(). Within that file, multiple fans are handled independently. This is not complete, though. Host commands and sysjump support still only handle a single fan, so at the moment multiple fans are treated identically in those cases. BUG=chrome-os-partner:23530 BRANCH=none TEST=manual All boards build, "make runtests" passes. On a multi-fan system, the EC command "faninfo" displays multiple results: > faninfo Fan 0 Actual: 0 rpm Fan 0 Target: 0 rpm Fan 0 Duty: 0% Fan 0 Status: 0 (not spinning) Fan 0 Mode: rpm Fan 0 Auto: yes Fan 0 Enable: yes Fan 1 Actual: 0 rpm Fan 1 Target: 0 rpm Fan 1 Duty: 0% Fan 1 Status: 0 (not spinning) Fan 1 Mode: rpm Fan 1 Auto: no Fan 1 Enable: no > and the "fanduty", "fanset", and "fanauto" all require the fan number as the first arg: > fanduty 0 30 Setting fan 0 duty cycle to 30% > fanset 1 2000 Setting fan 1 rpm target to 2000 > fanauto 0 > fanauto 1 On single-fan systems, there is no visible change. Change-Id: Idb8b818122e157960d56779b2a86e5ba433bee1b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175368 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Still more TODO commentsRandall Spangler2013-11-029-38/+59
| | | | | | | | | | | | | More of same. Comment changes only; no code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I8c42ed7d332cd9d461067e1aeac670855106cbcd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175405 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Verify data buffer is aligned for flash writesRandall Spangler2013-11-021-0/+4
| | | | | | | | | | | | | | | | | | | All the current data buffers *are* aligned, but we should check anyway just to avoid unpleasant surprises in the future. This matches what we do on STM32L. On STM32F, we copy a byte at a time so alignment of the source data doesn't matter. BUG=chrome-os-partner:9526 BRANCH=none TEST=manual flasherase 0x20000 0x1000 flashwrite 0x20000 0x200 -> succeeds flashwrite 0x20201 0x200 -> fails Change-Id: Id1a0fd8f6871e1fcdc3f55ec25eea40f33b5214c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175532 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: ADC clock management bug fixAlec Berg2013-11-011-3/+27
| | | | | | | | | | | | | | | | | | | | | | | Fixed bug in which two different tasks reading two different ADC channels could interfere and cause the ADC clock to get disabled when a read is still in progress, thus causing a reboot. Added a runtime assert to verify that developers don't sample the same ADC channel from multiple different tasks, which could cause hard to trace reboots. BRANCH=none BUG=chromium:313872 TEST=1) Added console command to continuously read an ADC channel not read anywhere else. Verified that when running this console command I could reproduce the bug every few minutes. 2) Wrote code in adc.c to protect the ADC clock resource. 3) Ran console command from step 1 for ~2 hours with no reboots. Change-Id: Ic1905dde12871a4b93957702f7f31a25a2762bb4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175404 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Even more TODO commentsRandall Spangler2013-11-0113-32/+38
| | | | | | | | | | | | | | | Update comments with more info, or remove if no longer applicable. No code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I5b56eeb500bc0f00e84e91ef99684f4b1b310972 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175418 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Update more TODO commentsRandall Spangler2013-11-016-31/+50
| | | | | | | | | | | | | | | Add bug links, reword, or remove as applicable. No code changes, just comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175326 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Improve / remove more TODO commentsRandall Spangler2013-11-016-22/+25
| | | | | | | | | | | | | Add bug references. Remove one assert that can no longer be triggered. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I3f4d2e4f2f3343a8d0531cb0715d151eaa4d0b50 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175293 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: Changes for Proto1bDuncan Laurie2013-11-016-25/+90
| | | | | | | | | | | | | | | | | | | | - disable PP1800_PGOOD internal pullup - add PP3300_DSW_EN control on PF6, turned on in S5 and off in G3 - change PCH_WAKE_L and PCH_PWRBTN_L to open drain signals - add PCH_BL_EN interrupt on PM3 for rising edge to put backlight controller into PWM mode, remove 1 second hook - add samus-specific extpower handler for AC_PRESENT to buffer the AC_PRESENT input to the new PCH_ACOK output on PM6. this is driven high in S5/S3/S0 when AC_PRESENT is high, otherwise driven low. BUG=chrome-os-partner:23752 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: Ie8ab538610e41914212ee1f3a6287b63474fb85b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175281 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Ignore failures in HWTest and VMTest in the commit queue.David James2013-11-011-0/+12
| | | | | | | | | | | | | | | Right now, firmware changes are rejected if the HWTest or VMTest stages fail. This is unnecessary as firmware changes are very unlikely to break these stages. BUG=chromium:285940 BRANCH=none TEST=none, this is just copied from the coreboot repository Change-Id: Id7ccff542b8abada41072ef26cd2b7d3ae179fd3 Signed-off-by: David James <davidjames@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175410 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Use actual Thumb2 SVC instruction instead of hard-coding the opcodeRandall Spangler2013-11-011-6/+2
| | | | | | | | | | | | | | | The current chroot toolchain properly compiles the SVC instruction, so there's no need to hard-code the opcode. That was a workaround for binutils < 2.22 (that is, binutils versions more than 2 years old). BUG=chrome-os-partner:23721 BRANCH=none TEST=compare EC binaries before/after this change; only the datestamp should be different Change-Id: I9c6282768c4562926397866ac3be218c393e3865 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175172
* cleanup: TODOs in ec_commands.hRandall Spangler2013-10-312-4/+10
| | | | | | | | | | | | | Comment changes only; no code changes. BUG=chrome-os-partner:11223 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I8f6f57514886dd1fda0e44cae1b036c22be481f8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175228 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: TODO comments in extpower_springRandall Spangler2013-10-313-13/+24
| | | | | | | | | | | | | | | No code changes, just comment fixes. Added config #ifdefs for the debug commands as requested; they're enabled for Spring, so functionality is unchanged. BUG=chrome-os-partner:18343 BRANCH=none TEST=build spring; see that ilim and batdebug commands still exist Change-Id: I7c9f12281afa7ec68aa7e62dcfcd51682d88a16a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175216 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Replace Makefile 'tags' target with 'xrefs', clean it upBill Richardson2013-10-311-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a 'xrefs' target to create various cross-reference files from the EC sources. In particular, it generates these files in the target build directory: cscope.files - for the cscope browsing tool TAGS - for emacs tags - for vi It parses the dependency files generated by a build, so that only those source files actually used to create the EC binary are scanned. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Inside the chroot: make BOARD=link xrefs ls -l build/link/cscope.files If you install the ctags and etags programs in the chroot, you should also see build/$BOARD/tags or build/$BOARD/TAGS, respectively. If those programs don't exist, those steps will be silently skipped. Note: You can install ctags with "sudo emerge ctags". AFAICT, installing etags requires the entire emacs suite, so it's probably simpler to just copy the etags binary from your build host into the chroot's /opt/bin/ If you don't have ctags or etags in the chroot, you can still run make BOARD=link CROSS_COMPILE= xrefs outside the chroot, provided you've built the EC image first. Change-Id: I8e16ef19b0f4e79aba887c308e58982fef8fa21f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175224
* cleanup: Assorted TODO commentsRandall Spangler2013-10-319-44/+62
| | | | | | | | | | | | | | | Remove comments if no longer applicable, or assign bug numbers if they still are. Tidy some debug output. No code changes other than the debug output. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms, pass unit tests Change-Id: I2277e73fbf8cc93f3b1b35ee115e0f2f52eb8cf9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175215 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: mkbp keyboard moduleRandall Spangler2013-10-306-13/+18
| | | | | | | | | | | | | | | | | | | Rather than compile it by default for host-based tests, only compile it for the few tests that actually use it. Since those (and all boards) now only use if if they also have a keyscan task, we can get rid of the #ifdefs in keyboard_mkbp.c as well. And remove a TODO we'll never do... BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests. These pass: util/make_all.sh make BOARD=pit tests Change-Id: I44d1806cfb375027a7ed0b33a5e9bdbbed8ccddc Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174513
* Separate fan_t from pwm_tBill Richardson2013-10-3019-124/+139
| | | | | | | | | | | | | | | | There is a logical difference between PWM controls for things like backlights and fan controls for actual fans. This change separates them into two different data structures, for better abstraction. BUG=chrome-os-partner:23530 BRANCH=none TEST=manual make runtests, make all boards, test on Link and Falco. Change-Id: Ib63f2d1518fcc2ee367f81bf5d803360c1aa5c76 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175151
* Rename CONFIG_FAN to CONFIG_FANSBill Richardson2013-10-3012-14/+14
| | | | | | | | | | | | | | | | | | Instead of just configuring fan support as yes/no, we'll use it to specify the number of fans on the board. Undefined (not zero!) means no fan support at all. Syntax change only. No new functionality. BUG=chrome-os-partner:23530 BRANCH=none TEST=manual make runtests, build all platforms, build and test on Link. Change-Id: Iff65efa69e05f3e1a54fdc2a8da9001b4e8487ca Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175150
* Add more descriptive comments to include/fan.hBill Richardson2013-10-301-1/+13
| | | | | | | | | | | | Just adding some comments. BUG=chrome-os-partner:23530 BRANCH=none TEST=none Change-Id: Ib3955e9d97ad8aa642e6fe298c17e34d2c66fb1c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175139
* Separate common fan behavior from implementationBill Richardson2013-10-3017-508/+560
| | | | | | | | | | | | | | | | | | This looks like a lot, but it's really just moving the non-board-specific stuff from chip/lm4/fan.c into common/fan.c, updating the appropriate headers, and renaming functions to better match the new location. This is entirely code refactoring and renaming. No new functionality. BUG=chrome-os-partner:23530 BRANCH=none TEST=manual make runtests, build all platforms, build and test on Link. Change-Id: I7dc03d6732bad83cf838a86600b42a7cff5aa7aa Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175012
* lm4: fix enabling RTC alarmRandall Spangler2013-10-302-1/+16
| | | | | | | | | | | | | | | | | | | | | | All hibernate register writes must wait for the WC bit. When we're enabling the RTC alarm, it's important to wait for the WC bit afterwards, too, or else we could go into deep sleep before the write to HIBIM is committed. Also make sure that the normal hibernate() path enables the RTC alarm if it has a timeout. This bug wasn't noticed until the low-power idle code called system_reset_rtc_alarm(), since before then HIBIM was initialized to 1 and just stayed there. BUG=chrome-os-partner:23678 BRANCH=anywhere we use low power idle (wolf/leon, too) TEST=with hacked firmware, note that HIBIM=1 just before the wfi instruction in chip/lm4/clock.c Change-Id: Ie01b106ac6a6c5894811f9a333715b22ef896f82 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175013 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lm4: Properly identify TM4 chip used on haswell/baytrail systemsRandall Spangler2013-10-301-6/+9
| | | | | | | | | | | | | | | This chip returns ver/family/partno = 0x10de, as indicated by the datasheet. Also switch the identification code to use a switch statement rather than re-reading the DID1 register in if-then-else. BUG=chrome-os-partner:23679 BRANCH=none (maybe haswell branches, but it's largely cosmetic) TEST=version command on rambi identifies the chip as ti tm4e1g31h6zrb B1 Change-Id: I4a3748413de65d3116feb7c444f5a2af5953eecd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175008 Reviewed-by: Vic Yang <victoryang@chromium.org>
View Lorry Controller Status