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* led_policy_std: turn off power led when system shutdownstabilize-9460.60.Bstabilize-9460.40.Bstabilize-9460.4.Bstabilize-9460.23.Bjames_chao2017-04-131-0/+8
| | | | | | | | | | | | | | | | | | The led is control by HOOK_SECOND, but if dut press ALT+VOL_UP+H, enter hibernate mode when system in s0, there is no one second to turn off the power led, so the power led is still on when system enter hibernate. BUG=b:36328757 BRANCH=gru TEST=press ALT+VOL UP+H, the power led turn off and system enter hibernate mode. Change-Id: I72d18876aa5468131bae7ad42203982d123db8ba Signed-off-by: james_chao <james_chao@asus.com> Reviewed-on: https://chromium-review.googlesource.com/476850 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hammer: Enable I2C passthroughNicolas Boichat2017-04-132-4/+14
| | | | | | | | | | | | | | This interface will be used to update the trackpad firmware. BRANCH=none BUG=b:35587174 TEST=make BOARD=hammer -j; flash hammer; lsusb -v -v shows I2C interface Change-Id: Ia4533c758f80eb786bd6dbb9f35feb66eb631793 Reviewed-on: https://chromium-review.googlesource.com/474667 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* hammer: Verify RW signature in a separate taskNicolas Boichat2017-04-111-0/+1
| | | | | | | | | | | | | | | About 864 bytes of stack is necessary for rwsig verification, so 1024 bytes should be enough. BRANCH=none BUG=b:35587171 TEST=Flash hammer, board boots to RW after 1s Change-Id: If71fb04ec16f16881d14fca2721303744fbce75a Reviewed-on: https://chromium-review.googlesource.com/468710 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tigertail: bugfix mux selectNick Sanders2017-04-111-2/+4
| | | | | | | | | | | | | | Don't clobber uart autodetect settings on detect. BRANCH=None BUG=b:35849284 TEST=ran on tigertail Change-Id: I608705b933272a902d5fff05c1b1a77162bf4c3c Reviewed-on: https://chromium-review.googlesource.com/461325 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kahlee: Modify PD port2 I2C address and clean up unused functionCloud_Lin2017-04-113-21/+1
| | | | | | | | | | | | | | | 1. PD vender suggests to use chip default address setting (0x16). 2. Clean up board_print_tcpc_fw version function and related define. BRANCH=None BUG=None TEST=Plug in type-c device and check behavior Change-Id: I44b7156c914b8de67630696e4534147cc3b7f2c3 Reviewed-on: https://chromium-review.googlesource.com/469449 Commit-Ready: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpm: anx74xx: Improvements to low power mode for S3/G3 chipset stateScott2017-04-116-17/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before entering standby mode, bit 7 (cable_det) or analog_ctrl_0 is cleared. This allows a new cable detect event to trigger the EC to put the ANX4329 into normal mode. However, in some cases such as when in S3/S5/G3 chipset power states a port will be in sink only mode and therefore won't attach when a sink only adapter is connected to the port. This results in the an indefinite toggle of standby<->normal mode transitions. This constant toggle floods the EC console and more importantly prevents the ANX4329 from remaining in standby mode and the power consumption remains at ~9.5 mW instead of ~1.2 mW when no adapter is connected. This CL adds logic around clearing the cable_det bit so that it's only cleared if both CC lines are open or if an Emark cable is attached. Emark cable is determined from the presence of Ra on one CC line and no Rd on the other CC line. The special consideration for an Emark cable is reqiured because when an Emark cable is connected, the USB PD auto toggle state may require some number of iterations until the attach event is recognized. In order to support handle cases where the drp mode is changed via either the EC console command or host command, added a call to tcpm_set_drp_toggle whenever the drp state is updated. Since the drp mode is updated upon chipset resume events, the chipset resume hook in board.c for anx74xx_cable_det_handler() became redundant and hence it was removed. BUG=b:35775019,b:35586188 BRANCH=reef TEST=Tested the following cases: - Sink, source adapters in chipset S0. Verified that adapters connected as expected. Also, used Emark cable to connect to both USB PD chargers (source) and Pixel phone (sink). - Run 'lidclose' on EC console then connect Type C -> A adatper [3490.370125 TCPC p0 reset!] [3490.389588 TCPC p0 Low Power Mode] It no longer toggles indefintely and after running 'lidopen' verified that port 0 is now in SRC_DISCOVERY. - In S3/G3 connected USB PD charger with regular and Emark typeC cable. Verified that port 0 is in SNK_READY state. - use 'pd dualrole sink' and test with Type C -> A adatper. Verified that tcpc wakes up, but goes into standby mode until entering 'pd dualrole on'. - When sink only adapter is connected in S3/G3, measure power level ~1.2 mW as opposed to ~10 mW in S0. - Repeated similar tests on port 1 (parade tcpc) to verify that adapters connected as expected. Change-Id: Ib8de666f72723934186fee7869f9dda01381c7a8 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/463991 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tcpm: anx74xx: Take ANX3429 out of suspend state before I2C accessScott2017-04-114-56/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cable_det signal is used to signal to the EC that the tcpc has detected a cable being connected when low power mode is configured. The driver then needs to take the tcpc out of suspend state by setting PWR_EN and RESET_N high. Then bit 7 of analog_ctrl_0 needs to be set properly. The code that is handling this transition was attempting to access the tcpc via I2C before putting the chip in normal mode when transitioning from suspend to normal. In addition there are issues with calling the driver function directly from the hook task (in the delayed ISR handler) and from the USB PD task. This CL changes the delay ISR handler to only set the TCPC_RESET indication so that the call to put the ANX3429 into normal from standby to normal mode only happens in the USB PD task. The TCPC_RESET event is only set if cable_det is high, but reset_n (to the ANX3429) is low which indicates that the ANX3429 is currently in standby mode. BUG=b:35775019 BRANCH=reef TEST=Manual Tested with various adapters in both S0 and S3/G3 chipset states. Verified that adapters connected as expected. When in S3/G3 connecting a sink only adapter still causes an indefinite toggle, but all calls into the driver are executed from within the USB PD 0 task and all ANX3429 I2C accesses work as expected. Change-Id: I6e4843e43f59afbf5ca3251feb68981b815c1c78 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/457103 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rwsig: Make it possible to run as a taskNicolas Boichat2017-04-114-20/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Optionally) split rwsig verification into a separate task. This allows us to initialize other components (e.g. USB) while the verification is in progress, speeding up the boot process to active USB in RO case. After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section if no action is taken by the AP (such as a forced request to jump to RW, or starting an update). Note: This comes with a ~36ms boot time regression, as other code gets to run before verification starts. BRANCH=none BUG=b:35587171 TEST=Flash, board boots to RW after 1s TEST=Change jump timeout to 5s, add 5s delay in check_signature, add console command to manually abort/continue rwsig verification. 'rwsig continue' works => Board jumps to RW after check_signature is completed (or immediately while waiting for timeout) 'rwsig abort' works => Board does not jump to RW. Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef Reviewed-on: https://chromium-review.googlesource.com/468709 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-1111-68/+87
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rollback: Update and lock rollback block as part of rwsig verificationNicolas Boichat2017-04-113-8/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done at RO stage. If the rollback region is unprotected, update it to match the version in the RW image. If the rollback region is protected, we can't do that update, so we wait for RW to unlock that region (presumably after AP has verified that image is somewhat functional) before updating it. BRANCH=none BUG=b:35586219 TEST=flashwp true; reboot => hammer reboots twice flashinfo shows RO+rollback protected: Flags: wp_gpio_asserted ro_at_boot ro_now rollback_at_boot rollback_now Protected now: YYYYYYYY YYYYYYYY Y....... ........ TEST=Hack version.c to add "+1" to rollback_version, check that RO updates ROLLBACK info block on first boot. TEST=Use hack above, convert rwsig to separate task, add 5000 ms delay in rwsig just before rollback information is updated. Then: Quickly type: flashwp true; reboot; flashwp all; reboot => Wait for system to jump to RW rollbackinfo => minimum version 0 flashwp norb; reboot; wait for jump to RW rollbackinfo => minimum version 1 Change-Id: I78e502315c611c5edaf34b8d70a12fedd3e57bdf Reviewed-on: https://chromium-review.googlesource.com/452816 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_updater: post a reset during upstart on old versionsMary Ruthven2017-04-071-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If Cr50 does not have support for invalidating the RW header and restoring it, then upstart should still post a reset. This changes usb_updater to post a restart during upstart if the RW minor version is less than 19. BUG=none BRANCH=cr50 TEST=manual Copy new usb_updater onto the DUT. run 'sync' Build two cr50 debug images one with 0.0.19 and one with 0.1.12 verify update process works test_that $DUT_IP -b $BOARD firmware_Cr50Update --args="old_release_image=$PATH_TO_PROD_13 release_image=$PATH_TO_PROD_18 dev_image=$DBG_IMAGE_19" Build a firmware image with https://review.coreboot.org/#/c/18946/3 test_that $DUT_IP -b $BOARD firmware_Cr50Update --args="old_release_image=$PATH_TO_PROD_18 release_image=$DBG_IMAGE_19 dev_image=$DBG_IMAGE_1_12" Change-Id: I811977de26999b1d26bd2d4126b88b1c55a93931 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/470326 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* servo_v4: Added dts_mode on/off control for DUT port connectionScott2017-04-074-80/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added a new static variable disable_dts_mode. By default, DUT port will attempt to connect as a DTS source. However, if disable_dts_mode is set via a console command, the DUT port will connect as a regular source device. Charging behavior is identical between the two modes. In DTS mode, Rp is presented on both CC lines. When it's disabled Rp is presented only on CC1. Added tables to support the appropriate VNC and RD voltage thresholds. BUG=b:36908939 BRANCH=servo TEST=Tested with new console command 'dts on|off'. If new mode equals the current mode, no action is taken. If the mode is different, then verified that DUT port connects as DTS following 'dts on' and regular SRC following 'dts off'. Verifed this when the command is issued when connected to the DUT or disconnected. Validated that the H1 console is present for DTS mode and not present when DTS mode is disabled. Change-Id: Ie649709d6b2bbe947708d05eac42fde61d2677a8 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/468447 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* eve_fp: tri-state pins connected to PCH during S3.Todd Broch2017-04-072-8/+32
| | | | | | | | | | | | | | | | | There's leakage through EC_INT when in S3 to the APs P3300_A rail. Changing the GPIO config to be an input all EC_INT and all the SPI slave pins during S3 removes the leakage. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, run int_test before & after suspend/resume successfully. Change-Id: I68e286c4770831544bea0d58ffa98185fd7ba788 Reviewed-on: https://chromium-review.googlesource.com/469527 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* system: Fixups in emulated sysrq codeNicolas Boichat2017-04-066-12/+18
| | | | | | | | | | | | | | | | Follow-up to CL:456520, addressing a few more comments. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I692afa7c911882f00d92b8e6d83889c52821e171 Reviewed-on: https://chromium-review.googlesource.com/468506 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: prefer CD pin assignments over EF for USBC->USBC case.Todd Broch2017-04-061-5/+8
| | | | | | | | | | | | | BRANCH=samus,glados,oak,gru,reef BUG=chromium:694597 TEST=manual, connect samus to USB-C monitor via cable and see it select pin assigmnent 'C' Change-Id: Iddad5b654715bd30ba081c62f8fb53e07816498c Reviewed-on: https://chromium-review.googlesource.com/465379 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_updater: /dev/tmp0 -> /dev/tpm0Brian Norris2017-04-061-1/+1
| | | | | | | | | | | | | That's a typo. BUG=none TEST=none BRANCH=none Change-Id: I4577a746c113b6c1d2c6745975272532909c8a8a Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/470507 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* usb_updater: only run send_done on usb transfersMary Ruthven2017-04-061-1/+2
| | | | | | | | | | | | | | | | show_fw_ver runs send_done on both usb and tpm transfers. This changes usb_update, so it will only run send_done on usb transfers BUG=none BRANCH=cr50 TEST=copy to dut. stop trunksd. Run 'usb_updater -f -s && usb_updater -f && usb_updater -f' Change-Id: I3a09c003ae41a4651c9961092552d7807656a68a Reviewed-on: https://chromium-review.googlesource.com/470169 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: print '.' every time cr50 resumes from sleepMary Ruthven2017-04-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | Right now there is no way to verify cr50 is asleep just by looking at the UART output. You can check by running taskinfo and seeing that the GC_IRQNUM_PMU_INTR_WAKEUP_INT irq count has increased or by measuring cr50 power. In the past we have had Cr50 issues that we think are related to sleep. Devices like poppy will have the Cr50 uart connected to servo, so we can capture the Cr50 console output. It would be helpful if there was an easy way to tell that cr50 is asleep from the UART output to more easily confirm issues might be related to sleep. This change will print '.' every time Cr50 resumes from sleep. Cr50 wakes up every half second for HOOK_TICK, so with this change '.' prints every half second while cr50 is asleep. BUG=none BRANCH=none TEST=boot a device, wait a while, and verify cr50 starts printing '.' every half second. Turn off the device and verify the '.'s stop. Change-Id: I94a82db00076062dbba2c3bc273cbe0731430520 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/463990 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-0612-3/+310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kahlee: initial board settingJimmy Wang2017-04-0513-0/+2151
| | | | | | | | | | | | | | | | | | | | 1. GPIO initial 2. board config 3. led control 4. power control of Stoney 5. battery setting BRANCH=None BUG=None TEST=power on device and test manually Change-Id: I14cc60bf2cdd40032b3cbdfacf68d7a3c17fe87c Reviewed-on: https://chromium-review.googlesource.com/461624 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Lin Cloud <cloud_lin@compal.com> Tested-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* eve: Disable sensors in S5Duncan Laurie2017-04-051-4/+4
| | | | | | | | | | | | | | | | The accelerometer sensors are not needed in S5, and having them get enabled early in boot is causing issues on a subset of boards. Similarly, the magnatometer is supposed to be disabled in S3/S5. BUG=b:36919184 BRANCH=none TEST=successfully boot on board that was previously failing Change-Id: I3c079a83b21b2f1875330ac16ef8d3f9da267f9f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/468686 Reviewed-by: Todd Broch <tbroch@chromium.org>
* servo_v4: Don't disable SBU mux when TypeC detach occursScott2017-04-041-12/+12
| | | | | | | | | | | | | | | | | | | | | | | When a USB PD connection is made, servo_v4 senses the polarity of the SBU signals and sets the SBU mux for the deteted polarity. If the DUT is reset, the SBU mux needs to retain the same state so the H1 console USB endpoint is not disrupted. Modified the CCD_MODE_DISABLED case to no longer disable the SBU mux. In addition, removed the static variable ccd_mode as it was being set, but not ever being checked, so wasn't serving any purpose. BUG=b:36561120 BRANCH=servo_v4 TEST=Connect servo_v4 to Electro. On Electro EC console enter 'reboot' verify the H1 USB console remains connected. Change-Id: I4f0f5167221c04314ca5be063411f200896bbdf6 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/464068 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* usb_updater: fix --fwverstabilize-9430.BMary Ruthven2017-04-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a send_done call at the end of show_fw_ver. With this change Cr50 will set the state to rx_idle after every usb_update -f call. Cr50 cannot process any vendor commands unless the updater state is idle. After a vendor command is sent cr50 wont set the state to idle unless it receives a send_done call. It will also reset the state if it sees that it has been more than 5 seconds since the last transfer. In the current state you cannot use usb_updater -f back to back because usb_updater doesn't call send_done through the -f path. If you wait 5 seconds between calls, then it will work. If the call fails and you keep retrying waiting less than 5 seconds between calls, then it will fail forever. The last transfer time will get reset with each call and Cr50 will never reach the timeout to reset the usb_update state to idle. BUG=none BRANCH=cr50 TEST=run 'sudo ./usb_updater -f && sudo ./usb_updater -f'. Verify both calls succeed. Change-Id: I5daca8e03ece840288abb61e02a528a9af0ada30 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/465491 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Poppy: Enter/exit from S0ix based on host commands from kernelstabilize-9428.BArchana Patni2017-04-033-3/+3
| | | | | | | | | | | | | | | | | | | | | This patch enables the entry/exit model for S0ix based on host commands. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. BRANCH=none BUG=b:36630881 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify EC goes to S0ix state, and on wake it comes back to S0 state. Change-Id: I22405021aead8488a5a1f166400cbde76faac59b Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/446219 Commit-Ready: Archana Patni <archana.patni@intel.corp-partner.google.com> Tested-by: Archana Patni <archana.patni@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* poppy: Add support for CONFIG_EMULATED_SYSRQNicolas Boichat2017-03-311-0/+1
| | | | | | | | | | | | | | | | This will eventually be used for debug mode. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I56b3a1f8f4b32d3ead91b83d474546356b65d221 Reviewed-on: https://chromium-review.googlesource.com/462757 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Add support for emulated sysrqNicolas Boichat2017-03-315-0/+51
| | | | | | | | | | | | | | | | | | | | On keyboard-less design, we will implement a special debug mode, based on button sequences, to transmit sysrq events to the AP. This implements the new MKBP event to send sysrq, and a console command to test it. Later CL will implement debug mode itself. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I71d3f77497baf8cc7fac65cd040ce20513b507bc Reviewed-on: https://chromium-review.googlesource.com/456520 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_updater: fix -b optionMary Ruthven2017-03-311-1/+1
| | | | | | | | | | | | | | | We want the -b option to be parsed the same way as the -u option, because usb_updater should handle reading the file the same way. This changes binver hasarg to be 0, so that it doesn't eat the filename. BUG=none BRANCH=cr50 TEST=usb_updater --binver $IMAGE Change-Id: I0b868bc5d316e5fb42fc34bc746bbee868d20630 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/465490 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: wp: Only use RAM val on wake from hibernate.Aseda Aboagye2017-03-311-6/+12
| | | | | | | | | | | | | | | | | When Cr50 resumes from hibernate, it should use the WP state that was stored in the long life scratch registers. All other boots should simply follow the state of the BATT_PRES_L pin. BUG=b:36659750 BRANCH=master,cr50 TEST=Power on Cr50 via battery, verify that WP_L remains asserted. Change-Id: I516d43b6540d7c543e7629f8709ce63515bb7f76 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/464258 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: rbox: Let pins stabilize before releasing EC.Aseda Aboagye2017-03-311-2/+6
| | | | | | | | | | | | | | | | | | When releasing the PINMUX hold, some of the output levels may change. Therefore, it's probably best to let those outputs stabilize before letting the EC out of reset and sample them. BUG=b:36659750 BRANCH=master,cr50 TEST=Flash Cr50. Verify that WP_L is stable before EC is released from reset. Change-Id: Ie2967c5e97f28240e1724b4531655c5dd08a3f29 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/464257 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* board/reef: enable CONFIG_DPTF_DEVICE_ORIENTATIONAaron Durbin2017-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | The BIOS had the tablet mode device enabled in CL:439308, however the corresponding change to the EC never was done. Therefore, powerd was monitoring the tablet mode device which always reported tablet mode because it wasn't reading the real state. As such the keyboard and trackpad were never being unhibited by powerd. Ensure the EC config matches the BIOS changes so that the correct state is properly reported. BUG=b:36788342 TEST=Booted device. keyboard and trackpad work as expected. BRANCH=reef Change-Id: Ie76007bc0e2ced046ebe1c241150f300efd3bb82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/464026 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* chg_ramp: Don't change ICL until vals are init'd.Aseda Aboagye2017-03-302-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the charge ramp task starts, it starts up in the DISCONNECTED state. From this state, it's possible to set the input current limit to 0 mA. However, upon task start, we shouldn't take any action until we have valid values from a new charge supplier or a supplier leaving. This commit changes the charge ramp task to not touch the input current limit until the charge ramp state changes or the desired input current changes at least once. BUG=b:36468002 BRANCH=gru,master TEST=Flash kevin EC RW or build AP FW that contains the fix that will by sync'd by EC SW sync. Make sure WP is asserted to prevent PD communications in RO. Unplug battery. Plug in AC, verify that system can boot up to UI on AC alone. TEST=make -j buildall Change-Id: I351917bce7902c49d1bb842a0cc83dd161d75b6f Reviewed-on: https://chromium-review.googlesource.com/461382 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/463927 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Kevin: enable CONFIG_CHARGER_DISCHARGE_ON_ACDerek Basehore2017-03-291-0/+1
| | | | | | | | | | | | | This enables CONFIG_CHARGER_DISCHARGE_ON_AC so the ectool chargecontrol discharge command will work. BUG=b:35563925 BRANCH=none TEST=run 'ectool chargecontrol discharge' Change-Id: I3a4acd83f131ccd050739e68d156f8facf4a93cc Signed-off-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/462464
* ISH: HPET Timer Configuration.Divagar Mohandass2017-03-293-42/+53
| | | | | | | | | | | | | | | | | | | | | This change includes - Configuring the HPET timer based on the spec (IA-PC HPET (High Precision Event Timers) Specification 1.0a) - Two timers used: HPET Timer0 (free running periodic timer) HPET Timer1 (event based non-periodic timer) - HPET interrupts are routed to ISH via IOAPIC - Both the timers are functional BUG=None BRANCH=None TEST=`Build ISH and verify the timer interrupt via various console cmds` Change-Id: Ib5ca24d05790868430a2cfa72ca73f5bd6a5fea3 Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/453858 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rose: add stm32f4 family supportRong Chang2017-03-281-2/+3
| | | | | | | | | | | | | This change applys config-stm32f446.h to stm32f4 family. BUG=chromium:688979 TEST=boots on stm32f401 and stm32f412 dev boards BRANCH=none Change-Id: I939fd17f29f4b431d9c1358c184166c67fef18d3 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438908 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32mon: add support for SPI flashing modeVincent Palatin2017-03-281-16/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow to flash an STM32 in bootloader mode through its SPI slave interface. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36125319 TEST=run from Eve AP: export SPIDEV="/dev/spidev32765.0" export GPIO_NRST=418 export GPIO_BOOT0=419 echo ${GPIO_BOOT0} > /sys/class/gpio/export echo "out" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction echo ${GPIO_NRST} > /sys/class/gpio/export echo "out" > /sys/class/gpio/gpio${GPIO_NRST}/direction echo 1 > /sys/class/gpio/gpio${GPIO_BOOT0}/value echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value stm32mon -s ${SPIDEV} -r /tmp/mcu-image.bin echo 0 > /sys/class/gpio/gpio${GPIO_BOOT0}/value echo 0 > /sys/class/gpio/gpio${GPIO_NRST}/value echo 1 > /sys/class/gpio/gpio${GPIO_NRST}/value echo "in" > /sys/class/gpio/gpio${GPIO_BOOT0}/direction echo "in" > /sys/class/gpio/gpio${GPIO_NRST}/direction re-verify UART flashing mode with 'flash_ec --board=eve_fp' Change-Id: Ic268dd9e62a2f279dd7992a4bbcf16fcf44c5f9e Reviewed-on: https://chromium-review.googlesource.com/456596 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* remove reef derivativesVincent Palatin2017-03-2717-5252/+0
| | | | | | | | | | | | | | | | | | | | The derivatives development should be done in the firmware branch. (here it is firmware-reef-9042.B) They are way too many 'follow reef settings' CLs, either all derivatives should be updated at the same time or we have to cut the rotten fruits. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36192920 TEST=make buildall Change-Id: I20cbc4897c7e6e3355ca0a4ed0e856d6b1d17eff Reviewed-on: https://chromium-review.googlesource.com/452459 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* eve_fp: enable internal flash supportVincent Palatin2017-03-261-7/+0
| | | | | | | | | | | | | | | | | Enable the support to re-flash the STM32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648258 TEST=On Eve, flash the FP MCU with: flashrom -p ec:type=fp --fast-verify -w /tmp/ec.bin Change-Id: I34ca69e1a530f217edb93cd8a189ee6c7244e353 Reviewed-on: https://chromium-review.googlesource.com/456712 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* servo_v4: Set desired data role for DUT port to UFPScott2017-03-262-10/+13
| | | | | | | | | | | | | | | | | | The default for servo_v4 DUT port is to be SRC to charge the DUT, but a UFP data role so that the DUT's usb mux gets connected. BUG=b:35586526 BRANCH=servo TEST=Connect to Electro and verify that servo_v4 data role is that of UFP and that electro is getting an IP address from the enet port on servo_v4. Change-Id: I8f2e4242777bf879598852004096f683d68c091c Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/452725 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: pd: Updated CC_NC and CC_RA macrosScott2017-03-263-10/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previous boards that implemented tcpc layer on chip didn't support variable Rp values. However, servo_v4 can present any of the 3 possible Rp values and therefore the voltage thresholds that are used to determine a no-connect or Ra attach status need a way to be set based on the Rp value that's current attached to a given CC line. - Added port and cc line selection to both the CC_NC and CC_RA macros and now check if they are already defined before being defined in usb_pd_tcpc.c. - Defined each of these macros in board.h to use a function that's able to select the threshold based on the current Rp configuration. BUG=b:35586526 BRANCH=servo TEST=Tested with servo_v4 against Electro and verified that it connects when a charger is and is not connected to CHG port which exercises the differnt Rp combinations that servo_v4 presents. Change-Id: I1a31e430c0f290486f0fa8a50bdafdddf20d23ca Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/451962 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: Enable VBUS passthrough from CHG to DUT portScott2017-03-243-68/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for the DUT port to advertise different current levels via the Rp resistor selection. The default setting is USB (500 mA). The board_manage_chg_port function relies on the off->on transitions only occurring when the CHG port is in a steady state condition. When the charger being used supports PD messaging, the entry point pd_set_input_current_limit() which is called after receiving a PS_RDY message. For TypeC only chargers, the entry point is typec_set_input_current_limit() which is called from SNK_DISOVERY after only after the max number of hard reset attempts have been attempted. This is intended to prevent this entry point from being called when a USB PD charger is connected and the CHG port enters SNK_DISCOVERY. When the CHG port Vbus transitions from off->on, a src_pdo is updated to reflect the current contract on the CHG port and this src_pdo can then be used by the DUT port when either a new connection is done or to update it's existing contract. BUG=b:35586526 BRANCH=servo TEST=Manual Connected servo_v4 DUT port to Reef with no charger connected. Verified that it connects, and CCD mode in Reef is enabled (H1 console is available) and that only 500 mA charging current is advertised. Then connected a 20V and 15V USB PD charger to the CHG port. In each case verified that the DUT renegotiates to the 20 and 15V level respectively. Repated the test with Guppy and verifed that VBUS is at 5V 3A. When Guppy is removed, then the DUT connection reverts back to the host as the VBUS source. Change-Id: I1a5eb346bbe1f0d586cb8b7bb24d77ff713fbf3c Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449954 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add internal flash support for STM32L4 familyVincent Palatin2017-03-243-6/+554
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a flash driver for the STM32L4 family. For write and erase, the code is very similar to other variants excepted the 'normal' writes need to be perform 2 aligned 32-bit words at a time. Option bytes are a sligthly easier business since the hardware deals with the option bytes page preserving and erasing for us. For the write-protection, the STM32L4 is slightly different from the other variants. The write-protection granularity is still a 2-kB block (2kB here) but instead of having a 'bitmap' of the protected blocks, it defines 2 write-protection ranges (WRP1AR and WRP1BR). For the EC code base, we are using WRP1AR to protect the Read-Only regions and WRP1BR to protect the Rollback and RW regions (if they exist). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648258 TEST=On Eve, run 'flashrom -p ec:type=fp -w /tmp/ec.bin' and 'flashrom -p ec:type=fp --wp-enable --wp-range 0x0 0x20000' Change-Id: Iaa98c1b4d3b07de2923ac076624bd4601c31a600 Reviewed-on: https://chromium-review.googlesource.com/456711 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* flash: ensure proper pstate alignmentVincent Palatin2017-03-242-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The pstate structure is written using the low-level flash_physical_write() function. As a consequence, it is supposed to meet the CONFIG_FLASH_WRITE_SIZE alignment constraint. Add a build-time assertion to avoid silent failures. Slightly decrease the maximum size of the serial number string, so the structure has a natural 32-byte alignment which is compatible with a large number of platforms (including STM32L4 which requires 64-bit alignment). Of course, this change is not fully backward-compatible. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:571477 b:35648258 TEST=on STM32L442, build and run 'flashrom --wp-enable' without failure. Change-Id: Ia8f82790a61a6c7d2cf9bfeb95bfdaf7b8c52d11 Reviewed-on: https://chromium-review.googlesource.com/458201 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: Move pwm open-drain functionality from gpio to pwm driver.Mulin Chao2017-03-247-28/+18
| | | | | | | | | | | | | | | | Setting PWM IO type in gpio driver seems not a proper way. This CL moves this functionality to pwm driver and introduces a new flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it in board driver. BRANCH=none BUG=none TEST=test pwm functionality on npcx_evb. Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: add a function to read TPM NVMEM locationsVadim Bendebury2017-03-232-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | The cr50 code might need access to certain variables stored in the TPM NVMEM. In particular the upcoming FWMP support will require reading the NVMEM FWMP space. This patch adds a generic function which allows to access TPM NVMEM spaces. The implementation was borrowed from NV_REad.c in the tpm2 tree, the only difference being that the location, if present, is read unconditionally, without checking access controls. The API accepts the NVMEM index in Chrome OS scope and maps it into TPM2 specification's NVMEM index space based at HR_NV_INDEX. The definitions are included straight from the tpm2 tree. BRANCH=none BUG=chrome-os-partner:62489, chrome-os-partner:62205 TEST=this code is not yet even being compiled, tested with the next patch. Change-Id: I8bcfd8637c192249780634491f30e4a28229984f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/457823 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* bd9995x: Disable IADPDaisuke Nojiri2017-03-231-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables IADP immediately after the EC boots. We observed noise on IADP/RESET pin causing SEL_ILIM_VAL to randomly change. This seems the cause of b:35648317. We enabled IADP to fix b:35647661 initially and also followed the vendor's recommendation. However, the issue is only reproducible on the particular board which was used for power measurement and we did not see the issue on other boards with IADP disabled. Also the vendor assumed our EC doesn't control IBUS_LIM_SET and ICC_LIM_SET. (I think they assumed like other thier customers our EC controls ILIM by DAC connected to IADP/RESET pin.) If ILIM is not set by EC and IADP is disabled, the system would brownout because ILIM stays at 128mA. Therefore, it was (mistakenly) recommended that our EC should keep IADP enabled. Cros EC configures IBUS_LIM_SET and ICC_LIM_SET dynamically thus the above concern does not apply. We also found that we have too much noise on IADP/RESET pin. The noise is not big enough to cause the chip to reset but it's big enough to cause ILIM to fall in 128mA zone. We think this is why the boards fail to boot from battery cutoff or no battery. (Contrary to the vendor's explanation, it seems IADP/RESET pin continusouly affects ILIM not only in the early chip power-up period.) BUG=b:35648317 BRANCH=none TEST=Booted two Electro and two Snappy from 1) dead battery 2) no battery 3) battery cutoff. Change-Id: Ic675f1354b9ef222ceec8ce112b19713812d2752 Reviewed-on: https://chromium-review.googlesource.com/458676 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* g:script to create cr50 release imagesVadim Bendebury2017-03-232-4/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are still building two images - for prod and dev fused H1 chips. This requires different pairs of RO images and calls for using different keys when signing RW images. Each produced image is of 512K bytes in size, the ROs are paced at offsets 0 and 0x40000, the RWs at offsets 0x4000 and 0x4000. The signed ROs come from their respective source, their processing is limited to converting into binary format and verifying that their key signatures match image designation (prod vs dev). The RWs binaries are derived from RW elf files which are the result of running 'make BOARD=cr50'. The elves are converted into binary format and signed, the bs script is used for that. The bs script is modified to accept the destination file name from the shell variable, to detect signing failures (resulting in zero sized binaries), and to fix error reporting. The new script create_released_image.sh expects exactly six command line parameters: <prod RO A>.hex <prod RO B>.hex <dev RO A>.hex <dev RO B>.hex \ <RW.elf> <RW_B.elf> and generates two cr50 binary images. The generated images are placed in the directory named cr50.r<ro vers>.w<rw vers> (the versions are retrieved from the binaries using usb_updater), and then placed in the tarball with the same base name. This naming convention is imposed by the ebuild pulling in the tarball from the binary component server (BCS). On the successful completion the script prints out commands which can be used to upload the new tarball to the BCS. BRANCH=none BUG=b:35587234 TEST=ran the script to generate the r0.0.10.w0.0.18 release, verified that all components of both imagea are properly signed (are bootable and the key signature matches the prod/dev convention). Change-Id: I87be1d44a721c979bdeeabf986d717e3a382db45 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/439907 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* eve: Fix corner case for trackpad wakeDuncan Laurie2017-03-231-1/+9
| | | | | | | | | | | | | | | | | | | | If we go to sleep with a lid close event, the trackpad is immediately waking the system. Since we don't want to accidentally wake if the trackpad got input while the lid is closed anyway this change will disable trackpad wake when the lid is closed. BUG=b:35587072 BRANCH=none TEST=manual testing on Eve P1b: 1) enter suspend by closing lid and ensure it stays in suspend 2) enter suspend by idle, and then close the lid, and ensure it stays suspended Change-Id: Ied73dde61e99231f057504ca56c473432aa30e4b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/457865 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* npcx: gpio: remove unused wui sources for npcx5mng.Mulin Chao2017-03-231-5/+0
| | | | | | | | | | | | | | | | Remove unused wui sources of GPIO96/A0/A2/A4 since we don't support them in 128/132-pins packages of npcx5mng. This CL also removes wui source of GPO66 in case developer declares it as GPIO_INT. BRANCH=none BUG=none TEST=test gpio functionality on npcx_evb, reef and poppy. Change-Id: I363813128d02be0fc642e82ca0b463971af22a90 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458238 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hammer: Increase HOOK stack sizeNicolas Boichat2017-03-231-1/+1
| | | | | | | | | | | | | | | | | After running an update, we used to be dangerously close to exhausting stack space, let's increase its size. 1 HOOKS 00000000 39.906350 476/488 BRANCH=none BUG=b:35587171 TEST=Update FW using usb_updater2, 3 times in a row, without reboot, no more panics. Change-Id: Ia1559d7c4097b8d3179a6fa2f38bef126cb8055e Reviewed-on: https://chromium-review.googlesource.com/458319 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: add code to corrupt new header until further notice and move rw to 0.0.19Vadim Bendebury2017-03-224-18/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the rest of support in place, this patch adds code which would corrupt the headers received during firmware updates. The VENDOR_CC_TURN_UPDATE_ON vendor command will be required to enable the new images. Care should be taken that other commands operating on the inactive image header do not do anything with it before it was enabled, some code is being added for that. The minor RW version is being bumped up to 19 to clearly indicate that the device is expecting the vendor command to enable the new image (this is used by usb_updater when downloading the image without the -p or -u command line options). BRANCH=cr50 BUG=b:35580805 TEST=verified that the new image can be installed and started by the new usb_updater. - the inactive header after uploading with the -p option (the image_size field's offset is 0x32c): > md 0x84320 4 00084320: 00000000 00000000 80033800 00084000 rebooting the device does not start the new image. - the inactive header after uploading without the -p option: > md 0x84320 4 00084320: 00000000 00000000 00033800 00084000 the device running a DBG image reports the following in the end of the image update: [64.176780 FW update: done] turn_update_on: rebooting in 100 ms Change-Id: I4d763eb89c8b1a43a13697033201066779826e85 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/457678 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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