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* Reef: Enable smart power control to the device's USB portsstabilize-8714.BVijay Hiremath2016-08-161-0/+8
| | | | | | | | | | | | | | | BUG=chrome-os-partner:55377 BRANCH=none TEST=From the Kernel console, using 'ectool usbchargemode' & 'lsusb' commands verified that the USB devices are able to connect and disconnect from the system. Change-Id: I45059d9e4a4995ae87eb24459c66f0110cfb20ce Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/361403 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common/btle_ll.c: Return error code instead of uninitialized valueMartin Roth2016-08-161-1/+1
| | | | | | | | | | | | | The variable rv was being returned without being initialized. Instead, return EC_SUCCESS. BUG=None BRANCH=None TEST=Build all boards successfully. Change-Id: If37057b737e6419c1d5cc22215a7d76d920d1267 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/370664
* fusb302: enable setting Rp valueVincent Palatin2016-08-163-0/+14
| | | | | | | | | | | | | | | | | | | | | Configure the FUSB302 current source used for Rp according to the CONFIG_USB_PD_PULLUP_xxx value. Set the default Rp for Kevin to 1.5A. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:54452 chrome-os-partner:56110 TEST=manual: plug to Samus, enable charging on the Samus side, measure the CC voltage with Twinkie, get 950mV instead of 450mV. Change-Id: I98faf18132a097e49e9c0fa8e1395d230608ee9e Reviewed-on: https://chromium-review.googlesource.com/369190 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: fix CC values in usb PD unittestsVincent Palatin2016-08-161-6/+4
| | | | | | | | | | | | | | | | | The if conditions to simulate the CC line levels had a couple of typos. Use a more realistic value for those corner cases. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make run-usb_pd Change-Id: Ia924ee4cfe4512a7543cfcae4d532c9a250d9c8d Reviewed-on: https://chromium-review.googlesource.com/368720 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_updater: refactor section transfer into a functionVadim Bendebury2016-08-161-61/+84
| | | | | | | | | | | | | | | | | | | In preparation to RW and RO cr50 updates, separate the code transferring an image section (an RW section currently) into a function. This will allow to add RO transfer by invoking the same function with different address and size parameters. BRANCH=none BUG=chrome-os-partner:55789 TEST=verified that it is still possible to update to RW_A and RW_B both over USB and SPI. Change-Id: Ia41317e0eefe114bac41e73c7e715b1a5cb6549c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368988 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* btle: Improved stability of ble_rx functionLevi Oliver2016-08-162-2/+32
| | | | | | | | | | | | TEST=Used function before and after CL in a more fully implemented stack. This improved reliability and lengthened connection times. BUG=None BRANCH=None Change-Id: I60680c8855d6166e4e4a6a71639ee57464fa21ce Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/370420 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_updater: use size_t for variables determining transfer sizeVadim Bendebury2016-08-151-9/+9
| | | | | | | | | | | | | | This is a mostly cosmetic change, use size_t as the type for variables which are used to pass around number of bytes received or transmitted. BRANCH=none BUG=chrome-os-partner:55789 TEST=verified that usb_updater still works both over USB and SPI. Change-Id: I2cc726315d613ee42937fb494745cf7e0ea66622 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368987 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* build: Specify pre-cq build targetsShawn Nematbakhsh2016-08-151-0/+3
| | | | | | | | | | | | | | | Include pre-cq build targets that actually build chromeos-ec. BUG=chrome-os-partner:56196 BRANCH=None TEST=Pass pre-cq, verify chosen targets are included. Change-Id: I175f627c23247bbd269dead8610979118cab8ac7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368893 Commit-Ready: Douglas Anderson <dianders@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: delay sleep for 3 minutes after resuming from sleep or after initMary Ruthven2016-08-142-1/+5
| | | | | | | | | | | | | | | | | | | | | | Disable sleep for the first 3 minutes after initializing cr50 and disable sleep for 3 minutes after a wakepin interrupt has been received. BUG=none BRANCH=none TEST=manual on a development board pull up dioa3 and dioa12 then verify cr50 does goes to sleep after 3 minutes. on gru see sleep is delayed by 3 minutes when the wakeup interrupt is called. enable deep sleep and check cr50 does not go to sleep for 3 minutes after resuming. Change-Id: I28ec3c2f5f86326b926d403ad52ffb4fc108e7ec Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367880 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Release EC_RST_L in RW after all initialization has completedtimothytim2016-08-132-3/+12
| | | | | | | | | | | | | | | | | | | Adding a lowest priority hook init function, guaranteed to run after all other initialization is completed, which is a good time to take the EC out of reset. Also moving pin hold release into the same function. BRANCH=none BUG=chrome-os-partner:55797 TEST=verified proper reset pulse generated on reef verified that reef, kevin and gru all boot up as expected Change-Id: Ic91e871f5040b9aa02a2f11cf76d2d596c48a04c Signed-off-by: Timothy Chen <timothytim@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367410 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* power: Add virtual-wire power signals support for skylake.Mulin Chao2016-08-132-7/+54
| | | | | | | | | | | | | | | | | | | Add virtual wire power signals support for skylake. By adding CONFIG_VW_SIGNALS definition in board level driver, we can save three GPIOs (SLP_S3/SLP_S4/CLK_RUN) on skylake platform. Modified sources: 1. common.c: Add support for VW power signals. 2. skylake.c: Add upper func to get system sleep state through GPIOs or VWs. BRANCH=none BUG=none TEST=make buildall; test boot up and shut down on eSPI POC of wheatley. Change-Id: I0eae363dad8cec011eb32929a40701f19fde7e1a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366711 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Fixed pwm bug to improve deviation of PWM frequency.Mulin Chao2016-08-121-1/+1
| | | | | | | | | | | | | | | | | | | | According the formula for computing prescaler of PWM, we needn't minus one again in line 89 of pwm.c. On npcx's evb, we observe the deviation of PWM 1 which freq is 10K is reduced from 0.6 kHz to 0.01 kHz. We also change PWM 1's freq to 100 Hz with PWM_CONFIG_DSLEEP and the deviation is reduced from 64.2 Hz to 9.2Hz. Modified sources: 1. pwm.c: Modifed formula for computing prescaler of PWM. BRANCH=none BUG=chrome-os-partner:56052 TEST=make BOARD=npcx_evb; use "pwm 1 50" to observe deviation of freq Change-Id: I9cd7fc0d807df62083d49a7e9ec6de1d9028be1b Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/368560 Reviewed-by: Shawn N <shawnn@chromium.org>
* btle: Timeout of ble_rx now based on chip timeLevi Oliver2016-08-122-2/+15
| | | | | | | | | | | | | | | Previously, timeout meant the number of attempts taken to receive. Now, it means the number of microseconds before timing out. TEST=printouts displaying time before and after rx attempt. Not included in CL. BUG=None BRANCH=None Change-Id: I00ccfc4bbf15f77c2777f35c911dceacaff98e4f Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/368471 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* test: Don't test with CONFIG_POWER_TRACK_HOST_SLEEP_STATEShawn Nematbakhsh2016-08-121-2/+2
| | | | | | | | | | | | | | | CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on MKBP, so just remove it from tests. BUG=chrome-os-partner:56156 BRANCH=None TEST=`make BOARD=gru tests` Change-Id: I8b95954e106c28c7152666c510f7611fe87014a0 Reviewed-on: https://chromium-review.googlesource.com/368970 Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org>
* tcpm/anx74xx: initialize reg variable before useMartin Roth2016-08-121-0/+2
| | | | | | | | | | | | | | | When disabling auto_good_crc, the reg variable was being used without initialization. Mirror the code for enabling auto_good_crc to set the variable. TEST=Booted reef with updated code. BUG=None BRANCH=None Change-Id: Ie552f2ff74df05750bd65b6344d8a80cc285f8b0 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368221 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* mkbp_event: Allow host to report sleep state for non-wake event skippingShawn Nematbakhsh2016-08-127-6/+84
| | | | | | | | | | | | | | | | | | | | | | Allow the host to self-report its sleep state through EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND param when the host begins its sleep process. While the host has self-reported that it is in SUSPEND, don't assert the interrupt line, except for designated wake events. BUG=chrome-os-partner:56156 BRANCH=None TEST=On kevin, run 'ectool hostsleepstate suspend', verify that interrupt assertion is skipped for battery host event. Run 'ectool hostsleepstate resume' and verify interrupt is again asserted by the battery host event. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I74288465587ccf7185cec717f7c1810602361b8c Reviewed-on: https://chromium-review.googlesource.com/368391 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Makefile.toolchain: Add error if make version will not build the ECMartin Roth2016-08-121-0/+7
| | | | | | | | | | | | | | | | | | | | If you try to build the EC codebase with GNU make version 3.81 or less, you currently get an error: Makefile.rules:286: *** multiple target patterns. Stop. Since this message isn't helpful in letting you know that the version of make needs to be updated, let's print something more useful. ERROR: GNU make version 3.82 or higher required. Stop. TEST=Built with Make 3.81 and saw the new error message. Built with make 3.82 and 4.0 and the EC built correctly. BRANCH=None BUG=None Change-Id: I5813fd26fa8120742544567c5ae04af01f993f94 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367944 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* charger/bd99955.c: Simplify flow in console_command_bd99955Martin Roth2016-08-121-5/+3
| | | | | | | | | | | | | | | | It looks to static analyzers as if the variable val could be used without being initialized. That isn't actually the case because of all the checks that are being done, but the flow can be simplified to only get the value to write when we're on the write path. BRANCH=None TEST=Build and boot Reef BUG=None Change-Id: I9f6ce3c9dcbab74f3c6de18dbd1f2e07bc1c4a13 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368302 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* npcx/flash: Don't print uninitialized valuesMartin Roth2016-08-121-2/+3
| | | | | | | | | | | | | | | | In command_flash_spi_sel_lock(), and command_flash_tristate() a value could be printed without being initialized first. Only display the values in the paths where the variable gets read. BUG=None TEST=Build and boot Reef BRANCH=None Change-Id: I8ef86f966d017290491d6fe2b1486ce913cd09fb Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368301 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* wheatley: Modified board level drivers for eSPI POC on wheatley.Mulin Chao2016-08-123-0/+13
| | | | | | | | | | | | | | | | | | | | | Modified board level drivers for eSPI POC on wheatley. By adding CONFIG_ESPI definition, ec can support espi protocols for host interface on x86 based platform such as skylake and so on. CONFIG_VW_SIGNALS will be used in the future for saving GPIOs during power sequence. Modified sources: 1. wheatley/board.h: Enable/disable espi driver. 2, wheatley/board.c: Add VW signals in power signal list. 3. wheatley/gpio.inc: Save GPIOs if CONFIG_VW_SIGNALS is defined. BRANCH=none BUG=chrome-os-partner:34346 TEST=make BOARD=wheatley; test nuvoton IC specific drivers Change-Id: I0e8a951de6eacd4f8be65ffaac242f38079375d5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366520 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Analogix: Present configured Rp pull-up.Tang Zhentian12016-08-113-6/+27
| | | | | | | | | | | | | | | | | | ANX was using 36K Rp detection as default detect value. ANX fix google issue google charger BUG=chrome-os-partner:54452 BRANCH=master TEST=On Reef: With twinkie tested CC voltage change for 1.5A Rp pull up meets the spec values. Change-Id: I3af20e5c437218b83befc899a7c62b019b2c9dee Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com> Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/366461 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* Amenia/Reef: Present 1.5A PullupDivya Sasidharan2016-08-116-3/+39
| | | | | | | | | | | | | | | | | | | | Enable config to choose the Rp pullup strength to advertise the desired current from USB-C while providing power. BUG=chrome-os-partner:54452 BRANCH=none TEST=Boot and check appropriate register settings in Reef. For Parade: i2cxfer r 1 0x16 0x1A -> 0x15 Change-Id: I5c1b7a45bf483333d7b411aad402fc95e4fa05de Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/353038 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* Cr50: NvMem: Added write/move error stateScott2016-08-112-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvmem_write() and nvmem_move() funcitons return an error if the write or move operation would exceed the user buffer boundary. However, the TPM2 functions which call these functions do not check for errors. Instead TPM2 NvMem relies on the return value of the nv_commit() function to determine if a TPM command which modifies NvMem succeeds or fails. This CL adds a nvmem_write_error flag which is set in cases where an nvmem_write/nvmem_move returns an error. This error flag is then checked in nvmem_commit() so that the commit operation can be abandonded and the error returned back up the TPM2 stack. Tested in full system for two cases. Installed TPM certificates on the Cr50, then manually erased NvMem with flasherase 0x7b000 0x5000 and rebooted system. Then on Kevin console entered the command <trunks_client --own> NV_MEMORY_SIZE = 9932 NVMEM_TPM_SIZE = 7168 Case 1 -> Without internal write error state, so commit() always executes if called. In this case, the Kevin console reports a TRUNKS_RC_WRITE_ERROR and there is a Cr50 reboot. Kevin Console: localhost ~ # trunks_client --own [INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK. [INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK. [ 134.056217] tpm tpm0: Operation Timed out [ERROR:tpm_utility_impl.cc(1987)] DoesPersistentKeyExist: querying handles: TRUNKS_RC_WRITE_ERROR [ERROR:tpm_utility_impl.cc(269)] TakeOwnership: Error creating salting key: TRUNKS_RC_WRITE_ERROR [ERROR:trunks_client.cc(98)] Error taking ownership: TRUNKS_RC_WRITE_ERROR Cr50 Console: > [131.501920 nv_commit()] [142.494755 nv_wr: max off = 0x1250] [142.496347 nv_wr: max off = 0x17b4] [142.548296 nv_commit()] [142.678001 nv_rd: max off = 0x1250] [142.679350 nv_rd: max off = 0x1254] [143.269614 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [143.271460 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [143.273055 Wr Err = TRUE, Resetting error only, not returning] [143.325073 nv_commit()] --- UART initialized after reboot --- [Reset cause: rtc-alarm] [Image: RW_B, cr50_v1.1.5056-8e5dc99+ private-cr51:v0.0.69- 12:23:02] [0.004349 Inits done] [0.007150 Active NVram partition set to 0] [0.008086 Debug Accessory connected] [0.009076 USB PHY B] Console is enabled; type HELP for help. tpm_manufactured: manufactured [1.155766 usb_reset] [1.240155 usb_reset] [1.311188 SETAD 0x6c (108)] Case 2 -> Using internal error state to gate the commit() operation. In this case, the attempted write overflow sets the internal error state and the commit() following attempted overflow detection is not exectued. It results in a different AP TPM error shown below as Error encrypting salt. The other different behavior is that observed is that if after failing on the RSA SRK, the ECC SRK write is still attempted. Kevin Console: localhost ~ # trunks_client --own [INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK. [INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK. [ERROR:session_manager_impl.cc(154)] Error fetching salting key public info: Handle 1: TPM_RC_HANDLE [ERROR:session_manager_impl.cc(94)] Error encrypting salt: Handle 1: TPM_RC_HANDLE [ERROR:tpm_utility_impl.cc(277)] TakeOwnership: Error initializing AuthorizationSession: Handle 1: TPM_RC_HANDLE [ERROR:trunks_client.cc(98)] Error taking ownership: Handle 1: TPM_RC_HANDLE Cr50 Console: > [107.867473 nv_commit()] [133.743522 nv_wr: max off = 0x123f] [133.744908 nv_wr: max off = 0x1250] [133.746159 nv_wr: max off = 0x17b4] [133.798498 nv_commit()] [133.900131 nv_rd: max off = 0x1250] [133.901496 nv_rd: max off = 0x1254] [134.507033 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [134.508852 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [134.510440 Wr Err = TRUE, Aborting Commit!] [144.856751 Nv Wr: overflow stop: reqst = 0x1d1c, avail = 0x1c00] [144.858611 Nv Wr: overflow stop: reqst = 0x1d20, avail = 0x1c00] [144.860198 Wr Err = TRUE, Aborting Commit!] BRANCH=none BUG=chrome-os-partner:55910 TEST=manual Test in system as described above and ran NVMEM unit tests and verified that when a write would overrun the user buffer, the write fails and sets the error state. Then, verified that the nv_commit() call returns an error and clears the internal error state. Change-Id: I376e17b273003ff3d75459b4e68ed69d42dc7415 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366757 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* btle: Cleanup: Moved constants, renamed functionsLevi Oliver2016-08-113-17/+38
| | | | | | | | | | | | | | | Moved link layer-specific constants into link layer .h file. Renamed data channel function to better represent its function. TEST=make BOARD=hadoken BUG=None BRANCH=None Change-Id: I239d535cf3725bf003443fc211fc802bc8aee13f Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/367805 Commit-Ready: Myles Watson <mylesgw@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* btle: Add framework for parsing data packetsLevi Oliver2016-08-116-25/+34
| | | | | | | | | | | | | | | | | | | Re-wrote ble_radio_init to work with both data and advertising packets. Updated all calls to refactored function. RADIO_PCNF0_ADV renamed because it applies to advertisement and data packet formats. Updated all references to this value. TEST=make BOARD=hadoken BUG=None BRANCH=None Change-Id: I0fdbe0eb146ce5cbc40e3ac67bf4d0e5465dcc2f Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/367732 Commit-Ready: Myles Watson <mylesgw@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Myles Watson <mylesgw@chromium.org>
* npcx: Add espi driver of npcx5mng for x86-based platform.Mulin Chao2016-08-107-11/+994
| | | | | | | | | | | | | | | | | | | | | | | Add espi driver for x86-based platform which support espi interface such as skylake and so on. Added source: 1. espi.c: Add drivers which supports the utilities of peripheral and virtual-wire channels so far. 2. espi.h: Add espi virtual-wire declaration for power sequence FW. Modified sources: 1. lpc.c: Add interrupts and initialization steps for espi. 2. gpio.c: Add interrupt handler of espi reset. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366181 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* minute-ia: Enable x86 core for Intel ISHJaiber John2016-08-1017-0/+1919
| | | | | | | | | | | | | | | | | Add intial minute-IA (x86) core to to enable the FW to boot on Intel Integrated Sensor Hub (ISH). BUG=chrome-os-partner:51851 BRANCH=None TEST=`make buildall -j` Change-Id: I4dcf841766f216cd00fb1d4214fae19ba5de5603 Signed-off-by: Jaiber John <jaiber.j.john@intel.com> Signed-off-by: Alex Brill <alexander.brill@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336443 Commit-Ready: Raj Mojumder <raj.mojumder@intel.com> Tested-by: Raj Mojumder <raj.mojumder@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* kevin / gru: Notify host of HPD IRQ statusShawn Nematbakhsh2016-08-107-3/+40
| | | | | | | | | | | | | | | | | | If an HPD IRQ event is seen, make note of it and keep the status set until informing the host. BUG=chrome-os-partner:55925 BRANCH=None TEST=Manual on kevin, trigger HPD event, verify that event bit is set in reply to first host command and not subsequent host commands. Change-Id: I0900a683dcb344d5d4d03a1fa6e3d8de913597b2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366990 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Chris Zhong <zyw@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Guenter Roeck <groeck@chromium.org>
* reef: Set IS_PROTO to 0 by defaultDavid Hendricks2016-08-101-1/+1
| | | | | | | | | | | | | BUG=chrome-os-partner:54947 BRANCH=none TEST=tested on proto and EVT units Change-Id: I8f42495e81d938f3d660d901930f7e71bcb42ceb Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361062 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Martin Roth <martinroth@chromium.org>
* npcx/i2c: Remove static from arrays & functions used by inline functionMartin Roth2016-08-101-3/+3
| | | | | | | | | | | | | | | | | | | | This fixes several errors caused by these being defined as static while being used in the inline function i2c_handle_sda_irq(). From the C99 Draft 6.7.4.3: An inline definition of a function with external linkage shall not contain a definition of a modifiable object with static storage duration, and shall not contain a reference to an identifier with internal linkage. TEST=Build with GCC 5.3 flash and boot Reef board BUG=None BRANCH=None Change-Id: Ie487f17b92736c2a56280783267da5d3bb12b969 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367486 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: adc: Properly wait for conversion interruptMulin Chao2016-08-101-17/+7
| | | | | | | | | | | | | | | | | | | | Certain tasks (eg. chipset) may be woken directly by other tasks / unrelated interrupts. Add an explicit wake event for ADC conversion done so that we're not mistakenly woken. BUG=chrome-os-partner:54971 BRANCH=None TEST=Manual on kevin rev5, run "reboot ap-off" then "sysjump rw", verify console isn't spammed with GPIO warning message due to ADC failure to read board version. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5477e11c2b434e4b350d81393f4463eea1a91e7c Reviewed-on: https://chromium-review.googlesource.com/366943 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Fixed bug with conflicting error codesChris Chen2016-08-101-0/+2
| | | | | | | | | | | | | BRANCH=None BUG=None TEST=Manual - Build and run meta tests, look for listed output Change-Id: Idd46fb92791c1d0576be95f3e4cda8cdca66daef Reviewed-on: https://chromium-review.googlesource.com/367401 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Added meta tests (testing cts suite itself)Chris Chen2016-08-103-0/+249
| | | | | | | | | | | | | | | | | | | | | This is a test suite with certain expected failures. If making any changes to cts code other than simply adding a test suite, run this to make sure you didn't break cts. BRANCH=None BUG=None TEST=Manual - Build with "./cts.py -b --debug -m meta" - Flash with "./cts.py -f -m meta" - View results at /tmp/cts_results/<board_name>/meta.html - Results should match debug descriptions Change-Id: Ia5c10c7ce0e0d852fe6b14e481798eaff2a82c9c Reviewed-on: https://chromium-review.googlesource.com/364273 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Debug message support added to cts testsChris Chen2016-08-103-30/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | You can now add debug messages into a cts test and they will be displayed with the test report html page. The macro to use is CTS_DEBUG_PRINTF Adding debug messages can potentially change test results by slowing down the test, so you can choose when compiling a test suite if you want the debug messages present or not by adding --debug as an argument when you call ./cts --build. BRANCH=None BUG=None TEST=Manual - Add a debug statement to a test - Build the test suite with --debug specified - Flash the boards - Run './cts/cts.py -r' - Open /tmp/cts_results/<board_name>/<test_suite>.html to view see your debug message for the test Change-Id: Icad8e0ac5cc905010caa4e7616f81572ce6ac771 Reviewed-on: https://chromium-review.googlesource.com/362475 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Acpi: Notify host when orientation changesjames_chao2016-08-093-0/+20
| | | | | | | | | | | | | | | | | 1. EC send EC_HOST_EVENT_MODE_CHANGE(29/0x1D) when mode changes 2. Host read current "physical mode" from EC ERAM 3. Host Nodify DPTF object BUG=chrome-os-partner:53526 BRANCH=master TEST=make buildall Change-Id: I3ede1ffd203024199884b3a0c56347ae630e6062 Signed-off-by: james_chao <james_chao@asus.com> Reviewed-on: https://chromium-review.googlesource.com/363220 Commit-Ready: BoChao Jhan <james_chao@asus.com> Tested-by: BoChao Jhan <james_chao@asus.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* btle_ll: Set advertising channel frequencyLevi Oliver2016-08-091-2/+12
| | | | | | | | | | | | | | Remove repeated deadline resets. Deadline reset now in the STANDBY state. Set radio frequency to match selected channel. TEST=ble_hci_adv 0 BUG=None BRANCH=None Change-Id: Ic7ff0dba862c0216301d138413a89e4ef4a812fe Signed-off-by: Levi Oliver <levio@google.com> Reviewed-on: https://chromium-review.googlesource.com/367094 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ec: Unit test: Remove (temporarily) nvmem from test-list-hostScott2016-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | There seems to be flaky issue where the nvmem tests don't fully complete. I need to spend some time to try and understand the mechanism. It doesn't happen on every build attempt and never happens when I just run this particular test. In the meantime, I don't want the builder to fail due to this issue so I am removing this test from the test-list-host while I debug the issue. BUG=chrome-os-partner:55854 BRANCH=none TEST=manual Execute the command 'make runtests' in /platform/ec and verified that the nvmem test is no longer executed. Change-Id: I9f0778fd9fa17cf8949292f7abe8b05ccab2bae2 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/367302 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Clarified a few comments in registers.hChris Chen2016-08-091-5/+7
| | | | | | | | | | | | BRANCH=None BUG=None TEST=None Change-Id: I31bb65d89adb41cf3affd63e6ee9f73fbf11183a Reviewed-on: https://chromium-review.googlesource.com/366887 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Added corruption detectionChris Chen2016-08-092-13/+22
| | | | | | | | | | | | | | | | | | | | | | | If test suite doesn't finish or results are received out of order, this is likely an indication of reset or hang by one of the boards and all tests after the point of corruption are marked as corrupted. BRANCH=None BUG=None TEST=Manual - Edit the gpio th code to change ordering of tests or hang or reset, etc. - Build and flash tests - Run './cts/cts.py -r' - You should see the results for all of the tests, with all corrupted tests marked as corrupted Change-Id: I7925e37db285a4e90e6e09bf3b187400ddfe9edf Reviewed-on: https://chromium-review.googlesource.com/362614 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: try recovering from rolling rebootsstabilize-8688.BVadim Bendebury2016-08-083-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes a perfectly sane image enters rolling reboot mode in case some data change triggered a bug which prevents the normal startup and causes a reset. The most likely task causing in in case of cr50 would be the tpm task. Let's add another check of the restart counter: should it reach the value of 50, do not start the TPM task. BRANCH=none BUG=chrome-os-partner:55708 TEST=with this code plus an unaligned access introduced in tpm initialization sequence in both RW_A and RW_B, program the full image on the dev board. Observe the device reset 50 time is rapid succession and then stop with the following message on the console: Bldr |511709 retry|50 Himg =4F992103..408D193E Hfss =384E4655..EE13EBD0 Hinf =44D21600..B70529BD jump @00044000 --- UART initialized after reboot --- [Reset cause: rtc-alarm] [Image: RW, cr50_v1.1.5044-8d6f7a2+ private-cr51:v0.0.68-633229c ... + cryptoc:v0.0.4-5319e83 2016-08-07 19:37:16 vbendeb@kvasha] [0.004130 Inits done] [0.006919 Active NVram partition set to 0] Console is enabled; type HELP for help. > system_rolling_reboot_suspected: roling reboots suspected. Try \ powercycling to clear this condition. [0.010502 Task 2 (TPM) exited!] Change-Id: I6b08c5c1a02da9edf9bdf394e57cc56d2e595ad1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366892 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: fix nvmem calculationsVadim Bendebury2016-08-084-18/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The nvmem space defined in the ec code base for the cr50 board is used by the TPM2 library, which has its own nvram size definition. The two definitions must match. On top of the fact that the definitions are not locked to each other, there is a third completely unrelated nvram size definition in board/cr50/board.c. This patch unifies nvmem size definitions between cr50 and tpm2 repositories by adding a compile time check for the size to be the same on both sides. Also, it turns out that two certificates (RSA and ECC) together do not quite fit into the cr50 TPM nvram. Hence the total allocated nvmem space is being increased to 20K (note that the actual nvram size available to the TPM is less than half of this). BRANCH=none BUG=chrome-os-partner:55898 TEST=tpm does not lock up any more when 'tpm_client --own' is ran on the Kevin-tpm2 command line CQ-DEPEND=CL:367010 Change-Id: I20b4f54118bd2fa12e5bd5741d6c58fbe91f65d1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366796 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* servo_micro: increase SPI clockNick Sanders2016-08-081-2/+1
| | | | | | | | | | | | | | While SPI routing on servo is not great, this is still fine and asn't as painfully slow. BUG=chromium:571477 TEST=flash some firmware BRANCH=None Change-Id: I26d67ed6cd1ba62a892388e96a21acc708265fc4 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366670 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* servo_v4: servo_micro: cr50: fix usb power declarationNick Sanders2016-08-086-4/+32
| | | | | | | | | | | | | | | | | | | | | | | Servo_micro sets usb config maxpower to 100mA. Servo_v4 is set to self powered as it's powered by a shared vbus and not be the bub it's connected to. cr50 is self powered as no power is transmitted as part of CCD. * Add CONFIG_USB_MAXPOWER_MA to define USB maximum power draw requested per board. * Add CONFIG_USB_SELF_POWERED to indicate that a device is not powered by allocated USB power. BUG=chromium:631302 TEST=lsusb reports 100mA bMaxPower (micro), Self powered (v4) BRANCH=None Change-Id: I79b8ce46f32d94f16104a4a8080104e30dce7f2c Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363153 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lid_switch: Add console command to get virtual lid stateShawn Nematbakhsh2016-08-081-0/+11
| | | | | | | | | | | | | | BUG=chrome-os-partner:55975 BRANCH=None TEST=Manual on kevin, verify "lidstate" on console prints open / closed based upon state of lid. Change-Id: I76f1b63a536f76aee7b248fefdd17436773a6716 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366710 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cts: Added html output to ctsChris Chen2016-08-081-2/+39
| | | | | | | | | | | | | | | | | | | | When you run a test suite, cts will now save your results for the suite/dut combo as a basic html page BRANCH=None BUG=None TEST=Manual - Connect dut, th - Build/flash desired test suite - Run './cts -r' to run tests - Open /tmp/cts_results/<board_name>/<test_suite>.html - You should see a table with test names/results Change-Id: Id3de3bd7833be1bc5dde437c516db411aac47579 Reviewed-on: https://chromium-review.googlesource.com/362091 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cts: Refactored scriptChris Chen2016-08-081-296/+398
| | | | | | | | | | | | | | | | | | | | Added in classes for Board (parent), DeviceUnderTest, and TestHarness. Reading, etc. should be easier now BRANCH=None BUG=None TEST=Manual - Build default - Flash default - Run - Open /tmp/cts_results/nucleo-f072rb/gpio.html - Should see a clean results page Change-Id: Ide3f75281f0b5b8b40dabd36f8c239737dc527d6 Reviewed-on: https://chromium-review.googlesource.com/364236 Commit-Ready: Chris Chen <twothreecc@google.com> Tested-by: Chris Chen <twothreecc@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* g: fix rdd sleepMary Ruthven2016-08-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This change disables sleep only when a cable is actually detected. Before it would disable sleep no matter what and if a debug cable was not plugged in and then deteached then it would never enable it. BUG=none BRANCH=none TEST=manual update cr50 unplug suzyq boot to kernel verify cr50 is asleep run 'powerd_dbus_suspend' cr50 will wake up for like a second then go back to sleep run 'apreset' on EC console boot to kernel verify cr50 is asleep run 'powerd_dbus_suspend' cr50 will wake up for like a second then go back to sleep Change-Id: I8337f694853b7840ef932b38bd0fa6453d31cb3d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366861 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Fix minor typo.Marius Schilder2016-08-081-1/+1
| | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025 TEST=no typo observed. Change-Id: I698fd6de3656bcf6a048c1cadba21c8278603697 Reviewed-on: https://chromium-review.googlesource.com/366891 Commit-Ready: Dan Shi <dshi@google.com> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* btle: Add the HCI layerMyles Watson2016-08-085-1/+680
| | | | | | | | | | | | | | | | | | | Add a case statement to handle HCI commands. Add a test commands. Try to match the hcitool syntax, so the same commands can be executed on a Linux host. Added lcmd (long cmd) to pass more parameters in fewer arguments BUG=None BRANCH=None TEST=Use HCI commands to configure an advertiser and listen for it using `hcitool lescan` on the host. Change-Id: Ie28038847c9549eb1c27a605aa0fbad5efd3b2c7 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362145 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* btle: Add common link layer codeMyles Watson2016-08-088-1/+682
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=make BOARD=hadoken Add a task that is responsible for the state of the link layer. Change-Id: Ifc79bf1e4c57f5de448ab05b3a8d3a1aca5a58e2 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362144 Commit-Ready: Dan Shi <dshi@google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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