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* CR50: Include NUL byte from label for OAEP pad calculationstabilize-7912.Bnagendra modadugu2016-02-091-2/+2
| | | | | | | | | | | | | | | | | | If a label is specified, then the NUL terminating character is considered part of the label per the TPM2 implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2/ pass. Change-Id: If5fccc293f7ab52fd6c33e2f3c38695c2921d919 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/326910 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Marius Schilder <mschilder@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* MEC1322 port80 Acknowledge interruptIcarus Sparry2016-02-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In normal operation the 16 bit timer number 1 is set up to count every microsecond, and every 1000 counts (i.e. every millisecond) to assert an IRQ (Interrupt Request). After a microsecond the IRQ is deasserted.when the count is again not at its limit. The IRQ handler ignores the IRQ from the timer itself. If the clock is stopped or the autoreload of the counter is disabled then the value of the count is left unchanged. If this count is the limit then the IRQ will remain asserted. For stopping the clock this is approximatly a 1 in 1000 chance, or is certain if the autoreload is disabled. If the IRQ from the timer continues to be asserted, then the NVIC will continue to generate a fresh call to the IRQ handler as each previous exception completes. The fix is to do what almost every IRQ handler does for almost every processor, and clear the request in the peripheral that is causing the interrupt, rather than hoping that the timer will clear it itself. This agrees with how the event timer is used. There may be a lurking bug in the system timer handler as well as it also expects the timer to clear its own IRQ. BUG=chrome-os-partner:48499 TEST=Pass 2000s of continuous calls to port_80_interrupt_disable() / port_80_interrupt_enable() without WDT being triggered. Stop the autoreload and see it doesn't watchdog. BRANCH=glados Change-Id: I4726854b7784e2e4a39b8cb74c350206d71f90df Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://chromium-review.googlesource.com/326781 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: i2c: Print port name on failureShawn Nematbakhsh2016-02-091-2/+12
| | | | | | | | | | | | | | | | | | Referring to i2c ports as i2c0 thru i2c4 is confusing, due to the special naming of controller 0 ports, so use their actual names from the datasheet. BUG=None TEST=Trigger failure on i2c0_1, verify that "i2c0_1 bad status .." is seen on console. BRANCH=glados, strago Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ibd0d638e5af1c0a64e6f4b1a709b790b6b10d5e6 Reviewed-on: https://chromium-review.googlesource.com/325822 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: clock: Use full-speed 48MHz processor clock during EC bootShawn Nematbakhsh2016-02-097-4/+28
| | | | | | | | | | | | | | | | | | | EC boot / hash computing can be a bottleneck for system boot time. Reduce this bottleneck by running our processor at 48 MHz through boot, until vboot hashing of RW completes. BUG=chrome-os-partner:49583 TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and 'cbmem' delta between 'vboot select&load kernel' and 'finished EC verification' is reduced to ~250 ms (which includes sysjump time). BRANCH=glados Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326792 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Driver: isl9237: configures ACOK assertion to switching timeli feng2016-02-091-1/+3
| | | | | | | | | | | | | | | | | | Isl9237 default setting sets 1.3s debounce time from ACOK assertion to switching. It's too long for EC being notified AC is present. Change the value to 150ms. BUG=none BRANCH=glados TEST=In Kunimitsu system, plug in Zinger and capture timestamp when EC receive AC_PRESENT interrupt, it's reduced by ~1.2s. Change-Id: I2b027eef816949527138f7b8b53d5408fc823093 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/326844 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu: S0ix/S3 EC power improvementKyoung Kim2016-02-091-2/+2
| | | | | | | | | | | | | | | | | | | | USB2_OTG_ID and USB2_OTG_VBUSSENSE pins were floated due to open drain configuration. Improve EC power and remove power difference between S3 and S0ix. Improve EC power for SOC G3. BRANCH=firmware-glados-7820.B BUG=none TEST=measure EC powers at S3/SOC-G3 and S0ix and check if there are difference. Change-Id: I6471a05a1f5f75b5c805e80190a3cc7ac96d7c3b Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/326901 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 31bff74cff46bf80518cc269da304a1090cb7eea) Reviewed-on: https://chromium-review.googlesource.com/326991 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cr50: integrate register definitions consistent with real siliconVadim Bendebury2016-02-094-126/+99
| | | | | | | | | | | | | | | The new register definitions file has been supplied, it is not defining some fields which were present only in FPGA. Some tweaks are required to accommodate this. BRANCH=none BUG=chrome-os-partner:50141 TEST=new code successfully boots on the evaluation board Change-Id: Ie4158554e0aaf039d59669558861a763a23f0ceb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326803 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charger: Settings for charger current in no battery conditionVijay Hiremath2016-02-081-1/+6
| | | | | | | | | | | | | | | | | | | | | In case of no battery condition, current code sets the charger input current to the charger maximum input current. To avoid damage to the board, set the charger input current to the maximum current that the board can support. BUG=none BRANCH=none TEST=Manually tested on kunimitsu, removed the battery & then using EC console command 'charger', verified that the current value is set to 3000mA. Change-Id: I94c40228a6362822c841a6e0c226bea0d3398b73 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/325522 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: reduce PD log sizeli feng2016-02-082-2/+2
| | | | | | | | | | | | | | | | | | | | Before pd logging enabled, there is about 1320 bytes for shared meory; after pd logging is enabled and reserved 512 bytes, only around 780 bytes for shared memory. In shared_mem_acquire(), we request 1024(ChUNK_SIZE) while 780 only available. This causes hashing abort and could not boot to RW. BUG=chrome-os-partner:50127 BRANCH=glados TEST=In kunimitsu system, boot to RO and check available shared memory is higher than 1024; system can soft sync, boot to RW. Change-Id: Ic521a1eb95491cbe9351a800d6471449cbd7b084 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/326762 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* chell: Blink LED in S0iXDuncan Laurie2016-02-081-1/+1
| | | | | | | | | | | | | | | Blink the LED in S3 as well as S0iX states so there is no user visible difference in their behavior. BUG=chrome-os-partner:49274 BRANCH=glados TEST=Enter S0iX on chell (need SKU4) and verify LED blinks. Also verify that the LED still blinks in S3. Change-Id: I91b123de17787159f4e7d6aca2e86b80885b8f4e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326740 Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: Add initial elliptic curve crypto implementation.nagendra modadugu2016-02-0815-81/+2729
| | | | | | | | | | | | | | | | This change adds support for NIST-P256 curve operations. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=new tests under test/tpm2/ pass. Change-Id: I03a35ff3ab8af3c52282d882937880bfa2bdcd32 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324540 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* fmap: note fmap_name dependencyMary Ruthven2016-02-081-0/+1
| | | | | | | | | | | | | | | | fmap_decode now checks the fmap name to determine if the fmap it is decoding is the correct one. This change puts a comment in the ec fmap header to note the use. BUG=none BRANCH=none TEST=make buildall -j CQ-DEPEND=CL:322262 Change-Id: Icdd56eef5474b51cb178b6ba37c530c2357341b2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326450 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* CR50: enable the bignum library to handle word un-aligned keysnagendra modadugu2016-02-084-147/+135
| | | | | | | | | | | | | | | | | The TPM2 api does not require keys to be word-aligned, so have the compiler generate alignment-safe reads where necessary. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2/ pass, more TCG tests pass. Change-Id: I247e29f2bec139ab7ed4010ffb58cdae77ba9e0b Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/326201 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Plankton: Added support for normal dualrole operationScott2016-02-081-12/+75
| | | | | | | | | | | | | | | | | | | | | | | | Added a 'drp' option to the console command usbc_action that is used to toggle dualrole mode operation on and off. The default Plankton operation is not affected as this control is initialized to be disabled. When dualrole mode is enabled, then both CC lines are used and monitored. BRANCH=none BUG=chrome-os-partner:50074 TEST=Manual Tested Plankton connected to Samus. Verified that when dualrole mode is enabled that it can connect as both SRC and SNK. Tested with Type C cable initially connected and disconnected. In addition, verified that power role swaps behave correctly, and that when disabled, default Plankton operation is resumed. Change-Id: I60adfa25844a01a50ba45d5d92e17a3318f3e0a0 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/325545 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: provide plumbing for prod mode RO signingVadim Bendebury2016-02-082-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Creating bootloader for the chip involves signing the image with an 'air gap' - some physical presence action is required. We don't want this to be required when the builder is building cr50 for test purposes. The solution is to keep using the dummy private key when building by default, and invoking make differently when building an image which would be accepted by the hardware. Setting CR50_RO_KEY variable in the environment or in the make command line will cause the signer use the value of this variable as the name of the file containing the key to use for signing the RO image. Should this file be a public key, the signer will stop and look for a fob containing the matching private key, and will stream the RO image through the fob for signing. Using the fob requires that the signer runs under sudo, but we do not want the generated files to belong to root, some more code is added to change the generated files' ownership to user running the make. BRANCH=none BUG=chrome-os-partner:49950 TEST=ran the following tests: - verified that the build still succeeds by default. - invoked make as follows: CR50_RO_KEY=cr50_rom0-dev-blsign.pem.pub make BOARD=cr50 observed the signer stop to wait for the user to interact with the USB fob and proceed. Made sure that the generated image runs successfully on the evaluation board. - verified that 'make BOARD=cr50 clean' still works (i.e. none of the generated files is owned by root). Change-Id: I733ec6386c1dfd838d83d22fb589fa64e5eeaced Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326484 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: signer: pick up latest and greatestVadim Bendebury2016-02-083-8/+136
| | | | | | | | | | | | | | These are relevant changes in the FPGA tree since the most recent sync up. BRANCH=none BUG=chrome-os-partner:50141 TEST=image signed by the new signer boots successfully. Change-Id: Id30c5da614aa5c2496305f9687bce06030449beb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326483 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: no need to check for USB inclusionVadim Bendebury2016-02-081-7/+0
| | | | | | | | | | | | | | With transitioning to silicon there is no need to check if the hardware includes USB subsystem or not. BRANCH=none BUG=chrome-os-partner:50141 TEST=the cr50 image successfully boots to the ec prompt Change-Id: I593205cf307e0fce5e74ea695ed1cf5bfea8fde4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326482 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add public key for RO verificationVadim Bendebury2016-02-081-0/+9
| | | | | | | | | | | | | | | | | | This key matches the private key used by the chip's rom to verify the first stage user firmware. By virtue of the fact that this is a public key, the signer, in case this key is used, will look for a fob storing the matching private key to sign the read-only portion of the image. BRANCH=none BUG=chrome-os-partner:49950 TEST=none yet Change-Id: I0c55d5250a354eae8294560ef7b442fee6445b4f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326481 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* flash_ec: Disconnect EC-3PO interps when flashing.stabilize-7907.BAseda Aboagye2016-02-061-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Since the stm32 MCUs are programmed over the UART, we need to make some changes to allow the interpreter to stop listening to the UART PTY when flash_ec needs those PTYs. Otherwise, the EC-3PO interpreter will interfere with the programming and cause the flash to fail every time. BUG=chromium:571170 BRANCH=None TEST=Use flash_ec to program both veyron_jerry and samus_pd with no interruptions. TEST=Use flash_ec to program veyron_jerry without servod changes with no interruptions. CQ-DEPEND=CL:321084 CQ-DEPEND=CL:318900 Change-Id: I350fdb708d30c4ec6f18e5dc4abd621370522381 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/320629 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* nuc: Add support for CONFIG_LOW_POWER_S0.Mulin Chao2016-02-0610-43/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get better power consumption in S0, we add FW support for CONFIG_LOW_POWER_S0. Before entering deep idle in S0, we must enable Host interrupt to wake up EC if it needs to service LPC bus. This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal. In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR since preload counter is changed by __hw_clock_source_set all the time. We also found there're no event set if it's deadline is over 32 bits but current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if ITIM32 expires, FW set an event for ITIM32 after process_timers(). Modified sources: 1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition. 2. clock.c: Enable Host interrupt for LPC. 3. clock.c: Disable LP_WK_CTL for better power consumption. 4. gpio.c: Add ISR for Host interrupt. 5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed. 6. register.h: Add uart_clear_pending_wakeup function. 7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow. 8. fan.c: Enable deep sleep if duty cycle is zero. 9. include/system.h: Add SLEEP_MASK_FAN for fan control loop. 10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the instruction pipeline. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324651 Reviewed-by: Shawn N <shawnn@chromium.org>
* ectool: add inject-keys.pyLuigi Semenzato2016-02-052-0/+238
| | | | | | | | | | | | | | | | | | | A simple wrapper for "ectool kbpress" to do basic automation when working remotely (for instance, logging in). Includes a test script. BUG=b:26349756 TEST=ran on platform in various ways BRANCH=none Signed-off-by: Luigi Semenzato <semenzato@chromium.org> Change-Id: I96fdd99aa228b51cf22f9323facdc4ddb59db9ff Reviewed-on: https://chromium-review.googlesource.com/322286 Commit-Ready: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: Add initialization code required by TPM2 compliance tests.nagendra modadugu2016-02-051-0/+4
| | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115 TEST=initial TPM2 tests pass Change-Id: Ie614f29e578fb177245c33e6d1a896534a8d6095 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/326180 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Fix sleep mask for multi-port lock.stabilize-smaug-7897.BMulin Chao2016-02-041-8/+18
| | | | | | | | | | | | | | | | | | | This change use a simple counter to to prevent ec enter sleep if there's any i2c port active. Once there's no i2c port active, we enable sleep bit of i2c in i2c_lock() func. Please note FW disables interrupt during changing counter to prevent preemptive conditions. Modified sources: 1. common/i2c.c: Fix sleep mask for multi-port lock. BUG=crbug.com/537759 TEST=make buildall -j; test on wheatley when CONFIG_LOW_POWER_S0 is deifned. BRANCH=none Change-Id: I17c226108fee0e5d656fa157808179898f9a8dbf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/325256 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Modified the flash driver to retry operations as appropriate.Nadim Taha2016-02-041-38/+75
| | | | | | | | | | | | | | The max retry counts are based on the TSMC specification. This is a necessary change given that we're using their smart program/erase algorithms. BRANCH=none BUG=chrome-os-partner:45366 TEST=Tested RW updates. Change-Id: I18ca09e54ce13f2cf75dac32fb2457d5963ca040 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/325535 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kunimitus: add VCONN swap abilityli feng2016-02-032-0/+10
| | | | | | | | | | | | | BUG=none BRANCH=glados TEST=make -j buildall Change-Id: Ifa4273acbeab8b8463eddae2d9dde9c158f337a3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/325529 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Fix signed vs unsigned typingShawn Nematbakhsh2016-02-033-5/+2
| | | | | | | | | | | | | | | | | | - ec_response_thermal_get_threshold.value is unsigned, so it can not be less than zero. - make power_button_wait_for_release() take a signed int, to match its existing usage. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5748df3d9904d1e417adc38fee18f8cb3ce9750 Reviewed-on: https://chromium-review.googlesource.com/325840 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: ec3po: Add OOBM queue and dynamic loglevels.Aseda Aboagye2016-02-032-0/+25
| | | | | | | | | | | | | | | | | | | | | | This commit adds an Out Of Band Managament queue which will allow the console to receive commands outside of the PTY which it can take action on. The first use of this is to dynamically change the logging level. Prior to this change, changing the log level using dut-control would not affect the log level of the console or interpreter. BUG=None BRANCH=None TEST=Launch modified servod; issue dut-control loglevel:debug, verify that debug messages from both servod and ec3po are emitted. Then issue dut-control loglevel:info and verify that no debug messages from either are emitted. Change-Id: I692824742b018da9540a81305985f6f355f716e6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/325134 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* NPCX: Move control of PD GPIO hibernation state to boardAnton Staaf2016-02-032-16/+9
| | | | | | | | | | | | | | | | | | Use board_set_gpio_hibernate_state to configure the PD GPIO's to support charging while hibernating. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I7b960967670c07f4861a59345bc23c97d3f61cc0 Reviewed-on: https://chromium-review.googlesource.com/325443 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Enforce compilation without system headersStefan Reinauer2016-02-0317-11/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces HOST_CPPFLAGS to be used for all objects being compiled with HOSTCC rather then the target compiler. Since glibc is not linked into the EC, no glibc include files should be included in the EC code base. Hence, create local definitions for clock_t and wchar_t that match what the glibc include would have done, and remove some unneeded includes. Due to very eager optimization, we have to give gcc a little notch to not kick out memset. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:43025 BUG=chrome-os-partner:49517 BRANCH=none TEST=compile tested Change-Id: Idf3a2881fa8352756b0927b09c6a97473358f239 Reviewed-on: https://chromium-review.googlesource.com/322435 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* Chell: Setting battery charging maximum value of temperatureBruce2016-02-032-0/+34
| | | | | | | | | | | | | | | | | | | | | Setting battery charging maximum value of temperature. If battery temperture is over than 45 degree, set charge current to 0 mA, and charge state to idle. Then LED will turn to white in idle state. BUG=chrome-os-partner:49695 BRANCH=glados TEST=check the battery will not charge when battery temperture is over than 45 degree, and LED turn to white. Then temperture is less than 45 degree, the battery will charge and LED turn to amber. Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/323982 Reviewed-by: Shawn N <shawnn@chromium.org> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 4994d85d3b6c589e3ac297697aeb36456f2401a6) Change-Id: Ic7d3fe0c482fab76041c5ae3f35402e529576b1c Reviewed-on: https://chromium-review.googlesource.com/325487
* util: ec3po: Change console permissions to 660.Aseda Aboagye2016-02-031-3/+2
| | | | | | | | | | | | | | | | | 666 gives out permissions to everyone and should be avoided. A similar change is made in servod. BUG=None BRANCH=None TEST=Run console.py and verify that the created PTY has the permissions of 660. Change-Id: Ib58952af5f9681fdc2ef351b2c2ac2ec10109095 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/325493 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: fix unaligned memory accesses in dcrypto/aes.nagendra modadugu2016-02-031-4/+4
| | | | | | | | | | | | | BRANCH=none TEST=new tests under test/tpm2/ pass. BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: Ibfc92eae8238954a861a8e91432f90db6d174ead Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325495 Commit-Ready: Vadim Bendebury <vbendeb@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* kunimitsu: lars: enable USB PD logging.Todd Broch2016-02-032-0/+4
| | | | | | | | | | | | | | | | | | Enable USB PD logging. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=chrome-os-partner:45933 BRANCH=none TEST=make -j buildall make -j BOARD=kunimitsu tests Change-Id: I05f80712e2efe59a3a3cdf333885b111cc79953b Reviewed-on: https://chromium-review.googlesource.com/325380 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: fix incomplete hash state initialization.nagendra modadugu2016-02-021-0/+3
| | | | | | | | | | | | | | | | The hashAlg field is expected to be populated by _cpri__StartHash. BRANCH=none TEST=new tests under test/tpm2/ pass. BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I237183c916fa800a82853aee8def7d734f53d6e9 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325386 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* charger/Kunimitsu: Fix for boot from cut-off batteryVijay Hiremath2016-02-025-22/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery in cut-off mode wakes when voltage is applied to the PACK and takes approximately 2 to 3 seconds to initialize before capable of providing the power. Hence made the battery present status to BP_NO in case of cut-off mode. Once the battery is ready new status is updated as BP_YES. When the battery status changes from BP_NO to BP_YES, charger input current is set to board specific charger input current which is not sufficient to boot the AP hence the system reboots. To avoid this issue, added code to write charger manager negotiated current to charger input current when the battery status changes from BP_NO to BP_YES. BRANCH=none BUG=chrome-os-partner:49224 TEST=Manually tested on Kunimitsu. Used console command 'cutoff' to put the battery in cut-off mode. Inserted the adopter to wake the system, system doesn't reboot & the battery charges. Change-Id: Ia5a1457506b4bef0b3dd27993e4b60ae64c8f746 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322430 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Reduce the period of watchdog check timerCHLin2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | There is probability to fail in firmware_ECWatchdog FAFT test by using CONFIG_WATCHDOG_PERIOD_MS period for check timer. Use CONFIG_AUX_TIMER_PERIOD_MS instead can fix it. Modified drivers: 1. watchdog.c: change watchdog check timer period from CONFIG_WATCHDOG_PERIOD_MS to CONFIG_AUX_TIMER_PERIOD_MS. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I93e700968751ecd58f032c2f5866cf4f2eb0ffe4 Signed-off-by: CHLin <chlin56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324712 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: define EMBEDDED_MODE=1 for code under cr50.nagendra modadugu2016-02-021-0/+2
| | | | | | | | | | | | | | | | | | EMBEDDED_MODE was missing from code compiled under cr50/tpm2, which resulted in code under third_party/tpm2 and cr50/tpm2 inferring differing declarations for a given type. BRANCH=none TEST=tests under test/tpm2 pass BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I56935f5ae8fc45e6b7f71eb239b3e0c325086795 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/325471 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* pd: Reinitialize state variables on TCPC resetShawn Nematbakhsh2016-02-021-2/+5
| | | | | | | | | | | | | | | | | Resetting our state to default without also resetting the power role may lead to a state / role mismatch. BUG=chrome-os-partner:49563 TEST=Verify kunimitsu correctly detects charger at either polarity on sysjump. BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I239df9793773429e9b84a847e55d6753577fab32 Reviewed-on: https://chromium-review.googlesource.com/325385 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: signer should be a dependency for RW_B target tooVadim Bendebury2016-02-021-0/+1
| | | | | | | | | | | | | | | | | | | The makefile is missing an explicit dependency which ensures that the signer utility is available by the time the RW_B image is built. This works most of the time, but once in a while RW_B gets ahead in the race and the build fails. Adding explicit dependency will prevent this from happening. BRANCH=none BUG=chromium:578761 TEST=make buildall -j still succeeds. Change-Id: I7f5223f51e71b1d78de012bf5d934f1a17c86cc0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/325031 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Don't declare functions inline that aren't always defined as suchPatrick Georgi2016-02-022-3/+3
| | | | | | | | | | | | | | | | | | gcc 5.2 bails out on an inline declaration that isn't followed up with a definition in the same compilation unit. BRANCH=none BUG=chrome-os-partner:49517 TEST=compile tested with coreboot's toolchain. samus, oak and others that failed now build. Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/324970 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* chell: Enable S0ix power state supportDuncan Laurie2016-02-012-2/+3
| | | | | | | | | | | | | | | | Enable the config option for S0IX power control and set the GPIO to use power_signal_interrupt_S0. BUG=chrome-os-partner:49274 BRANCH=glados TEST=echo freeze > /sys/power/state Unfortunately currently SLP_S0_L is not asserting so this is difficult to actually test the EC behavior Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324567 Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix null pointer check in tokenFilename()Stefan Reinauer2016-02-011-1/+2
| | | | | | | | | | | | | | | | | | | From https://scan.coverity.com/projects/chromium-ec : CID61407: Dereference after null check The home directory that is received from getpwuid() needs to be assigned to home but it wasn't. BUG=none BRANCH=none TEST=build tested Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I36c30906e1388e2f8a0d466d516a5ffa6ae70bf6 Reviewed-on: https://chromium-review.googlesource.com/324637 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Fixed soft resets on silicon.Nadim Taha2016-02-012-56/+87
| | | | | | | | | | | | | | Fixed the peripheral clock enable definitions and enabled the low speed timers. BRANCH=none BUG=none TEST=Tested soft resets on silicon. Change-Id: Ie63e5732e5bead174abda89e5c5069b818212e9b Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324843 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Removed references to FPGA-only registers from the bootloader.Nadim Taha2016-02-011-6/+2
| | | | | | | | | | | BUG=none BRANCH=none TEST=Booted to an RW image on silicon. Change-Id: Iadca3c05cfd095427867d877e4a916c999a9cdb3 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324803 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Kunimitsu: Change the battery minimum voltage valueVijay Hiremath2016-01-311-1/+1
| | | | | | | | | | | | | | | | | Charger Low_VSYS_Prochot# threshold voltage assertion is set to 6V hence increased the minimum battery voltage to 6.1V to avoid unwanted Prochot# assertions. BUG=none TEST=Drained the battery to 6.1V, Prochot# pin did not assert. BRANCH=glados Change-Id: Ie5d4decf3327a45d64638771dd8a5fc7017db261 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/324564 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* CR50: implement _cpri__StirRandom as a no-op.nagendra modadugu2016-01-293-8/+12
| | | | | | | | | | | | | | | | Stirring the random pool on CR50 is not currently supported, so just implement as a no-op. TEST=none BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I32b0144737139e524d4f71a11cc9d4ad939cd9cb Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324620 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* it8380dev: util: Enhance iteflashDonald Huang2016-01-291-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add verify function. BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" /* ==SNAPSHOT START== */ (cr) (b-verify) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB Done. CHIPID 8390, CHIPVER 82, Flash size 256 kB Erasing chip... /100% Writing 262144 bytes at 0x00000000 Done. Verify 262144 bytes at 0x00000000 -100% Verify Done. /* ==SNAPSHOT END== */ Change-Id: Iac08e2eeb934c3a4a721e17a85de628ea4d9d065 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/322524 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chell: Trigger PMIC shutdown rather than hibernateShawn Nematbakhsh2016-01-281-9/+17
| | | | | | | | | | | | | | | | | | Shut down all PMIC-supplied power rails rather than initiating EC / PD hibernate. This results in considerable power savings. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual on chell. Run "hibernate" on EC console, verify that 3.3V EC DSW rail goes to 0V, and the EC powers up on zinger insert, lid open or power button press. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I7bf0c494ea240183240f5a6abc3d611df8efb45a Reviewed-on: https://chromium-review.googlesource.com/324087 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add hibernate board-level callbackShawn Nematbakhsh2016-01-287-0/+25
| | | | | | | | | | | | | | | | | Allow boards to take action (such as entering a custom low-power hibernate-like state) before putting the chip into hibernate state. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual with subsequent commit on chell. Verify board-level hibernate callback is called when "hibernate" is run on EC console. Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324086 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Fixes the SFDP_BITFIELD() macro.Nadim Taha2016-01-291-1/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=<redacted> Change-Id: If6e2732a29e084417ba1d2f80732ac412028342a Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324622 Reviewed-by: Ewout van Bekkum <ewout@chromium.org>
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