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* sb_firmware: shorter console messagesstabilize-6842.BSheng-Liang Song2015-03-021-3/+1
| | | | | | | | | | | | | | | Reduced console log messages BUG=chrome-os-partner:36310 BRANCH=none TEST=Compile Only Change-Id: I0e30a3094d77673a5fd238efed3851a726fdcdb6 Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254931 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
* nrf51: Reset clean up.Myles Watson2015-03-023-12/+22
| | | | | | | | | | | | | | | | Use the values from the datasheet to report the reset reason. TEST=hard reset, soft reset, wake from sleep with a GPIO BRANCH=NONE BUG=None Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I2a45741c9c17f0c2e4eb4b8b12d3231f407244dd Reviewed-on: https://chromium-review.googlesource.com/254112 Tested-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org>
* Producer/Consumer: Convert USART and USB Stream driversAnton Staaf2015-03-026-296/+221
| | | | | | | | | | | | | | | | | | | | | | | Previously the USART and USB Stream drivers exposed in_stream and out_stream interfaces, which don't allow for sharing their queues easily. This change converts these drivers over to the producer/consumer model and updates the two uses. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verify that the discovery echo functionality is unchanged. Change-Id: I29f043ab1712373f638e1621378df98647d736cf Reviewed-on: https://chromium-review.googlesource.com/252820 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* pd: Bugfix for write log entry command.Todd Broch2015-03-021-1/+1
| | | | | | | | | | | | | | BRANCH=samus BUG=chrome-os-partner:37264 TEST=manual, ectool --name cros_pd pdsetmode 0 0xff01 1 0 successfully exits displayPort mode again. Change-Id: Ica2faf8de92460f01c2af9be829795c0cd538135 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254990 Reviewed-by: Shawn N <shawnn@chromium.org>
* plankton: always run as UFP when in USB hub modeVic Yang2015-03-023-10/+25
| | | | | | | | | | | | | | | | | | When Plankton is in USB hub mode, running as DFP doesn't make sense. In this case, ask for a data swap. BRANCH=None BUG=chrome-os-partner:37079 TEST=With Ryu, check Plankton is always UFP no matter it's sink or source. Change-Id: I7752b8c1255234a5ea726138708fe52c5fcd47b2 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/254713 Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Revert "mec1322: Fix LPC interrupt bit mask"stabilize-6835.BVic Yang2015-02-281-4/+4
| | | | | | | | | | | | | | | | | | This reverts commit 9ed4434ad8770ca3edd6bccd456738019c9e08b0. According to MEC1322 errata, LRESET# interrupt is indeed GIRQ 19 bit 1. BRANCH=None BUG=chrome-os-partner:36326 TEST=None Change-Id: I9d0dc0ef3abac1ace59b46eafae04f6b9e5c0b9b Reviewed-on: https://chromium-review.googlesource.com/254771 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* sb_firmware: clean up sb firmware update programSheng-Liang Song2015-02-281-53/+55
| | | | | | | | | | | | | | | | | | | | | | | | - battery firmware filename need match with gs:// filename - changed from "%04X" to "%04x" - A fix for LGC battery firmware update. - Add control flags: F_AC_PRESENT - 1 iff AC is connected. F_VERSION_CHECK - 1 if do version check - option to disk version check for stress test. - Add detail log messages - Remove old debug flag. BUG=chrome-os-partner:36310 BRANCH=none TEST=run ec_sb_firmware_update on glimmer Change-Id: Iebc15222a7a55a786291ce2d8931e70acc5b3c4d Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253970 Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f0: Fix RTC read glitchShawn Nematbakhsh2015-02-281-1/+7
| | | | | | | | | | | | | | | | Reads to RTC_SSR may be invalid if they occur close to the RTCCLK edge. As suggested by the datasheet, perform consecutive identical reads to ensure the read is valid. BUG=chrome-os-partner:37216 TEST=Manual on Samus. Repeatedly call rtc_read in test function, verify that RTC_SSR never incorrectly ticks up. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib26fbfab4a07263f638c580066e993675dd8c451 Reviewed-on: https://chromium-review.googlesource.com/254725 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* samus: don't unwedge charging when purposely discharging on ACAlec Berg2015-02-283-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | For factory testing, when purposely discharging on AC, don't automatically detect and unwedged charge circuit. BUG=chrome-os-partner:37171 BRANCH=samus TEST=plug in AC and run: "ectool chargecontrol discharge". check on ec console that battery is discharging. let sit for 3 minutes and make sure charge circuit unwedge code never runs. run "ectool chargecontrol normal" and make sure battery starts charging again. Also force discharge with "ectool chargecontrol discharge" and then unplug and replug AC, make sure battery is not charging nor discharging, then set mode back to normal and make sure we start charging again. Tested without this CL and everytime you force discharge the charge unwedge is activated and messes everything up. Change-Id: Icc7a504c148e1e08777e7aafce64ff4cc38a32c5 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254722 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* nrf51: add RNG definitions to registers.hMyles Watson2015-02-281-0/+21
| | | | | | | | | | | | | | | | RNG (Random Number Generator) register definitions from the datasheet TEST=buildall BRANCH=NONE BUG=None Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: Id700564edfa8021aa5604ed53f7ccfe8c3c4f6db Reviewed-on: https://chromium-review.googlesource.com/254111 Tested-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org>
* nrf51: add definitions for RADIO and FICR registers.Myles Watson2015-02-281-0/+183
| | | | | | | | | | | | | | TEST=tested that the radio sends and receives packets correctly. BRANCH=NONE BUG=None Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I7f59521062558be90c217013e2ea2dae502005c4 Reviewed-on: https://chromium-review.googlesource.com/254110 Tested-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org>
* charge_state_v2: return correct host command error codesAlec Berg2015-02-281-2/+2
| | | | | | | | | | | | | | | | Return host command error codes for EC_CMD_CHARGE_CONTROL instead of returning the result of EC functions which typically return element from enum ec_error_list, which is a different error list. BUG=chrome-os-partner:37171 BRANCH=samus TEST=make -j buildall Change-Id: Ia13cc8a2f747ddeafdc059c6e575dcc2f5b20b8d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254721 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Remove unused CONFIG_PSTATE_AT_END optionRandall Spangler2015-02-274-41/+3
| | | | | | | | | | | | | | | | All current boards in ToT place pstate at the end of the RO section. Remove the unused option to place it at the end of the RW section; we'll never do that again. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I0d279a4c9786bb33367a7387423481cc9b94e115 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253636 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: avoid shell errors when building for hostBill Richardson2015-02-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When building hosttests, CONFIG_FLASH_BASE is not a numeric constant (it's a pointer to a buffer). This makes the the shell complain when the Makefile tries to convert it from hex to decimal. Since the Makefile only needs that value to convert .bin to .hex, let's just wait to calculate it until we need it. BUG=chrome-os-partner:37071 BRANCH=none TEST=manual Before, "make hosttests" printed a bunch of this: sh: ((uintptr_t)__host_flash): missing `)' (error token is "__host_flash)") Now it doesn't. Change-Id: If408eb347b4f2385893d53cdfbf8fd5033868737 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254410 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus_pd: Skip pericom detection if we're sourcing VBUSShawn Nematbakhsh2015-02-271-14/+20
| | | | | | | | | | | | | | | | If we're sourcing VBUS, there is no need to proceed with the pericom debounce / reset procedure, since we know that we're not charging. BUG=chrome-os-partner:37137 TEST=Manual on Samus. Insert USB keyboard, verify that pericom reset doesn't occur. Insert SDP port + Apple charger, verify that pericom reset / redetection still occurs. BRANCH=Samus Change-Id: I1a616f6e2287cd474b94e8fb61c19514d2ec2042 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/254140 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* charge_manager: Classify VBUS supplier typeShawn Nematbakhsh2015-02-273-1/+8
| | | | | | | | | | | | | | | | Add a new supplier type for VBUS chargers (USB chargers which supply VBUS but are not identified as another charger type). BUG=chrome-os-partner:37168 TEST=Manual on Samus with subsequent kernel commit. Modify code to reject all non-VBUS suppliers, charge with SDP port, and verify charge icon appears in OS. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5fbdb1cb57bd0224b01aaf5a763f93b678b6d204 Reviewed-on: https://chromium-review.googlesource.com/254346 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* npcx: Use SPI status register instead of pstateRandall Spangler2015-02-263-89/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npcx chip and evb use a SPI flash chip to hold the EC image. They don't need pstate, and should use the SPI flash status register directly. 1. Remove CONFIG_FLASH_PSTATE from npcx_evb. 2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect line to the SPI flash chip). 3. Change the npcx flash driver so that it directly reads/writes the SPI status register instead of mucking with pstate. BUG=chrome-os-partner:34346 BRANCH=none TEST=manual Add a switch or jumper to the EVB so R1 can be closed. Toggle the switch and see that WP_L state changes. Leave enabled. flashinfo -> nothing is protected, WP_L is enabled (=0) (also do this after each flashwp command to check the protection status) flashwp enable -> RO is protected now and at boot. reboot flashwp enable -> RO is still protected. flashwp disable -> RO is still protected. (because WP switch is enabled). Toggle the switch so WP_L is disabled (=1) flashwp disable -> Succeeds, flash is not protected Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253633 Reviewed-by: Shawn N <shawnn@chromium.org>
* Add CONFIG_FLASH_PSTATE option to enable persistent flash WP stateRandall Spangler2015-02-264-16/+41
| | | | | | | | | | | | | | | | | | | | | | | Previously, the flash module assumed it needed to emulate a SPI write protect register using a bank of flash to hold the persistent flash write protect state. This is not true for mec and ncpx chips under development, which use external SPI flash. So, gate that code with CONFIG_FLASH_PSTATE. For compatibility, leave it on by default (as we do with CONFIG_FLASH_MAPPED). There is no change to the behavior of currently supported chips, since all of them already assume pstate is present. Removing this feature from npcx will be done in a subsequent change. BUG=chrome-os-partner:34346 BRANCH=strago TEST=make buildall -j; verify flash wp and flashinfo work properly on samus Change-Id: Ie044eb042863e4a7359ea540166ffd8d0089589d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253632 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* cr50: enable signed RW imagesBill Richardson2015-02-256-9/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This signs the RW firmware (with a non-secret key). The RO firmware will verify the RW firmware and jump to it if it's good. Note that this isn't the final solution, just the beginning. BUG=chrome-os-partner:37071 BRANCH=none TEST=manual Build and install it. You'll see something like this: --- UART initialized after reboot --- [Reset cause: reset-pin hard] [Image: RO, cr50_v1.1.2929-27e1b82-dirty 2015-02-24 14:36:29 wfrichar@wfrichar-glaptop] [0.000444 Verifying RW image...] [0.423742 RW image verified] [0.423946 Jumping to image RW[0.428492 UART initialized after sysjump] [Image: RW, cr50_v1.1.2929-27e1b82-dirty 2015-02-24 14:36:29 wfrichar@wfrichar-glaptop] [0.428931 Inits done] Console is enabled; type HELP for help. > > sysinfo Reset flags: 0x00000c02 (reset-pin sysjump hard) Copy: RW Jumped: yes Flags: unlocked > Change-Id: Icafa554baca135ff1f80cbce4dad5f980e7fc122 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253081 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add USE_GIT_DATE=1 to make args to build repeatable imagesBill Richardson2015-02-252-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now, every image includes the time of compilation in the build information. This makes it impossible to verify that a particular image came from a particular source code snapshot. With this change, specifying USE_GIT_DATE=1 to the make command will use the author date of HEAD as the timestamp. That means that successive builds from the same source will produce bitwise-identical output (assuming the same toolchain, of course). BUG=none BRANCH=none TEST=manual Do this twice: \rm -rf build make BOARD=cr50 USE_GIT_DATE=1 md5sum build/cr50/ec.bin The md5sum should be the same for both runs. Change-Id: If64307101a453cb13c62fa003f1bf432f4998273 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252751 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Massage initialization at task start.Todd Broch2015-02-2517-32/+121
| | | | | | | | | | | | | | | | | | | | | | | | | Refactoring effort to unify the set of PD intialization tasks that need to occur. Those areas include: 1. host mode as it relates to power & pull-ups/downs 2. PD tx init 3. PD mux settings Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:36481 TEST=manual, 1. compiles and functions on samus_pd 2. If sysjump w/ dongle connected than alternate mode re-entered properly including muxing and HPD Change-Id: I47f32acaeccbd7745e1e01a8b085b1804c4c5000 Reviewed-on: https://chromium-review.googlesource.com/249273 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* WIP - Nuvoton 30-Jan patchRandall Spangler2015-02-2525-243/+419
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues fixed on 0216: 1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c 2.Modified warm_reset checking in gpio.c 3.Modified system_get_chip_name in system.c for package info. 4.Modified fan.c and pwm.c for: ● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low. ● Fan stall condition event: If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called. 5. Change cycle_pluses to 480 in board.c Issues fixed: 1. Jump data at top of RAM is getting corrupted. Changed the flag to RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST issue. 2. Hibernate wake need to report whether wake reason was GPIO or RTC 3. Hibernate wake must be distinguishable from watchdog reset. The booter will log reset reason in Code RAM. I copy the log data to battery-backup RAM in little FW. And system driver will refer this data to distinguish if it's watchdog reset or not. 4. Watchdog reset flag is not set. Same fix as 3. 5. Should return error if unable to clear SPI flash status register. 6. Remove chip_temp_sensor.c 7. Remove use of pstate from flash driver 8. Remove support for watchdog warm reset 9. Keyboard raw driver must support COL2 inverted 10. LPC memory mapped data must be read-only from host 11. LPC should support PLTRST# signal 12. Problems reading chip type/version. Use core registers and ROM data to read IDs. 13. When chip type/version is unknown, report hex value. 14. Watchdog does not consistently print panic information. 15. Remove console force enable logic. 16. Enable only the peripheral clocks that are needed. Please notice user should add bit mask in CGC_XXX_MASK if they want to enable additional module. For example, if user wants to enable PWM3, he must add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK. Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions. If I turn off all I2C modules in system_pre_init and turn on the modules I need in i2c_init, I found its freq is not correct. The root cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in clock_init) before i2c_init. At this time, i2c modules are power-down and writing to freq register is useless. I re-execute freq-changed hook function after turning on modules again. 17. MPU properly configured to prevent code execution from data RAM 18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM. Additional items we also modified: 1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func array to support it) 2. ec_npcxflash.c: Use definition to replace constant value. Stop watchdog during flash programing. 3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock MPU commands for Data RAM. BUG=chrome-os-partner:34346 BRANCH=none TEST=manually verify changes Change-Id: I722a77d29e7543b054819480c7b7477af4263119 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248670
* cortex-m0: Fix branch from 64-bit signed to unsigned divideRandall Spangler2015-02-251-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We put each assembly function in its own section. So the sections for 64-bit signed and unsigned divide end up too far apart for b<cond> (8-bit delta) or b (11-bit delta). Instead, use bl, which has no such limit. This is a little less efficient in the case where numerator and denominator are both positive, but equivalent if either or both is negative, and is far outweighed by the cost of the unsigned divide itself. The other alternative would be to put both uldivmod and ldivmod in the same section. However, we're often tight on code size on cortex-M0 parts, so that's less desirable. BUG=chrome-os-partner:26126 BRANCH=minnie TEST=add the following function static int command_divtest(int argc, char **argv) { int64_t a, b, c; char *e; if (argc < 2) return EC_ERROR_PARAM_COUNT; a = strtoi(argv[1], &e, 0); b = strtoi(argv[2], &e, 0); c = a / b; ccprintf("%d / %d = %d\n", (int)a, (int)b, (int)c); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(dt, command_divtest, "a b", "Divide test", NULL); and test with divides in all 4 quadrants (+/- 20 divided by +/- 5, for example) Change-Id: I2a5e49c4534044c2f509e325f8dd6bdf10b544c4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252243 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lightbar: make tap red threshold match low battery thresholdAlec Berg2015-02-251-2/+3
| | | | | | | | | | | | | | | | | Make tap for battery red threshold match the low battery red threshold. BUG=chrome-os-partner:36811 BRANCH=samus TEST=use a fake battery console command to change battery percentage on samus and make sure that the same level at which lightbar turns red in S0 is the same level at which tap for battery shows red. Change-Id: I084c8412beac4f5b311eb30f46f4f3273e9f2456 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252351 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: make sure EC sends battery percentage to PD on changeAlec Berg2015-02-251-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure the EC sends the battery state of charge to the PD every time it changes. BUG=none BRANCH=samus TEST=create command to fake battery percentage in driver/battery/smart.c: static int cmd_battfake(int argc, char **argv) { char *e; if (argc > 1) batt_fake = strtoi(argv[1], &e, 0); return EC_SUCCESS; } DECLARE_CONSOLE_COMMAND(battfake, cmd_battfake, NULL, "", NULL); and in battery_get_params(): if (batt_cap > -1) batt_new.remaining_capacity = batt_cap; On samus use battfake command to change battery percentage back and forth every few seconds for minutes and make sure the PD receives host command 0x100 and that it is still happy. Change-Id: Ic69ab2af900fa2a38e3d2f6562675684487f556e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252350 Reviewed-by: Shawn N <shawnn@chromium.org>
* USART: Add STM32F3 support and fix STM32F baud rate bugAnton Staaf2015-02-247-15/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the STM32F3 support was non-functional due to it being a cut and paste of the STM32F0, and the clocks are not set up the same way on the two platforms. Also, the STM32F initialization code was incorrectly calling the F0/L buad rate setup code. This change has the variant specific USART code pass the input frequency to the baud rate divisor clock to the baud rate setup code, instead of that code calling clock_get_freq() to determine the input clock frequency. This is required because the STM32F3 is not configured such that the clock_get_freq value and the input to the USART baud rate divisor match. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verify USART works on discovery as well as Ryu Change-Id: I71248d83b53969d0e7020747a9bb9570803f30ac Reviewed-on: https://chromium-review.googlesource.com/250920 Reviewed-by: Vic Yang <victoryang@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* panic: Send host event on panic detectShawn Nematbakhsh2015-02-243-3/+22
| | | | | | | | | | | | | | | If a panic caused us to reboot, send a host event to notify the AP. BUG=chrome-os-partner:36985 TEST=Manual on Samus. Trigger EC panic, verify that "Panic Reset in previous boot" is seen in /var/log/eventlog. BRANCH=Samus Change-Id: Icf0d00a8cfc7aa788f3ceadd65fe3139f40df503 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/252410 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Remove ryu_p1 boardVic Yang2015-02-2412-857/+1
| | | | | | | | | | | | | | | | | P1 boards are not used anymore. We haven't built ryu_p1 EC for a while. Let's get rid of it. BRANCH=None BUG=chrome-os-partner:35138 TEST=make buildall Change-Id: Ie0c0b91ce0af99a0975050935af920503ca7383a Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/252340 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Streams: Define a lower level abstraction for queue accessAnton Staaf2015-02-247-2/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a new pair of interfaces called producer and consumer which are simpler (in that they don't hold onto the underlying queue) than the stream interfaces. This makes it easier to share a single queue between the endpoints that will manipulate it. It was not possible to share a queue between two objects that implemented the in_stream and out_stream interfaces. This also adds a pair of adaptors that can convert a producer or consumer into a stream of the correct type. These adaptors will be used for existing code once the usb-stream and usart drivers are converted over to use the producer/consumer interfaces instead of the stream interfaces. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I42b4b1ac15cca28e1adc6d3cea315f15e17a0b4d Reviewed-on: https://chromium-review.googlesource.com/250941 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* samus_pd: make shmem command optional, disable on samus_pdAlec Berg2015-02-243-0/+4
| | | | | | | | | | | | | | To save flash space, disable "shmem" console command on samus_pd to save 128 bytes. BUG=none BRANCH=samus_pd TEST=make-j buildall Change-Id: I0d0277a0c4a80dffd90dcbf2c3ee77eba2408c57 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251911 Reviewed-by: Shawn N <shawnn@chromium.org>
* samus: change USB type-A ports to default to CDPAlec Berg2015-02-231-0/+1
| | | | | | | | | | | | | | | | | Change USB type-A ports to default to CDP. The port will automatically revert back to SDP if it needs to. BUG=chrome-os-partner:36876 BRANCH=samus TEST=load on samus, make sure ports advertise as CDP by connecting A to C port to charge itself (note this causes other problems, but good enough to make sure we detect CDP). Change-Id: Ic09b31788557d2c6ff4292c62a2ac0168b136c64 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251834 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* stm32f0: fix handling of RTC alarm 24 hour rolloverAlec Berg2015-02-221-0/+6
| | | | | | | | | | | | | | | | | | | | Fix bug in RTC module for stm32f0 in which it doesn't handle the 24 hour rollover appropriately and can cause a watchdog reset if in deep sleep during rollover. BUG=chrome-os-partner:36920 BRANCH=samus TEST=add line to rtc_init() STM32_RTC_TR = 0x00235952 This initializes RTC clock to 8 seconds before rollover. Using samus make sure unit is allowed to go to deep sleep (S3/S5 and not charging) and see that without this CL we watchdog most of the time, and with this CL we don't watchdog ever. Change-Id: I3f4b4b1ab7b2be1d4e344477d5eaaa0dc916773a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251852 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* ryu: add charge ramp moduleAlec Berg2015-02-214-2/+60
| | | | | | | | | | | | | | | | | Add charge ramp module to samus. For BC1.2 DCPs allow ramping up to 2A, and for BC1.2 SDPs allow ramping to 1A. BUG=chrome-os-partner:34946 BRANCH=none TEST=tested with a variety of BC1.2 chargers, type-C only chargers, and PD chargers to make sure we always stabilize charging at an appropriate current limit. Change-Id: I63d4ba38f2e137aff32831386f1bde2cc7c57850 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/249934 Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* stm32f3: Allow per-board ADC sampling timeVic Yang2015-02-212-6/+16
| | | | | | | | | | | | | | | | | | Depending on the hardware, each ADC channel may need a different sampling time. To keep things simple, let's allow per-board ADC sampling time configuration instead of per-channel configuration. BRANCH=Ryu BUG=None TEST=Configure sampling time to 3 and measure IADP on Ryu P4 and check it's more accurate. Change-Id: I3c1eeea22439c0340f84fdeb3624fc84450358ca Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/251701 Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* samus_pd: remove resetting pericom 30 sec after detecting SDPAlec Berg2015-02-211-20/+3
| | | | | | | | | | | | | | | | | | Remove resetting pericom 30 seconds after detecting SDP. This is not helpful anymore since we have fixed pericom detection problems and have a charge ramp for SDPs. BUG=chrome-os-partner:36813 BRANCH=samus TEST=connect samus A port to samus C port. this detects as SDP and ramps to 1A, but every 30 seconds resets the pericom. with this change it detects SDP, ramps to 1A and stays constant. Change-Id: I2400a06d237cef8c03f921960954dcf54d93de1e Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251583 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* common: Add the possibility to filter UART inputMyles Watson2015-02-213-0/+24
| | | | | | | | | | | | | | | | | | | Add CONFIG_UART_INPUT_FILTER, which is undefined by default. BUG=chrome-os-partner:36745 TEST=buildall for the case where it is not defined. Added a filter function to the btle code on hadoken. Tested reset, transmit test, receive test, test end, and test mode end. BRANCH=None Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I3a9c067ffcb114449b61f468271a48491a8c7ec5 Reviewed-on: https://chromium-review.googlesource.com/250580 Tested-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org>
* timer: usleep: Use HW clock to detect elapsed sleep timeAlec Berg2015-02-211-1/+9
| | | | | | | | | | | | | | | | | | | If a non-timer task event is received while in usleep, we will again attempt to sleep for the entire duration. This can cause an infinite sleep in cases where a periodic task event occurs. Fix this by checking the HW clock for our elapsed duration. BUG=chrome-os-partner:36864 TEST=Manual on Samus. Verify that we don't get stuck in usleep during VCORE_PGOOD interrupt storm. BRANCH=Samus Change-Id: Ie3ab8ce3c22822095845a3d9a6f33bd4b1273c6e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251311 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus: Only enable VCORE_PGOOD interrupt when it is validDuncan Laurie2015-02-201-0/+15
| | | | | | | | | | | | | | | | The VCORE_PGOOD signal to the EC goes through a buffer which is powered by PP1050_VCCST that itself is gated by SLP_S3. Until this point the input is invalid and may be oscillating so only enable it as an interrupt once we are in S3->S0 state. BUG=chrome-os-partner:36864 BRANCH=samus TEST=boot on samus to ensure power sequencing still works properly Change-Id: I90ad3b578297a5194c110407be1cba2d65226290 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251324 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* charge_state_v2: Do not draw max input current if battery is presentVic Yang2015-02-201-12/+11
| | | | | | | | | | | | | | | | | | | | | Currently we set the input current limit to its maximum when the system is unlocked, so that we can boot the system with a powerful charger when the battery is absent. However, with a low power charger, we risk browning out the charger. If the battery is present, reduce the input current limit so that low power chargers work in this case. BRANCH=None BUG=None TEST=On Ryu, reboot EC when the a low power charger is used. Without this change, the charger browns out right after the reboot. With this fix, the problem doesn't happen anymore. Change-Id: I9d491cbe45e77f864198c97a47624918e6c272db Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/248442 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* samus: samus_pd: Increase task stack sizesShawn Nematbakhsh2015-02-202-7/+5
| | | | | | | | | | | | | | | Since we have RAM to spare, increase the stack sizes of certain tasks that may come close to stack overflow. BUG=chrome-os-partner:36914 TEST=Manual on samus / samus_pd. Run task_info, verify new task stack sizes. BRANCH=Samus Change-Id: Id667f963bffbf7776e7cbe07b7e7d34f4ac27398 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251420 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* EC: Support firmware updater to auto select a battery fw imageSheng-Liang Song2015-02-202-144/+221
| | | | | | | | | | | | | | | | Auto select a battery firmware image based on the current "battery info." sprintf(auto_image_name,"/lib/firmware/battery/maker.%04X.hwid.%04X.bin" maker_id, hardware_id); BUG=chrome-os-partner:24741 BRANCH=glimmer TEST=Verified Simplo Battery Update on glimmer Change-Id: Ie6b2f797a4629fdde3a45e9a6a83c4568655db7a Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250130 Reviewed-by: Shawn N <shawnn@chromium.org>
* samus: add i2c retries to backlight controlAlec Berg2015-02-201-15/+69
| | | | | | | | | | | | | | | | | | Add i2c retries to backlight control. Also check return value, if i2c transfer fails, do not continue. Also modified backlight control so that we only send I2C commands when backlight chip is enabled (in S0 and lid is open). BUG=chrome-os-partner:36803 BRANCH=samus TEST=test suspend/resume and booting and make sure panel always comes up. Change-Id: I0dd71c12d0c3f64a08fb389c37f64b1b0ac16fb8 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250670 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cr50: Separate ARM core GPIOs from pinmux configurationBill Richardson2015-02-208-179/+276
| | | | | | | | | | | | | | | | | | | | This separates the configuration of the ARM core GPIOs from the routing of internal peripherals to external pins. Both are still described in the gpio.inc file, but are less dependent on each other. BUG=chrome-os-partner:33818 BRANCH=none TEST=manual Before this CL, running "sysjump rw" or trying to use more than 8 GPIOs caused hangs and reboots. Now it doesn't. Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251015 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Add ec.hex to hex: build targetBill Richardson2015-02-201-1/+5
| | | | | | | | | | | | | | | When the default build target creates .hex files, emit the complete ec.hex output as well as the RO and RW halves. BUG=none BRANCH=none TEST=make BOARD=cr50 Change-Id: Ia87bbace29d89695ef6a9c090c895ca10f14d919 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251014 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: bitmasks should be unsigned valuesBill Richardson2015-02-201-1/+1
| | | | | | | | | | | | | | | Change the struct gpio_info to use uint32_t for the mask field, instead of signed integer. BUG=none BRANCH=none TEST=make buildall Change-Id: I8cc7e3d06a00bd3c890522a896e36e1eb18a862e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251013 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Don't admit the existence of unimplemented gpiosBill Richardson2015-02-201-1/+1
| | | | | | | | | | | | | | | | | | | For boards with unimplemented GPIOs, don't display those GPIOs in the output of "gpioget" or accept them as signal names in "gpioset". BUG=none BRANCH=none TEST=manual Pick a board with an unimplemented GPIO (search board/*/gpio.inc for UNIMPLEMENTED), run "gpioget" and "gpioset". It shouldn't show up. Change-Id: I343ece7d6df5fa09fda8418e3f3148d74f1540ae Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251012 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Poke the watchdog when dumping lots of memoryBill Richardson2015-02-201-0/+9
| | | | | | | | | | | | | | | | | | | If you use the "md" command to display lots of memory, it can cause the watchdog to trip. This just pokes it every now and then to be sure it's happy. BUG=none BRANCH=none TEST=manual Print a lot, see that it doesn't timeout: md 0 0x4000 Change-Id: Ic4e2746c07f4fbdf922e87ea3efbe90b88ae08c9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251011 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* panic: fix logging of watchdog in panic dataAlec Berg2015-02-202-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix bug with the new CONFIG_SOFTWARE_PANIC where a watchdog panic will write panic data after jump_data pointer is calculated. Since jump data uses the same RAM location as panic data (the end of RAM), we rely on panic data being written BEFORE jump data pointer is calculated so that we don't use the same RAM space. BUG=chrome-os-partner:36871 BRANCH=samus TEST=without this CL, can reproduce problem where jump data is corrupted using samus with following steps: 1) hibernate 1 (this will clear panicinfo) 2) waitms 3000 (this will cause a watchdog reset) 3) let system boot to S0 4) sysjump rw On sysjump to RW, the jump data will be corrupt because while we were in RO panic data was added where there wasn't any before. This means the jump_data pointer in RW will differ from the jump_data pointer that was used in RO and we will fail to find the magic jump data. Most visible consequence of this is that the USB ports will be disabled after these steps because we use jump data to store last state of USB port enables. With this CL, following the steps above, the USB ports are restored to the pre-sysjump state, which is enabled. Change-Id: Ia129419db7400eddb54bcf57b4d4aed63d5c52ef Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251110 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hwtimer/hwtimer32: Remove task_resched_if_needed from watchdog helpAlexandru M Stan2015-02-182-8/+4
| | | | | | | | | | | | | | | | | | | | | Remove task_resched_if_needed, since we don't do any task scheduling modifications. Just return instead. This makes it work on F0 as well, where we don't have task_resched_if_needed BUG=None TEST=With series, see watchdog help work on any veyron BRANCH=veyron Change-Id: I93cce722b6d53008b015c7cdd56b7e77dc07bbff Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/242713 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 8363dfb14cb36fca412132ab14d2c9451de7d94e) Reviewed-on: https://chromium-review.googlesource.com/250671 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* samus: initiailze boostin_voltage in extpower moduleAlec Berg2015-02-181-1/+1
| | | | | | | | | | | | | | | Fix complile bug, initialize local var boostin_voltage. BUG=none BRANCH=samus TEST=make -j buildall Change-Id: Ie178d3bfe164fc900b1c52a05412f75d5a090ddd Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250820 (cherry picked from commit 54f01a6c030ed7608a4bf0d673740a0dca24a52f) Reviewed-on: https://chromium-review.googlesource.com/250821 Reviewed-by: Shawn N <shawnn@chromium.org>
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