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* usb: fix undefined USB endpointsstabilize-6415.Bfoo-testVincent Palatin2014-10-291-4/+8
| | | | | | | | | | | | | | | | | | When calling the ep_undefined function, the linker was not considering it as a Thumb function and not setting the LSB in the address pointer. This was causing an exception at runtime. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=all BUG=none TEST=inspect assembly Change-Id: I8f4d1e351081032e138f593f0b61294031fc09b1 Reviewed-on: https://chromium-review.googlesource.com/226093 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* it8380dev: add pwm control moduleDino Li2014-10-298-22/+294
| | | | | | | | | | | | | | | | Add pwm control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console manual test, pwm channels output correctly. Change-Id: I6eb1a9e4fdcb9279e9d0cbd67f7a92afed21c889 Reviewed-on: https://chromium-review.googlesource.com/223921 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* EC:KBC: Wait until LPC host senses the IRQ and gets the character.Kenji Chen2014-10-281-1/+6
| | | | | | | | | | | | | BRANCH=master BUG=chrome-os-partner:29139 TEST=Buiid an EC FW image and run on Rambi to test if key loss is improved and any side effect somes with this change. Need more test units to confirm this. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I2399e33d2ca3defe8cd9b1f94ab0af1db7f84635 Reviewed-on: https://chromium-review.googlesource.com/225557 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mohammed Habibulla <moch@chromium.org>
* USB-console: Don't wait in interrupt contextsAnton Staaf2014-10-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the USB console code would wait for up to 30 ms for the USB packet buffer to become available for transmission, even if it was called from an interrupt context. This doesn't work because, even if we were OK with waiting this long in interrupt contexts, which we are not, we rightly assert that we are not in an interrupt context in task_wait_event, which usleep calls. This solution is a quick fix to only wait when not called from within an interrupt context. The correct solution is likely to decouple the printf code from directly calling the console driver code, instead we should place a queue between the driver and printf logic. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Enable USB console on discovery board and manually test. Change-Id: I5b6f7bbb77f75132c75935f8fda01e652a236ae0 Reviewed-on: https://chromium-review.googlesource.com/225867 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* twinkie: dual channel CCx sniffingstabilize-6412.BVincent Palatin2014-10-283-69/+111
| | | | | | | | | | | | | | | | | | Update the sniffer code to sample both CC lines at the same time. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28337 TEST=make BOARD=twinkie do an on a sample pattern from the function generator on both channels and verify that the waveform looks good. Change-Id: I30c607591775531e432e757f61209733804b55e5 Reviewed-on: https://chromium-review.googlesource.com/224583 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@google.com> Tested-by: Vincent Palatin <vpalatin@google.com>
* stm32f0: stm32f3: Wake from STOP mode on UART start bitVic Yang2014-10-283-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | By default, UART wakes the chip up on RXNE interrupt. This means when the chip wakes up, RDR is full and only the shift register is empty, and this leaves us only the time of a single character to process the character in RDR. On some system, this is not enough and the first (or even the second) character is overrun, and thus any multi-character keys (e.g. arrow keys) break. To avoid this problem, let's change the wake source to wake on start bit detection. This gives us the time for one more character to wake up and process the console input. BRANCH=None BUG=chrome-os-partner:33219 TEST=Enable low power mode on Ryu P2. In STOP mode, hit up arrow key and see the last command show up. Change-Id: Idce4c0bdfcf3e04ad84152ba525f704a0909f115 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225771 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@google.com>
* samus: use resulting current limit from charge managerAlec Berg2014-10-283-72/+77
| | | | | | | | | | | | | | | | | Send the current limit chosen by charge manager to the EC so that it can set the current limit appropriately. Note, before this change, only the PD negotiated current limit was sent to EC. BUG=none BRANCH=samus TEST=use a non-PD type-C charger and verify current limit gets set appropriately on EC. Change-Id: Ic4bfce052ec8150cad07d35e2cb2fcbfd3d3e6c8 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225667 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_pd_protocol: Don't prematurely set PD charge supplier limitShawn Nematbakhsh2014-10-281-22/+14
| | | | | | | | | | | | | | | Wait until we have a confirmed PD charger before setting the PD charge limit to non-zero. BUG=None TEST=Manual on samus_pd. Insert type C non-PD charger, verify that current limit is correctly set to to 3000 mA. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib4ec663d926e6ed955427e4a77123caac0e20252 Reviewed-on: https://chromium-review.googlesource.com/225691 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* charge_manager: Move supplier list and priority hierarchy to boardShawn Nematbakhsh2014-10-265-25/+41
| | | | | | | | | | | | | | | | Allow the list of charge suppliers and port selection priority to be specified at the board level. BUG=chrome-os-partner:32650 TEST=Manual on samus_pd. Plug + unplug PD and BC1.2 chargers, verify that PD is always preferred and higher power port / supplier is always selected. BRANCH=Samus Change-Id: Ic867a40120c809111bf76bf290ed6f204eab1168 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225292 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: for DP mode, only enter mode if device is DFP_U capableAlec Berg2014-10-254-6/+20
| | | | | | | | | | | | | | | | | | Added return parameter to enter mode functions. For DP mode on samus and fruitpie, only send enter mode if device is a DP sink (DFP_U). BUG=none BRANCH=samus TEST=make buildall. tested a simpler version of this with a third-party DFP_D capable device and verified we don't send enter mode. Change-Id: I5caf008b7b3711232aeb1a1012cde2022584109b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225288 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: make transition out of hard reset shorterAlec Berg2014-10-251-0/+1
| | | | | | | | | | | | | | | | | Shorten the hard reset timeout so that we transition out of hard reset state faster. BUG=none BRANCH=samus TEST=test on third-party product that sends source cap very soon after we send hard reset. without this patch we weren't responding to the first few source caps, with this change we respond right away. Change-Id: I285aaf0296604da22438e31bc962629701694b7b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225247 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add initial support for jerryKatie Roberts-Hoffman2014-10-259-0/+449
| | | | | | | | | | | BUG=chrome-os-partner:33269 TEST=make BOARD=jerry; ./util/flash_ec BOARD=jerry (on a pinky rev2 as a sanity) Change-Id: I2c54e4044a65a0014adb32dd46f74bf5ed11b02d Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225300 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* pd: Add DFP parsing for alternate mode status & attention.Todd Broch2014-10-257-63/+171
| | | | | | | | | | | | | | | | | | | | | Once alternate mode is entered the DFP will make an initial status request to the UFP. Future status changes on the UFP are then sent to the DFP via the attention command. This VDM consists of the VDM header plus another VDO containing mode specific information. CL adds ability of DFP to consume the attention VDMs status message and in the case of DisplayPort SID toggle the necessary HPD gpio accordingly. BRANCH=samus BUG=chrome-os-partner:30645 TEST=manual, for DFP w/ HPD over CC see HPD toggle correctly without manually driving it providing cable connected when AMA is inserted. Change-Id: Ifef60b5d0170cbcc1b518e3b13e84bac99a17e32 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224769 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Wait for UART Tx to complete before entering STOP modeVic Yang2014-10-241-1/+20
| | | | | | | | | | | | | | | | | | | | | | | Before entering STOP mode, we need to ensure UART Tx has completed. Otherwise, we may lose some characters or some bits within a character. For Tx DMA mode, this is already done as we wait until TC (Tx complete) is set before disabling Tx. However, when not using DMA, we enable sleep when TXE is set. At this moment, the last character is still in the shift register and going into sleep causes loss of the whole or part of the last character. To avoid this, let's enable TC interrupt and enable sleep only if we have no more characters to send and TC is set. BRANCH=None BUG=chrome-os-partner:33219 TEST=Enable low power mode on Ryu P2. Type when the EC is in STOP mode and check there is no broken character. Change-Id: Ife42671882b7f1d1d17734d7d20fb4ba7dffb371 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225283 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: Enable watchdog helper for P2 boardsVic Yang2014-10-241-1/+2
| | | | | | | | | | | | | | We have several unused timer. Let's use TIM19 for watchdog helper. BRANCH=None BUG=chrome-os-partner:32660 TEST='waitms 3000' and see debug message. Change-Id: I638a4de7d2729ffb10cb5cf2b3fb9c458dd588a5 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225254 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32: Add watchdog debug message for hwtimer32Vic Yang2014-10-241-0/+77
| | | | | | | | | | | | | | | | This adds the option to use one 16-bit timer for watchdog helper when using 32-bit hwtimer. With this, a debug message is dumped before watchdog fires and we can easily see the task hogging the processor. BRANCH=None BUG=None TEST=On Ryu P2, 'waitms 3000' and see debug message before the EC reboots. Change-Id: I498f63a105a0ba1ab7ec7d274dc8b1f16a44140f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225253 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: update DP pin configuration declarationVincent Palatin2014-10-242-4/+4
| | | | | | | | | | | | | | | | | | | | | | When we are a UFP with a plug, for the supported DisplayPort pinout, we need to state which DFP pin configuration we support. Update the field used for declaring pin configuration in our display dongles. HoHo is a protocol converter : update the pin assignment to C. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:30645 TEST=none Change-Id: Ie5484f228bd39666c6b01055bd11f68eb9acad88 Reviewed-on: https://chromium-review.googlesource.com/225231 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: update DP mode signaling bitsVincent Palatin2014-10-245-14/+15
| | | | | | | | | | | | | | | | | | | | | A USB type-C to DisplayPort dongle can support either DPv1.3 or USB Gen 2 signaling. Our dongles need to advertise that they support DPv1.3 and only this. Our DFP needs to request DPv1.3 signaling. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:30645 TEST=Plug a type-C to DP dongle from another vendor to Samus and see a display output. Change-Id: Ie0ac16b675e86f635220a954a2c03442777cc527 Reviewed-on: https://chromium-review.googlesource.com/225250 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: properly enable UART Rx DMA for P2 boardsVic Yang2014-10-241-0/+1
| | | | | | | | | | | | | | We defined the DMA channel for UART Rx DMA to use, but we didn't actually enable it. BRANCH=None BUG=chrome-os-partner:32660 TEST=Check the console is still responsive Change-Id: I0dcbeeccb3a4213305c84ec5238e6e9dbee09b33 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225280 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Fix UART Rx DMA for USART2 and aboveVic Yang2014-10-241-1/+1
| | | | | | | | | | | | | | This modifies the stray hard-coded DMA channel for UART Rx to the correct config flag. BRANCH=None BUG=chrome-os-partner:32660 TEST=On Ryu, enable UART Rx DMA and check console is still responsive Change-Id: Icec2de6ad4d34c6e0f8df2a1d51d9fefd982c9f4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225239 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* MKBP event signalling implementationVic Yang2014-10-2411-1/+241
| | | | | | | | | | | | | | | | | | | This implements a new API for EC modules to define MKBP event sources and send MKBP event to the AP. Also, a new host command EC_CMD_GET_NEXT_EVENT is added for the AP to query the pending MKBP events. Each event type may have custom event data sent along with the event. BRANCH=None BUG=chrome-os-partner:33194 TEST=Enable MKBP event on Ryu. Set a host event from EC console, run 'ectool nextevent', and see MKBP event 0x01 (HOST_EVENT) and the set host event. Signed-off-by: Vic Yang <victoryang@chromium.org> Change-Id: I28a1b7e826bcc102bbe39016c9bb3e37d125664c Reviewed-on: https://chromium-review.googlesource.com/224905 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EC: Ensure the udelay function waits at least the time indicated.Kenji Chen2014-10-231-1/+1
| | | | | | | | | | | | | | | | | | | | Udelay function might get delay less than the time indicated by the input parameter. udelay(4) sometimes get the tick like, 6->7->7-> 8->8->9->A and then the udelay return. But, the sampling point of 6 could be at the end of 6(close to 7) and the point of A could be right at the beginning of A(close to A). This function could get delay from (us - 1) to (us + 1). This change is to ensure the delay at least over the parameter, us. BRANCH=master BUG=None TEST=Build an EC FW iamge and run on Rambi to ensure at the time duration indicated by the parameter is elaspsed and satisfied. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I797f80c577d7e29e75a304aec1e02d2c750f8a23 Reviewed-on: https://chromium-review.googlesource.com/224660 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mohammed Habibulla <moch@chromium.org>
* ryu: Enable pull-up on console UART Tx/Rx pinsVic Yang2014-10-232-13/+13
| | | | | | | | | | | | | | | | There is no external pull-up on UART signals and this could lead to garbage characters received. Let's enable the internal pull-up to avoid this. BRANCH=None BUG=None TEST=On a Ryu board with which UART Rx gets garbage when servo is not connected, check that we don't get garbage characters anymore. Change-Id: I014b399dfecc1b8495cce7c80c481c3668976084 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225095 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* flash_ec: Add support for kittyKen Chang2014-10-231-2/+3
| | | | | | | | | | | | | | Make board kitty to use flash_stm32. BUG=chrome-os-partner:33035 BRANCH=None TEST=Run util/flash_ec on kitty, verify flashing complete successfully. Change-Id: I302cfc85bfe5fa36fdf1a61d59b4dc21b36cc06a Signed-off-by: Ken Chang <kenc@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/224231 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* plankton: Fix output voltage selectionVic Yang2014-10-231-2/+2
| | | | | | | | | | | | | | We updated the source PDO indices and we also need to update the output voltage selection function. BRANCH=None BUG=chrome-os-partner:33133 TEST=On Plankton, output 5V and measure with INA. Change-Id: I771c04cf929a8e473cf09ae3eb222518f042600a Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225154 Reviewed-by: Pin-chih Lin <johnylin@chromium.org>
* stm32f3: Use the correct RTC ALARM IRQVic Yang2014-10-232-2/+3
| | | | | | | | | | | | | | | | | | | | On STM32F0, a single IRQ is used for all RTC events, including RTC_ALARM and RTC_WAKEUP, and this IRQ is named RTC_WAKEUP. We use RTC_WAKEUP IRQ in our code while we actually meant to capture RTC alarm event. On STM32F3, RTC_WAKEUP and RTC_ALARM are separate IRQs and thus we're having problem. Let's make it explicit which RTC IRQ we want to use and fix our code to use RTC_ALARM. BRANCH=None BUG=chrome-os-partner:33219 TEST=Run 'rtc_alarm' on Ryu and verify the EC gets interrupted after a second. Change-Id: Ib1a14a5da49d709a4d071d44fbfa46544cc5929b Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224998 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: Implement battery cut-offVic Yang2014-10-238-46/+80
| | | | | | | | | | | | | | The battery cut-off is achieved by putting BQ27742 in SHUTDOWN mode. BRANCH=None BUG=None TEST=Unplug AC and do 'cutoff' in EC console. The EC console goes unresponsive. Change-Id: I4a1aa359d79333d47aaf53b685a52960e5dfd652 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225007 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* discovery-stm32f072: Enable SPI over USB tunnelAnton Staaf2014-10-236-19/+81
| | | | | | | | | | | | | | | | | Enable master control of SPI2 over USB for testing flashrom's ability to write to a SPI flash chip attached to the stm32. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j; write image using flashrom Change-Id: I7d320acd28a03e91fcd7f7d697be40f69ea7bbdc Reviewed-on: https://chromium-review.googlesource.com/218741 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* Allow 5V/3A on PlanktonVic Yang2014-10-221-3/+4
| | | | | | | | | | | | | | Plankton is capable of supplying 5V at 3A. Advertise 5V/3A as well. BRANCH=None BUG=chrome-os-partner:33133 TEST=Switch plankton to 5V/12V/20V source and measure power with INA. Change-Id: Iea0545b30127b415a9dc51fceff0b7eff162c1d0 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224986 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Fix clock bug on STM32F0 that HSI48 isn't enabledVic Yang2014-10-221-2/+13
| | | | | | | | | | | | | | | | | | | When changing the clock init code for STM32F3, I accidentally disabled HSI48 for STM32F0, which is causing all problems on all STM32F0 platforms. Re-enable it. BRANCH=Samus BUG=chrome-os-partner:32660 TEST=Boot on Ryu P1 and see console. Change-Id: Ie343cdb039d839e41b36489388fc91970e2bb7d8 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225002 Reviewed-by: Anatol Pomazau <anatol@google.com> Tested-by: Anatol Pomazau <anatol@google.com> Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Calibrated lightbar values for Samus & RyuBill Richardson2014-10-222-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | This updates the lightbar params with the values determined in the optic lab. The full-on primary colors are of uniform intensity at the brightness level used by Link. The Google colors provide the closest match to the official color palette (at full brightness) described at https://sites.google.com/a/google.com/brandsite/the-colours BUG=chrome-os-partner:33017 BRANCH=ToT,samus,ryu TEST=manual The calibration and testing was done in the optic lab. You can see the result just by looking at the lightbar. For best results, set the brightness to the max with ectool lightbar brightness ff Change-Id: I1cb64e3c547844adf733cd46bff1256319b4f612 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224992
* ryu_p2: Fix broken build due to overlapped commitsBill Richardson2014-10-221-11/+15
| | | | | | | | | | | | | | Looks like the commit queue latency caused a breakage. Commit 7eaa290 breaks commit 00551f7. This fixes it. BRANCH=None BUG=chrome-os-partner:32660 TEST=make buildall -j Change-Id: I37ac58ae26a17bc75fae8e6da28bead9a195ba89 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225001 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
* samus_pd: Add BC1.2 charging and charge port + current limit selectionShawn Nematbakhsh2014-10-225-11/+163
| | | | | | | | | | | | | | | | | | | On an interrupt from the Pericom charger detection IC, check the current limit of the attached charger. Charge manager is informed of available charge from BC1.2 source and PD sources and selects the proper port + charge limit in each case. BUG=chrome-os-partner:32003 TEST=Manual on samus. Insert Apple charger, verify charge limit is selected appropriately. Insert PD charger, verify that charge port switches to PD port. Remove + reinsert chargers, verify that port / limit is selected appropriately. BRANCH=samus Change-Id: I47e1e3be1c522f1e11529a0b4ac665e695f33e14 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221791 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32-USB: USB SPI tunnel driverAnton Staaf2014-10-224-0/+301
| | | | | | | | | | | | | | | | | | | | | Simple control of SPI for flashing over USB. This driver is working, and using the discovery board with a W25Q16 flash chip attached flashrom can read, erase, write, and verify the whole chip in 45 seconds. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I224f1f87cd6adc8b64c17de1df98dae0a9cfa6a5 Reviewed-on: https://chromium-review.googlesource.com/218740 Reviewed-by: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* ryu: enable lid switchVic Yang2014-10-226-16/+6
| | | | | | | | | | | | | | This is needed for inductive charging to work. BRANCH=None BUG=chrome-os-partner:31392 TEST=On Ryu, close the lid and check BASE_CHARGE_VDD_EN is toggled. TEST=Open the lid and see the AP booting. Change-Id: Ib153c08a803088b832c7d65261c71605c3378d5f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224804 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus: change fan RPM values, enable fast-startBill Richardson2014-10-223-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the fan speeds according to the manufacturer's specs. The fan vendor recommends that the minimum fan speed be a 20% duty cycle. Since the built-in fan controller has a tach-based feedback loop, I'm using the RPM value instead of the duty cycle (20% is 2286 RPM, according to the vendor). The vendor also wants a 30% duty cycle to start turning, but the built-in fan controller provides support for fast-start too. The controller's minimum fast-start duty cycle is 50%, but it also has a programmable number of revolutions that it will wait before backing off. Holding my ear down close to the fans while they start and stop, it seems that the minimum 2 revolution start period is sufficient and provides the least noise. Of course, since I've never had any problems starting the fans directly at 1000 RPM this noise is a little more noticeable than that. It's quite possible that the built-in controller is smart enough to make 1000 RPM work by bumping the duty cycle up until the fans turn even if the fans don't like it. BUG=chrome-os-partner:32892 BRANCH=ToT,samus TEST=manual Listen closely and run the EC console "faninfo" command to see the fans start and stop as the system boots and idles. Change-Id: I47c9e7cef3f9f4bd815a13032fe10234decd62ed Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224830 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_pd_protocol: Add support for charge_manager and voltage reportingShawn Nematbakhsh2014-10-2212-49/+200
| | | | | | | | | | | | | | | | | | | | | | | | Integrate charge_manager and include several API changes designed for reporting voltage. 1. Make pd_choose_voltage set the chosen voltage for use by caller. 2. Add voltage parameter to pd_set_input_current. 3. Add pd_get_role to grab the sync / source state of a port. 4. Add charge manager PD + type C port initialization to the pd state machine. BUG=chrome-os-partner:32003 TEST=Manual on samus. Insert Apple charger, verify charge limit is selected appropriately. Insert PD charger, verify that charge port switches to PD port. Remove + reinsert chargers, verify that port / limit is selected appropriately. Remove battery, insert power source, verify that our power source port never becomes disabled. BRANCH=samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idf3198c71d2ddf1e401e766fc82a4b7a02aed068 Reviewed-on: https://chromium-review.googlesource.com/223758 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* ryu_p2: Set alternate function for USB D+/D- pinsVic Yang2014-10-222-0/+7
| | | | | | | | | | | | | | | Unlike STM32F0, we need to configure alternate function for USB module on STM32F373. Adds the pin configuration for ryu_p2 and also adds the proper configuration step in USB module. BRANCH=None BUG=chrome-os-partner:32660 TEST=With changes to enable USB on ryu_p2, see the device enumerated Change-Id: I5e2cb7cfc44a1bb88bae69804021c783c8d17968 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224789 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: enable lightbar on P2 boardsVic Yang2014-10-223-2/+7
| | | | | | | | | | | | | | | Ryu uses the same LEDs as Samus, so let's use the same brightness values for them. Also, increase the stack size for console task so that 'lightbar' command doesn't cause stack overflow. BRANCH=None BUG=chrome-os-partner:32203 TEST=See lightbar in action on Ryu. Change-Id: I89b61f6df2751c9dd6b40f9e374f01e1b0dfd504 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224426 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add new build target ryu_p2 for Ryu P2 boardsVic Yang2014-10-2212-8/+804
| | | | | | | | | | | | | | | | | | | | | | | | | The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a new EC chip with bigger flash, so make the corresponding changes: - Pinout changes - HW Timer: TIM5 - USB PD Tx Timer: TIM3_CH4 - USB PD Rx Timer: TIM2_CH4 - Use UART2 for EC console - Disable UART Tx DMA as it conflicts with USB PD Tx DMA - Use 24MHz HSE x2 = 48MHz for SYSCLK BRANCH=None BUG=chrome-os-partner:32660 TEST=Sanity check on a new board: - i2cscan - PD negotiation - UART console - gettime Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221404 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Support UART DMA on UART2Vic Yang2014-10-223-2/+16
| | | | | | | | | | | | | | | This adds the DMA channel definition for UART2 and allows selection of DMA channel for UART. BRANCH=None BUG=chrome-os-partner:32660 TEST=With the CLs to enable the new Ryu boards, check the console is working. Change-Id: I964c284899777dda67c264e622aea6aba752ea76 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224176 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus: fix false shutdown due to low batteryAlec Berg2014-10-221-1/+7
| | | | | | | | | | | | | | | | Fix bug causing unit to falsely shutdown due to low battery. The shutdown warning time was not getting reset, so two false readings of battery SOC or voltage, seperated by more than 30 seconds in time would cause "charge force shutdown due to low battery" BUG=chrome-os-partner:33111, chrome-os-partner:33144 BRANCH=samus TEST=make buildall Change-Id: I6f00187516d23aa78139e5c1565febca34176ecc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224765
* samus: new algorithm for tmp006 object temperatureBill Richardson2014-10-226-266/+457
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original algorithm is given in the TMP006 User's Guide (SBOU107.pdf). The algorithm we previously implemented is that, plus some additional and completely undocumented massaging of the Tdie and Vobj registers. The original meaning of that hack is now lost in the mists of time, thanks to our email retention policy. This CL introduces a new algorithm variant, but at least this time the details are in the bug report. It's essentially the same as the User's Guide algorithm, except that we apply one-stage FIR filters to the Tdie input and the Tobj output. There are five new parameters: d0, d1, ds, e0, e1. Refer to tmp006_read_object_temp_k() in ec/driver/temp_sensor/tmp006.c to see how these new parameters are applied. CAUTION: The tmp006 sensor algorithm is mostly math and magic numbers. The spreadsheet attached to the bug report has six sheets with wildly varying values for those parameters. Since the correct parameter values haven't yet been determined for Samus, all I can be sure of with this CL is that it seems to work and isn't any worse than the old one. Oh, and note that the EC's 't6cal' console command has been disabled until/unless we add support for floating point IO. Use ectool from the host to get and set the params instead. BUG=chrome-os-partner:32260 BRANCH=ToT,Samus TEST=manual After booting, look at the sensor values using ectool: localhost ~ # ectool temps all 0: 312 1: 314 2: 313 Sensor 3 not calibrated 4: 311 Sensor 5 not calibrated 6: 305 Sensor 7 not calibrated 8: 306 Sensor 9 not calibrated 10: 307 Sensor 11 not calibrated 12: 312 Sensor 13 not calibrated localhost ~ # localhost ~ # ectool tempsinfo all 0: 0 PECI 1: 1 ECInternal 2: 1 I2C-Charger-Die 3: 2 I2C-Charger-Object 4: 1 I2C-CPU-Die 5: 2 I2C-CPU-Object 6: 1 I2C-Left C-Die 7: 2 I2C-Left C-Object 8: 1 I2C-Right C-Die 9: 2 I2C-Right C-Object 10: 1 I2C-Right D-Die 11: 2 I2C-Right D-Object 12: 1 I2C-Left D-Die 13: 2 I2C-Left D-Object EC result 2 (ERROR) ... localhost ~ # There are six tmp006 object temps that need calibrating. The index used for the calibration is for the tmp006 objects, not the 3,5,7,.. numbers reported for all temp sensors. See the current values with tmp006cal: localhost ~ # /tmp/ectool tmp006cal 5 algorithm: 1 params: s0 0.000000e+00 a1 1.750000e-03 a2 -1.678000e-05 b0 -2.940000e-05 b1 -5.700000e-07 b2 4.630000e-09 c2 1.340000e+01 d0 2.000000e-01 d1 8.000000e-01 ds 1.480000e-04 e0 1.000000e-01 e1 9.000000e-01 localhost ~ # If the s0 param is zero, this sensor is uncalibrated. The params are entered in the order in which they're displayed You can change any or all of the parameters. Skip the ones you don't want to update by specifying '-' for its position. (Note: throw in an extra '--' first so that ectool doesn't think that negative numbers are command options). For example, to change s0 and b0: localhost ~ # ectool -- tmp006cal 5 1.0 - - -3.0 localhost ~ # localhost ~ # ectool tmp006cal 5 algorithm: 1 params: s0 1.000000e+00 a1 1.750000e-03 a2 -1.678000e-05 b0 -3.000000e+00 b1 -5.700000e-07 b2 4.630000e-09 c2 1.340000e+01 d0 2.000000e-01 d1 8.000000e-01 ds 1.480000e-04 e0 1.000000e-01 e1 9.000000e-01 localhost ~ # Now sensor 13 (tmp006 object index 5) is calibrated: localhost ~ # ectool temps all 0: 310 1: 315 2: 313 Sensor 3 not calibrated 4: 310 Sensor 5 not calibrated 6: 305 Sensor 7 not calibrated 8: 307 Sensor 9 not calibrated 10: 307 Sensor 11 not calibrated 12: 312 13: 313 Change-Id: I61b5da486f5e053a028c533ca9e00b9a82a91615 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224409 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: change hibernate delay to 7 daysAlec Berg2014-10-213-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add macro for default hibernate delay, and set to 7 days on samus. Also, adds CONFIG_ option for hibernating early if low on battery. For samus, setting early hibernate at 1 day when battery < 10%. BUG=chrome-os-partner:33088 BRANCH=samus TEST=make buildall Added ccprintf("Target shutdown: %.6ld\n", target_time); to print out target shutdown time after setting it. Verifed the following on samus 1) If CONFIG_HIBERNATE_DELAY_SEC is left at default 3600 (samus board.h does not overwrite it), then target time is 3600s. 2) If CONFIG_HIBERNATE_DELAY_SEC is defined in samus/board.h, then target time equals that value. 3) If CONFIG_HIBERNATE_DELAY_SEC is defined as 1 week and CONFIG_HIBERNATE_BATT_PCT is defined to 10% and CONFIG_HIBERNATE_BATT_SEC is 1 day, then when battery is between 8-10% target time is 1 day and if battery is at 11%, target time is 1 week. Change-Id: Ief155ad6c327775fa348d3458fc47ee9dd8569c3 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224520 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m0: add more constraints on atomic implementationVincent Palatin2014-10-211-2/+2
| | | | | | | | | | | | | | | | | | | In ARMv6-m instruction set, the load/store address register can only be a "low" register : r0..r7. Update the inline assembly constraints to match the hardware. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd Reviewed-on: https://chromium-review.googlesource.com/224582 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Add DisplayPort status and configure SVDMs.Todd Broch2014-10-216-35/+229
| | | | | | | | | | | | | | | | | | | | | | | Per revisements to the DisplayPort Alternate mode specification there are two additional SVDMs for DPout support: status & configure. This CL adds those SVDMs and calls them (status then config) after finding a device that supports DP Alternate mode. Future CLs will use these SVDMs to complete providing HPD over CC support. BRANCH=none BUG=chrome-os-partner:31192,chrome-os-partner:31193 TEST=manual, plug hoho/dingdong into samus and see: 1. Additional DP status [16] & DP configure [17] 2. Drives DPout properly Change-Id: I52b373085ddc330e4afb1d1883d2621bc2e4ee95 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/223260 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Correct use of console printing in USB PD policy files.Todd Broch2014-10-2110-60/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | All non-interactive console prints should use their tasks channel parameter to make it easy for developers to inhibit console output. This CL corrects printf's in the various usb_pd_policy files that belong to the USB PD task to use cprintf(CC_USBPD, ...) instead of the macro reserved for interactive console commands ccprintf. BRANCH=none BUG=none TEST=manual, set 'chan 1' and see none of the previous chatter relating to USB PD. set 'chan 0x08000000' and see it return. Output from DFP side for SVDM discovery now looks: SVDM/4 [1] ff008041 340018d1 00000000 11000008 [1119.966911 DONE] SVDM/2 [2] ff008042 ff010000 [1119.970135 DONE] SVDM/2 [3] ff018043 00100081 [1119.973437 DONE] SVDM/1 [4] ff018184 Change-Id: I47e5f4ec2d4a6a25f171177ead5ebc99409f80b6 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224191 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: Pinky: Fix power leak caused by SPI at startupAlexandru M Stan2014-10-211-2/+0
| | | | | | | | | | | | | | | Seems like we were setting outputs too early during boot, sometimes causing a power leak. SPI should only turn on power levels more active than S3, not on the S5->S3 transition. BUG=chrome-os-partner:32824 BRANCH=None TEST=Pinky powers on, Scope VCC33_PMUIO and VCC33_IO, note that they're smooth Change-Id: I05c3622d124c2539222b883b895bc9092c5f0b12 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224508 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Pinky: Reoganize power on sequencingAlexandru M Stan2014-10-211-28/+18
| | | | | | | | | | | | | | | | | | This is the first step to fix a leak when powering up the system. Some stuff should wait till after the rails are up. The SPI timeout was removed because there's a simpler way to determine this: SPI is only ready when the AP goes from S3->S0 BUG=chrome-os-partner:32824 BRANCH=None TEST=Pinky powers on Change-Id: Ia4281f54f7735d4efe2bc3e8ba1e462fccc51fd0 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222632 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: do not respond to unknown SVDMsAlec Berg2014-10-211-0/+4
| | | | | | | | | | | | | bug fix: if we see an unknown SVDM, do not respond to it. BUG=none BRANCH=samus TEST=test with third party that sends unknown SVDM Change-Id: I3ef6c38be029d57bf3784ba832b7ae137f379049 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224179 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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