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* CHERRY-PICK: [Swanky] lid_switch: Support forced lid openstabilize-6310.69.Brelease-R39-6310.BHenry Hsu2014-12-023-1/+56
| | | | | | | | | | | | | | | | | | | | | | | Factory test process need lid switch no function or keep lid opened BUG=chrome-os-partner:33850 BRANCH=swanky TEST=Run command "ectool forcelidopen 1" and "reboot". Then lid close quickly, the system boot as lid opened. Deault value or run command "ectool forcelidopen 0" make the device normal. Change-Id: I7fc884b10a064091f8c55656795af4247934e7f5 Original-Change-Id: I94527b7ef7f9efe779c6b86f3eab651f99af6000 Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/230180 Reviewed-by: Mohammed Habibulla <moch@chromium.org> Reviewed-by: Bowgo Tsai <bowgotsai@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232152 Commit-Queue: Anson Tseng <anson.tseng@intel.com> Tested-by: Anson Tseng <anson.tseng@intel.com>
* temp_metrics: add "--" when invoking ectool tmp006calSameer Nanda2014-10-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | ectool has switched over to using getopt for command line options parsing. This breaks temp_metrics' invocation of "ectool tmp006cal" command since some of the coefficients are negative and therefore start with "-". getopt treats that as another command line option causing ectool to barf. BUG=chromium:422160 TEST=On a Pixel issue "sudo start temp_metrics" and check /var/log/messages to ensure that no new messages such as "init: temp_metrics main process ended, respawning" show up. BRANCH=none Original-Change-Id: I42232b3027ec6339814d226f1d8ab493e3420eea Signed-off-by: Sameer Nanda <snanda@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222845 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 63c41f239223cb343978635c7409ee341eeb08d8) Change-Id: Idd8e1653a5c77b0e03adb5306b81bcb3b8b97472 Reviewed-on: https://chromium-review.googlesource.com/223176 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Sameer Nanda <snanda@chromium.org> Tested-by: Sameer Nanda <snanda@chromium.org>
* Fix floating point usage in lightbar moduleVic Yang2014-09-271-4/+4
| | | | | | | | | | | | | | | | | This patch fixes stary floating point usage in lightbar module. They should be scaled by FP_SCALE and of type 'int'. BUG=None TEST=Compile and make sure the compiler is not using floating point related instructions. BRANCH=None Change-Id: I8d598af1014160b83bc44ef3e88e2cc4bf304e5e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/220121 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Eric Caruso <ejcaruso@chromium.org>
* stm32f0/i2c: Return error if we see a NACKAlexandru M Stan2014-09-272-8/+9
| | | | | | | | | | | | | | | | | | | | | | | i2cdetect -q was broken on the AP. The way it works is by sending a 0 length write request and checking for NACK. The stm32f0 driver had to be fixed to actually return non-success if there was a NACK. i2cdetect -r worked so far because it relied on a 1-length read and we indirectly detected NACKs by the lack of data. The error catching also had to be moved(in both drivers) before the success returns, because it is possible to transmit something successfully(buffer got emptied) without getting an ACK. We want this to be an error. BUG=None BRANCH=None TEST=veyron: i2cdetect -y -r 20 0x09 0x0b should display -- on the 0x0a spot since there's no device there. i2cdetect -y -{r,q} 20 should display the same thing. Change-Id: Id6cadb798e4d972dea089f15742e5b30888a038b Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/220185 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* twinkie: add USB PD snifferVincent Palatin2014-09-276-1/+286
| | | | | | | | | | | | | | | | | | Record the edges on the CC lines to sniff the USB PD traffic. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28337 TEST=make BOARD=twinkie Change-Id: I05c3135e47d0dc848875cbc99e4b57aff52ccbf6 Reviewed-on: https://chromium-review.googlesource.com/202206 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Add demo_tap() function for lightbar demo modeBill Richardson2014-09-263-3/+14
| | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:29041 BRANCH=ToT TEST=manual From the host run ectool lightbar demo on Then press the 'T' key. The lightbar should change to indicate the charge state. Fiddle with the arrows to change the pretend battery level and AC presence. Change-Id: I398a829e2e5de5e1a186500aa2ed72c61e71deaa Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/220024 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lightbar: test programs for seq type PROGRAMEric Caruso2014-09-268-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | These programs test various bytecode interpreter functions. rainbow-shift, red-green-blink and green-pulse produce visual effects, whereas the other three programs test error cases. bad-jump makes sure the interpreter stops if the PC goes out of bounds. bad-opcode makes sure the interpreter stops if it does not understand the instructions it is decoding. infinite-jump makes sure that sticking a tight loop in the EC (i.e., one not perforated with any DELAYs, RAMP_ONCEs, or CYCLE*s) does not cause it to hang or crash. bad-decode-8 and -32 test that malformed instructions are detected while decoding the instruction's immediate data. BUG=None BRANCH=ToT TEST=In simulator/scp files to device and test Change-Id: I6c189997a13e7c6196daa28eb74d5506b5288f2b Signed-off-by: Eric Caruso <ejcaruso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219565 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* zinger: remove reserved 4k for pstateAlec Berg2014-09-251-0/+5
| | | | | | | | | | | | | | Remove 4kB reserved flash for pstate since we don't use persistent state flash on zinger and flash space is limited. BUG=none BRANCH=none TEST=make -j buildall. load and run zinger. Change-Id: Id0020932ed47873d22e81516abf97b4279a7deae Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219932 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: enable flash prefetch bufferAlec Berg2014-09-253-4/+11
| | | | | | | | | | | | | | | | Enable flash prefetch buffer for stm32f0 chips to make for faster CPU execution. BUG=none BRANCH=none TEST=load onto samus_pd and zinger. let run for a while. connect/disconnect AC a few times. boot samus. Change-Id: I88c0ae67a3205987344552f5b44952f9890c8177 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219921 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org>
* veyron: enable low power idleAlexandru Stan2014-09-251-9/+11
| | | | | | | | | | | | | | | | | | Enable low power idle for veyron (with uart wakeup as well). Low power idle is only active in S5/S3. Also sorted options from board.h BUG=chrome-os-partner:31226 BRANCH=none TEST=load onto pinky-proto1, use idlestats command to verify that we are going into deep sleep (STOP mode). Run 30 min. and verify no watchdog reboots or anything out of ordinary. Change-Id: Id14b04f33ea46b1e6cca1c8e812b5875e9ee0446 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219044 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Allow to disable default DMA interrupt handlersVincent Palatin2014-09-252-0/+5
| | | | | | | | | | | | | | | | | The default DMA interrupt handlers are somewhat slow and not really flexible, allow to override them in board if needed. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I909bfab265ccaa4f3b61d0a2a69bf7dfc0414be2 Reviewed-on: https://chromium-review.googlesource.com/215671 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: change pd_soft_reset() to use PD task to send commandAlec Berg2014-09-252-16/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix potential bug in pd_soft_reset() function. That function is part of a global API and as such can be called by other tasks. For example, a sysjump which takes place as part of host command task. So, this function should not directly initiate PD communication because if it is interrupted by the PD task, then there will be unpredictable behavior since the send_validate_message() is not designed to be re-entrant for a given port. This changes pd_soft_reset() to simply change the PD state to SOFT_RESET and then wake up the task to actually send the command. BUG=none BRANCH=none TEST=you can test this with a type-C to A receptacle dongle. The dongle has a pulldown on the CC line, but no device to respond to PD comms. When you plug in C to A cable, samus should send source cap repeatedly for 5 seconds. During that time, if you do a sysjump from RO to RW, it will call pd_soft_reset(), which will send the soft reset command. But, since there is no device it will timeout and retry 3 times. During that period, the PD task will wake up and try to do it's own thing, causing craziness and eventually a hang and watchdog reset. With this fix, I can plug in a C to A adapter, and sysjump to RW cleanly. Change-Id: Icab936ab8ab930e8e37b5a23825f7f054a50c177 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219893 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* stm32f0: fix rare ADC initialization bugAlec Berg2014-09-253-9/+21
| | | | | | | | | | | | | | | | | | | | Fix potential bug in ADC initialization. After setting ADEN bit to enable ADC module, we must wait for ADRDY (ADC ready) bit before continuing. This bug only affects a few chips, and only some of the time. BUG=chrome-os-partner:31978 BRANCH=none TEST=Used a samus board where the PD MCU fails ADC initialization quite often. Without this fix, if you reboot the PD MCU, it will sometimes come up with all ADC's reading 0 and ADEN reading 0. With this fix, it always boots with the ADC's working Change-Id: Iba1d0e56006ba1ad6d9f0eee964a70ef2d0f8dcf Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219522 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* lightbar: add seq type PROGRAM for user-programmable sequencesEric Caruso2014-09-256-2/+469
| | | | | | | | | | | | | | | | | | | | | | | | This diff allows the user to send small programs to the EC and gain control of the lightbar. Right now, this is only exposed through ectool, and sysfs support will come later. To send a program to the EC, use $ ectool lightbar program /path/to/program.bin and then start running the program with $ ectool lightbar seq program BUG=None BRANCH=ToT TEST=Using the above steps with hand-assembled programs. Checked that infinite bytecode loops do not hang the EC. Checked that bad opcodes exit with an error. Stress tested pushing programs and changing sequences. Signed-off-by: Eric Caruso <ejcaruso@chromium.org> Change-Id: I635fb041a5dc5c403f7c26fb9a41b5563be9b6b7 Reviewed-on: https://chromium-review.googlesource.com/219558 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lightbar: show google colors in S0 (red for low battery)Bill Richardson2014-09-251-0/+54
| | | | | | | | | | | | | This removes the pulsing blue colors in S0. BUG=chrome-os-partner:31546 BRANCH=ToT TEST=manual Change-Id: Ib756b93bb51cb7b618958e5b1d270ba9cd1eef22 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219417 Reviewed-by: Vic Yang <victoryang@chromium.org>
* [common]: Remove accelerator calibration code.Gwendal Grignou2014-09-2510-591/+3
| | | | | | | | | | | | | | | | This code is used to find the orientation of the sensor. Given sensor are aligned with the edges of the device, it is not too dificult to find manually. BRANCH=ToT BUG=None TEST=Check ACCEL_CALIBRATE is not used anymore. Check 'make buildall -j' works. Change-Id: I81ffcb4f6b01c530ef16baf13113a5942f615092 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219527 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32/spi: Reset peripheral after every packetAlexandru M Stan2014-09-251-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | RX DMA seems to get misaligned sometimes yielding to extra bytes before the first byte on the wire. in_msg=[00 00 00 03 f4 09 00 00 ...] ^ real first byte To fix this we want to reset and reinit the SPI peripheral after every packet, in the same place where setup_for_transaction() is called. This bug applies to the STM32F0 line but resetting the peripheral on other STM32 ECs should not break anything. BUG=chrome-os-partner:31390 TEST=On STM32F0: ap# cd /sys/class/power_supply/sbs-20-000b/; while true; do grep "" * >/dev/null 2>&1; done You should not see "SPI rx bad data" with in_msg packets that have extra bytes in the beggining. Wait though, it might take up to a few minutes for stuff to break. BRANCH=None Change-Id: If9ab93c5c9040a2c7bda33d7cc990603f1121f3f Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/217527 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f0: samus_pd: add hibernate and enable wake pins for samusAlec Berg2014-09-245-1/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hibernate functionality for stm32f0, and enable wake pins for samus PD MCU. Samus wake pins are VBUS present on either port. BUG=chrome-os-partner:31226 BRANCH=none TEST=load onto samus PD. test hibernate console command: > hibernate 0 500000 Hibernating for 0.500000 s (5 seconds later) --- UART initialized after reboot --- [Reset cause: hibernate] ... > hibernate Hibernating until wake pin asserted. (plug in AC) --- UART initialized after reboot --- [Reset cause: hibernate] Change-Id: Ib86f2677721df29e7bf6975e239de79c25a38795 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219105 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* discovery-stm32f072: Add echo taskAnton Staaf2014-09-245-3/+211
| | | | | | | | | | | | | | | | | | | | This task echo's all bytes from any console stream back to all other console streams. It is a test case for the new multi-USART and USB stream drivers. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manual testing of cutting and pasting large blocks of text into the echo'ed usarts, and verifying no dropped characters. Change-Id: I408c77e40931d3a473657326f9772e71a7ae8a60 Reviewed-on: https://chromium-review.googlesource.com/213178 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* stm32: Fix PWM driverShawn Nematbakhsh2014-09-243-3/+22
| | | | | | | | | | | | | | | | | | | STM32F and STM32F0 series require an MOE bit to be set to enable PWM output. In addition, require that the PWM alternate function # be manually specified for STM32F0 -- there seems to be no logical mapping here, unlike other STM32* parts. BUG=chrome-os-partner:32089 TEST=Manual on samus-pd. Set ILIM PWM output to 50% duty cycle with pwm driver functions, probe and verify avg. 1.62V on pin. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Icb13a153fa3eee52be938d76a6c980fe6fd2bb3e Reviewed-on: https://chromium-review.googlesource.com/219570 Reviewed-by: Alexandru Stan <amstan@chromium.org> Tested-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* tegra: Remove 'power' console commandVic Yang2014-09-241-59/+0
| | | | | | | | | | | | | | | | | The 'power' console command is entirely redundant: - 'power on' can be replaced by 'powerbtn'. - 'power off' can be replaced by 'apshutdown'. - 'power' can be replaced by 'powerinfo'. Let's remove this command to save flash space. BUG=chrome-os-partner:32203 TEST=Build Ryu. BRANCH=None Change-Id: Ib33804c1748dd44bbb89277fed938b50f0f946c4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219491 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32/gpio: Supress overriding interrupt warning in some casesAlexandru M Stan2014-09-241-1/+1
| | | | | | | | | | | | | | | | | | | The warning should only warn if there's an actual danger(in order to give a clue to developers that something might be amiss). Messages like "Overriding SPI1_NSS with SPI1_NSS on EXTI4" are just spammy. This patch makes it so it only warns if the interrupt is different. BUG=chrome-os-partner:31390 TEST=spam gpio_enable_interrupt(GPIO_SPI1_NSS); in a bunch of places (like spi_event), it should not complain about the interrupt being set to the same thing before. Whereas before it was so spammy it did not even have time to reply to SPI. BRANCH=None Change-Id: I786a821eb8167e3568d0be371c4de26bb124431a Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218563 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add options to disable rarely used console commandsVic Yang2014-09-245-0/+11
| | | | | | | | | | | | | | | | | | | 'powerindebug' is only used when there is a problem with power sequencing. 'taskready' is rarely used and the same info can be retrieved by 'taskinfo'. Put both behind config flags and disable 'taskready' by default. Also disable 'powerindebug' for Ryu. BUG=chrome-os-partner:32203 TEST=Build Ryu and check flash space used. BRANCH=None Change-Id: I753a1f5411d6e840a80aba03afc94f9640d381a8 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219490 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32/spi: Print packet on bad datastabilize-6297.BAlexandru M Stan2014-09-231-0/+7
| | | | | | | | | | | | | | | | | Just after a bad data error the EC will print the packet(pretty much the whole thing): in_msg=[02 00 0f 03 f4 09 00 00 ] I found it very helpful when debugging SPI TX/RX to know what the EC sees. BUG=chrome-os-partner:31390 TEST=Load spidev and send the EC bytes manually(malformed packets) BRANCH=None Change-Id: I037ab909076dc454379040e2e927dc6a0b5c5ea9 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218442 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: accel: fix calibration bug, only using base sensor dataAlec Berg2014-09-231-1/+1
| | | | | | | | | | | | | | | | Fix accel calibration bug from refactoring. The motion_get_accel_lid() function used by calibrate routine to get lid accel data was actually returning base accel data. BUG=none BRANCH=none TEST=load onto samus, run accel calibration routine. Change-Id: I095381390267aa6ea3b3a74311c27f30d70e9c81 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219520 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Remove floating point usage in lightbar codeVic Yang2014-09-231-84/+96
| | | | | | | | | | | | | | | Not every chip that we use has FPU. To make it easier to enable lightbar on chips other than LM4, let's remove floating point usage in lightbar code. Instead, scale those numbers by a factor of 10000. BUG=chrome-os-partner:32203 TEST=Run on Samus. Visually check lightbar. BRANCH=None Change-Id: I88b12bb66b5c586f2e14135069bd97d6b56832a1 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219246 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* plankton: Set polarity when connectedVic Yang2014-09-231-0/+1
| | | | | | | | | | | | | | | When a cable is connected, set USBC_POLARITY to the right polarity. This is done in a different way than how we do this on other boards because we only want to control polarity automatically on cable connection. BUG=chrome-os-partner:32163 TEST=Flip the cable, check USBC_POLARITY changes. BRANCH=None Change-Id: I903123b8fd729e8c913014b83812d20328600f8e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219291 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* plankton: Do not send soft reset unless already sourcing powerVic Yang2014-09-231-10/+16
| | | | | | | | | | | | | | | | | | | | When 5v/12v/20v buttons are pressed, plankton first switchs to source role, set the requested source cap, and then perform a soft reset. However, if plankton was sink and just switched to source, the port partner might not have switched to sink and this leaves the CC line in a state where communication is not possible. The subsequent soft reset then fails. If we are not already sourcing power, we actually don't need a soft reset after changing source cap. BUG=chrome-os-partner:32163 TEST=Switch from sink to source. Doesn't see "soft reset" in console. TEST=Switch from 5V to 12V. See "soft reset". BRANCH=None Change-Id: Ia4b834c2e7dc1324b9143c46a72938845499e2fb Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219004 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: use GET_POLARITY for SNK_DISCONNECTED state as well.Todd Broch2014-09-231-1/+2
| | | | | | | | | | | BRANCH=none BUG=none TEST=compiles Change-Id: Ic4c0631737885ca66ac4d8b826d5447363c820bb Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218384 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* hoho: Enable USB PD support.Todd Broch2014-09-235-2/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CL to allow hoho to receive initial USB PD communication (source capabilities payload). BRANCH=none BUG=chrome-os-partner:31192 TEST=manual, When attaching hoho to fruitpie and configured via 'pd dualrole source' I see on hoho side: --- UART initialized after reboot --- [Reset cause: reset-pin power-on] [Image: RO, hoho_v1.1.2213-2bf6a29-dirty 2014-09-15 12:10:22 tbroch@brisket.mtv.corp.google.com] [0.000466 Inits done] C0 st2 Console is enabled; type HELP for help. > [0.250678 USB PD initialized] C0 st3 [0.264629 PD TMOUT RX 1/1] RX ERR (-1) Request [1] 5V 3000mA C0 st4 C0 st5 C0 st6 > pd 0 state Port C0, Enabled - Role: SNK Polarity: CC2 State: SNK_READY Change-Id: Ic5871946425f0ff12d717fbbbbb9e81c6b67cc6f Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/217977 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Plankton: reset USB hub on PORVic Yang2014-09-231-1/+20
| | | | | | | | | | | | | | | On power-on reset, the USB hub might get stuck in a locked state due to a race condition in hardware. Let's reset the hub after 0.5 seconds to make sure this doesn't happen. BUG=chrome-os-partner:32163 TEST=Power on the board. Measure the reset signal. BRANCH=None Change-Id: I0f89883c5db7c5376f3612da1615ba4f86b5efa6 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219199 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Plankton: Add console command to reset USB hubVic Yang2014-09-235-0/+121
| | | | | | | | | | | | | This command resets the USB hub through the IO expander. BUG=None TEST=Reset the hub on Plankton. BRANCH=None Change-Id: Ia77a1e326adc6aba65438534158a4c461479727a Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218758 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* samus: Do not assert RTCRST on every recovery mode bootDuncan Laurie2014-09-231-4/+0
| | | | | | | | | | | | | This causes the loss of CMOS stored flags like dev_boot_usb. BUG=chrome-os-partner:30832 BRANCH=none TEST=pass suite:faft_bios on samus Change-Id: I5e168eaf496ddebb5b409a42b6d8b1a05693db40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219215 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32-USB: Initial USB bulk endpoint stream driverAnton Staaf2014-09-234-0/+422
| | | | | | | | | | | | | | | | | This stream driver works like the USART stream driver but connects to two bulk USB endpoints. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I9cbd2e54a811d3e32c68a820f7ab5de693c29569 Reviewed-on: https://chromium-review.googlesource.com/216002 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* ectool: Do not increase buffer size after probe max size from ecPuthikorn Voravootivat2014-09-231-6/+16
| | | | | | | | | | | | | | | | During the communication init, ectool will probe max request and response packet size from ec and set packet size accordind to that. However, with older kernel's ec driver, the buffer allocated by kernel is not large enough and this will cause kernel bug. BUG=chrome-os-partner:31989 TEST=ectool version runs fine on blaze BRANCH=ToT Change-Id: I499a5305c8fa8b0fd6f3be8554c9cf066b7e0828 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219114 Reviewed-by: Mohammed Habibulla <moch@chromium.org>
* samus_pd: enable low power idleAlec Berg2014-09-236-25/+74
| | | | | | | | | | | | | | | | | | | | | Enable low power idle for samus_pd. Low power idle is only entered when no USB PD device is connected. BUG=chrome-os-partner:31226 BRANCH=none TEST=load onto samus_pd, use idlestats command to verify that we are going into deep sleep (STOP mode). Run 30 min. and verify no watchdog reboots or anything out of ordinary. Also, verify that host commands from EC work when going into deep sleep by sending host commands on the EC console with pdcmd 0 0. Change-Id: I3e2e04e6c4c0a84e291286dbed90945847e0dfdd Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218957 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32-USART: Add generic stream based usart driverAnton Staaf2014-09-2312-0/+847
| | | | | | | | | | | | | | | | | | | This driver can be used to access multiple usarts using an abstract stream interface. The stream interface can also be used in drivers for the host interface and USB console interface, providing a consistent API across all character stream style IO. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Icf567f0b0fa4eb0e9ad4cdb0be8edc31c937a7de Reviewed-on: https://chromium-review.googlesource.com/209671 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* samus: enabled fast charging for EVT ATL cellsAlec Berg2014-09-231-19/+51
| | | | | | | | | | | | | | | | | Enable fast charging with profile designed for ATL cells that will be used in EVT. BUG=chrome-os-partner:23776 BRANCH=none TEST=Took detailed charging/discharging data and verified that the actual profile matches the desired profile and that the fast charging profile is actually faster than the standard. See bug report for more info and data collected. Change-Id: Ic11ab89e48afb73987b8013abf8b0564e1138156 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/212980 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32f0: low power idle taskAlec Berg2014-09-222-22/+170
| | | | | | | | | | | | | | | | | | | Add low power idle task to stm32f0. This can be enabled by defining CONFIG_LOW_POWER_IDLE. This low power idle uses STOP mode to conserve power. BUG=chrome-os-partner:31226, chrome-os-partner:28335 BRANCH=none TEST=add #define CONFIG_LOW_POWER_IDLE to samus and use idlestats console command to verify using deep sleep. also #define CONFIG_FORCE_CONSOLE_RESUME and make sure serial console works without problems when going into deep sleep. Change-Id: I76b0ceb8587a139faa74353d3d8efb4f689fc669 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218956 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: fix UART clock source for console on UART2Alec Berg2014-09-221-2/+2
| | | | | | | | | | | | | | | | Bug fix. Recently changed to use HSI 8MHz clock as clock source for console UART, but the clock register was set incorrectly for the case that the console UART is UART2. BUG=chrome-os-partner:32170 BRANCH=none TEST=Tested on fruitpie which is using UART2 for console. Verified that console works. Change-Id: Ied629eb3828e5fab911acb6a8e5f4087563ddb32 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219312 Reviewed-by: Vic Yang <victoryang@chromium.org>
* pd: make flash_pd.py forward compatible.Todd Broch2014-09-221-11/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | Older versions of flash VDM supported a 'rw_hash' command that has since been deprecated in favor of 'info' command. This CL makes flash_pd.py try either in order to determine whether the pd flash erase was successful. BRANCH=none BUG=chrome-os-partner:28330 TEST=manual, succesfully run on zinger with only 'info' command support util/flash_pd.py -m 1 zinger_ec.RW.flat 2014-09-18 14:35:39,305 - root - INFO - Current PD FW version is zinger_v1.1.2192-5cd 2014-09-18 14:35:39,305 - root - INFO - Flashing 11532 bytes 2014-09-18 14:35:45,779 - root - INFO - Successfully erased flash. 2014-09-18 14:35:45,890 - root - INFO - Chunk 0 of 481 done. ... 2014-09-18 14:36:39,133 - root - INFO - Chunk 480 of 481 done. 2014-09-18 14:36:46,072 - root - INFO - Flashing DONE. 2014-09-18 14:36:46,072 - root - INFO - SHA-1: f6b296ba d474edc4 2e917ad0 33cd16cb 0f51a3fc 2014-09-18 14:36:46,090 - root - INFO - New PD FW version is zinger_v1.1.2226-bea Change-Id: I32f8b06fa546aa99c8290b6b73faa9b8df05e4fb Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218878 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32f0: Change uart clock to HSIAlexandru M Stan2014-09-191-1/+22
| | | | | | | | | | | | | | | | | | | | | When waking up from sleep, the real CPU_CLOCK is a lie for a moment(since we cannot switch to the real clock during the first character) so the first character will be corrupted. The UART clock is now sourced from HSI(8MHz) which is available from the first moment after the cpu wakes up from sleep. BUG=None TEST=Console should work. When waking up(not implemented yet) it will also not lose a character BRANCH=None Change-Id: Ia12ed0634290f3edadfe3471b311759c3176260e Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218728 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* stm32f0: add RTC alarm functionalityAlec Berg2014-09-192-0/+220
| | | | | | | | | | | | | | | | Implement RTC alarm, with resolution 50us, for stm32f0. This is useful for using low power modes and waking up after set period of time. BUG=chrome-os-partner:31226, chrome-os-partner:28335 BRANCH=none TEST=tested on samus_pd with CONFIG_CMD_RTC_ALARM defined and used rtc_alarm console command to test various timeout periods. Change-Id: Ibabd8662cfbea654c7de387669f7be83af4fd79d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218322 Reviewed-by: Todd Broch <tbroch@chromium.org>
* Remove PD power check in flash erase routineVic Yang2014-09-191-17/+0
| | | | | | | | | | | | | | Now that ping is disabled by default, we can remove the PD power check in flash erase routine. BUG=chrome-os-partner:31362 TEST=Build Ryu BRANCH=None Change-Id: Id021529aa2323050ff760b3ce22312c96f23609e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218080 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Fixup for coreboot & portability.Todd Broch2014-09-191-5/+5
| | | | | | | | | | | | | | | Removed include for sha1 and just hardcoded the #define for now. BRANCH=none BUG=chrome-os-partner:32108 TEST=manual, can compile EC & BIOS firmware for samus Change-Id: Iab03315041ec9ac12e85ca93f97b80b850c61377 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218809 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Stream: Add In and Out stream interfaces and configAnton Staaf2014-09-186-0/+187
| | | | | | | | | | | | | | | | | | These interfaces will be used by USART, USB and I2C stream drivers to provide a uniform interface for console mux'ing code. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: If8938512c29708f7b8c28f6ca1c707aa6b5c1708 Reviewed-on: https://chromium-review.googlesource.com/216001 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* Queue: Add functionality needed by new USART stream driverAnton Staaf2014-09-186-160/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously there was no way to remove multiple units at a time from the queue, and the queue was wasting an entry to disambiguate full from empty. There was also no way to get the free entry count from the queue, only the ability to query if it was above a required amount. The queue was also storing its constant compile time configuration as well as its dynamic state in the same structure. This wasted RAM on configuration information that doesn't change. This refactor fixes these issues, making the queue suitable for use in the new USART stream driver. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I284cee52d8189928dbc4c499f87ab34e14019e5a Reviewed-on: https://chromium-review.googlesource.com/210533 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* samus: exchange status with PD MCU on bootAlec Berg2014-09-172-4/+11
| | | | | | | | | | | | | | | | | | | | | On boot, the EC should send host command to exchange status with PD MCU. This allows EC to get the correct input current limit when EC reboots and PD does not. Also had to move some of the charger state machine initialization to run with HOOK_INIT so that it runs before the tasks run. BUG=none BRANCH=none TEST=tested on EVT samus. Without this change, if you reboot EC, and run charger command, the charger input current limit is 512mA. with this change, when the EC reboots, it sends host command to PD MCU to get current limit and sets it appropriately. Change-Id: I5426f0fc3a62b6cd7a73f55cb11b895902a54903 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/216879 Reviewed-by: Todd Broch <tbroch@chromium.org>
* fruitpie: Fix default OSPEEDR reg settings for PB15.Todd Broch2014-09-171-1/+1
| | | | | | | | | | | | | | | | OSPEEDR cfg for PB15 was inadvertently set to '01' for PB15 (should be '00'). Not sure it causes any harm but shouldn't be set according to comment which is speeding up output pins on SPI interface PB12-14 only. BRANCH=none BUG=none TEST=manual, compiles, boots, talks PD w/ samus_pd. Change-Id: Ibc2ec1c427a2c3c92ffdf424b668752b1c0b0032 Signed-off-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/217963 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Add support for BQ27742 battery gauge chipVic Yang2014-09-171-5/+24
| | | | | | | | | | | | | | | | This reuses most of the existing BQ27541 driver, but changed necessary parts to make it work. BUG=none TEST=Boot on Ryu. See battery charging. BRANCH=factory-ryu-6212.B Change-Id: I3a7325a821c81f84396bcc328036b6a5e7749a2e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/217198 Reviewed-by: Alec Berg <alecaberg@chromium.org> (cherry picked from commit f44593e20bf61a2243d7baaae901c912ca798d75) Reviewed-on: https://chromium-review.googlesource.com/218413
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