summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
...
* cleanup: comments in i2c modulesRandall Spangler2013-10-255-21/+27
| | | | | | | | | | | | | No code changes; just update comments with bug links BUG=none BRANCH=none TEST=build all platforms Change-Id: I8b845f9c43315b7db5a746a16c6618c3ee96979d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174614 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: charge state headerRandall Spangler2013-10-251-9/+1
| | | | | | | | | | | | | Remove old TODO and function which no longer exists. BUG=none BRANCH=none TEST=compile all platforms Change-Id: I81c5ddb3d0e156d455be1af82f12d8d4f30e1bc8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174393 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: rename I2C_PORT_HOST to I2C_PORT_MASTERRandall Spangler2013-10-2524-104/+60
| | | | | | | | | | | | | | | | | Previously, it was really confusing whether I2C_PORT_HOST meant the port where the EC was the master, or the port used to talk to the AP. No functional changes, just a global find/replace and some tidying of unused comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: Ia591ba4577d3399729556e0234ba0db3a0e3c5ea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174546 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pit: Fix battery cutoff command to use deferred function callRandall Spangler2013-10-251-16/+14
| | | | | | | | | | | | | | | | Rather than hackily sending a host response before sending the battery cutoff command, just put the cutoff command in a deferred function call and respond normally to the host command. BUG=chrome-os-partner:23568 BRANCH=none TEST=On battery power, 'ectool batterycutoff' prints success, then the system loses power due to battery cutoff. Change-Id: Ic42d08ef94a10f89d093290cda63da01fca985a5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174573 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: Leave WiFi power on in S3Paul Stewart2013-10-241-2/+6
| | | | | | | | | | | | | | | | | | This improves WiFi stability after resume since powering down may erase or otherwise stymy the firmware. Signed-off-by: Paul Stewart <pstew@chromium.org> BUG=chrome-os-partner:22175 BRANCH=none TEST=Suspend and resume samus, make sure WiFi is still operable Change-Id: I91914482c2040abe0feecd94891fca01a176f667 Reviewed-on: https://chromium-review.googlesource.com/174258 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Paul Stewart <pstew@chromium.org> Commit-Queue: Paul Stewart <pstew@chromium.org>
* cleanup: remove obsolete declaration from headerBill Richardson2013-10-231-5/+0
| | | | | | | | | | | | | | | | | When we cleaned up the alternate function GPIO initialization, we left a declaration for configure_fan_gpios() in fan.h. That function doesn't exist anywhere, so there's no point in declaring it. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build everything. Nothing fails. Change-Id: I3d1fe1ff62e523aa7c87d57c5e838b01a0c6e899 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174334 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* throttle_ap.c should only be compiled if there's a chipset/power taskRandall Spangler2013-10-232-3/+9
| | | | | | | | | | | | | It doesn't need to be compiled if there would be nothing for it to talk to. BUG=chrome-os-partner:20739 BRANCH=none TEST=build all platforms, pass unit tests comment out chipset task in Rambi ec.tasklist; code still compiles Change-Id: I004364b8c1fdf02c420162b5ad2843068a26b452 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174302
* cleanup: Rename and move header filesRandall Spangler2013-10-2342-62/+54
| | | | | | | | | | | | | | Device-specific headers belong in driver/ or chip/. The include/ directory should be for common interfaces. Code should not normally need to include driver-specific headers. If it does, it should use the full relative path from the EC project root (for example, drivers/charger/bq24715.h). Change-Id: Id23db37a431e2d802a74ec601db6f69b613352ba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173746 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move source files to driver/ and power/ subdirsRandall Spangler2013-10-2333-29/+71
| | | | | | | | | | | | | | | | | | | | | The common/ subdir was getting cluttered. Move drivers for external components to a new driver/ tree, and move what used to be called chipset_*.c to a new power/ directory. This does not move/rename header files or CONFIG options. That will be done in subsequent steps, since moving and modifying .c files in the same CL is harder to review. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I67a3003dc8564783a320335cf0e9620a21982d5e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173601 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* bolt: Leave WiFi power on in S3Paul Stewart2013-10-231-2/+6
| | | | | | | | | | | | | | | | | This improves WiFi stability after resume since powering down may erase or otherwise stymy the firmware. Signed-off-by: Paul Stewart <pstew@chromium.org> BUG=chrome-os-partner:22175 BRANCH=none TEST=Suspend and resume bolt, make sure WiFi is still operable Change-Id: Ia9e39464955b373e6f03a36ca5af5c475e957208 Reviewed-on: https://chromium-review.googlesource.com/174257 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Paul Stewart <pstew@chromium.org> Commit-Queue: Paul Stewart <pstew@chromium.org>
* daisy: Clean up pmu initializationRandall Spangler2013-10-231-22/+1
| | | | | | | | | | | | | | CG_CTRL0 is already set to 2 by pmu_init_registers(), and the battery charge rate hack was temporary. BUG=chrome-os-partner:23425 BRANCH=none TEST=build daisy Change-Id: I863c8d6d5d5f30375dce14b7d2a30e9e710ef969 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173915 Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
* lpc: No need to scan entire host command I/O space for detectionRandall Spangler2013-10-232-13/+12
| | | | | | | | | | | | | | | | The EC LPC implementation guarantees that the status byte will have at least one zero bit, so there's no need to scan the parameter space as well. Removing this unneeded check will slightly speed up ectool. BUG=chrome-os-partner:10963 BRANCH=none TEST=on an x86 chromebook (e.g. link), ectool hello still works iotools io_read8 0x200 && iotools io_read8 0x204 -> not both 0xff Change-Id: Ic02ca0ee686ab10e50093807717ec638aaa468c6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174059 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Comments about PMU powerinfo moduleRandall Spangler2013-10-222-3/+18
| | | | | | | | | | | | | | | Document some Pit-platform-specific assumptions. No code changes. BUG=none BRANCH=none TEST=build pit Change-Id: I601ca4a57645ba45e7db01e271556a30d334f9cd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174056 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Remove obsolete comment in STM32 GPIO moduleRandall Spangler2013-10-221-1/+0
| | | | | | | | | | | | | | USB A-A cable works fine downloading firmware on pit now, so this comment no longer applies. BUG=none BRANCH=none TEST=build pit Change-Id: I4f07108357ffcab590fd95ffb50955f60698a39e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174047 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: More detail in todo comments for mccroskeyRandall Spangler2013-10-222-20/+23
| | | | | | | | | | | | | | This dev board hasn't seen much love. Add bug links for the unloved bits and remove an empty interrupt handler. BUG=chrome-os-partner:23494 BRANCH=none TEST=build mccroskey Change-Id: Ic521c6cba4ca438bf54f9ce77eb0cba99be57602 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174082 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: update comments with existing bug numbersRandall Spangler2013-10-224-25/+11
| | | | | | | | | | | | | | | Some of the comments no longer apply. Others needed more info. No code changes; just comment changes. BUG=none BRANCH=none TEST=build all platforms Change-Id: I1d52aa9a98427a78c9d9a8cf44934fb04c3c00c8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174084 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* rambi: Remove internal pullup from write protect pinRandall Spangler2013-10-221-1/+1
| | | | | | | | | | | | | | | The pin has a 100k series resistor, which is overwhelmed by the internal pullup. BUG=chrome-os-partner:23489 BRANCH=none TEST=gpioget wp_l, with screw present and removed. With screw present, signal should read 0; with it removed it should read 1. Change-Id: I35ee867111d0d7e8626dd3ac8010e9a10f46ccf7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174094 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* puppy: remove temporary workaround in pmu chipset startupRandall Spangler2013-10-221-14/+1
| | | | | | | | | | | | | | This was temporary until bug 18778 was fixed - which it was, a while ago. BUG=chrome-os-partner:23425 BRANCH=none TEST=build puppy Change-Id: I053867dcb1c3e74d0c09ac98a5c218bdca925317 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173799 Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* samus: Use analog BAT_TEMP as presence indicatorBill Richardson2013-10-222-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | There is an analog temperature line on the Samus battery connector. We don't yet know what it means, but there's a pull-up on it, so if it's reading close to ADC_READ_MAX, we can probably assume there's no battery. This change says that any reading within 90% of ADC_READ_MAX means the battery pack is not present, so we can go ahead and boot without trying to wake it up first. BUG=chrome-os-partner:23449 BRANCH=none TEST=manual Connect the battery, boot. It should happen quickly. Disconnect the battery, boot. It should STILL happen quickly. Running "adc" on the EC console should show an entry for "BatteryTemp". If no battery is connected, it should read somewhere close to 4095. Change-Id: I1e41bccb2a988d34de09192ebb0a68b91b1b0b24 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174046 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: FIFO comment in MKBP driverRandall Spangler2013-10-221-1/+9
| | | | | | | | | | | | | | | A 16-element FIFO consumes 208 bytes of RAM, which isn't too horrible. No code changes, just expanding on a comment. BUG=none BRANCH=none TEST=build spring Change-Id: Ibb51970b6fc72623435d21bd0b368c3e60da24da Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173922 Reviewed-by: Vic Yang <victoryang@chromium.org>
* cleanup: Remove fixme from ec_commands.hRandall Spangler2013-10-221-4/+1
| | | | | | | | | | | | | | | The fixme was just a feature request. I've moved it to a new bug. Comment change only; no code changes. BUG=chrome-os-partner:23457 BRANCH=none TEST=build rambi Change-Id: Ie3fc0482b6697c12040b868ba837073929cf5b82 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173921 Reviewed-by: Vic Yang <victoryang@chromium.org>
* bolt: Implement prochotstabilize-4856.BRandall Spangler2013-10-221-1/+2
| | | | | | | | | | | | | | | | This code is pretty much the same across all x86 chipsets. In the long run, maybe it should be moved to x86_common.c, but for now, simply implement on bolt what we did on samus and all the other haswell systems. BUG=chrome-os-partner:20372 BRANCH=none TEST=build bolt; don't have a bolt to test on Change-Id: I01c2795192fcbd3980ed464c1e3e1dfb64fdb228 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173798 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cleanup: Thermal commentsRandall Spangler2013-10-221-3/+11
| | | | | | | | | | | | | | No code changes, just replacing a FIXME from the comments with a more thorough explanation. BUG=chrome-os-partner:20805 BRANCH=none TEST=build falco Change-Id: Ibd98322c2b9fd6e0447771ce5fe43e0283743c60 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173930 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Remove battery temperature fixmes for falco and slippyRandall Spangler2013-10-222-2/+1
| | | | | | | | | | | | | | | | | | Falco has shipped, so those numbers are evidently good enough. Slippy is not being developed and won't be fixed. Simply note that numbers are estimates. Comment changes only; no code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build falco and slippy. Change-Id: I064896235626af8a5b7214b410908bba91434f7f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173911 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Comments in extpower_falco.cRandall Spangler2013-10-221-7/+13
| | | | | | | | | | | | | | | | | Note that adapter current limits are specific to the given battery charger chip used in falco. Since the file is named extpower_falco.c, no additional fixing needed. Comment change only; code is the same. BUG=none BRANCH=none TEST=compile falco Change-Id: I28d8b6c9335ec188c30f7c47fb2f8ecdda276bae Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173914 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Use low speed clock in deep sleep.Alec Berg2013-10-2119-21/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | Changed the low power idle task to use the low speed clock in deep sleep. The low power idle task is currently only enabled for Peppy, Slippy, and Falco. This change decreases power consumption when the AP is not running. Note that the low speed clock is slow enough that the JTAG cannot be used and the EC console UART cannot be used. To work around that, this commit detects when the JTAG is in use and when the EC console is in use, and will not use the low speed clock if either is in use. The JTAG in use never clears after being set and the console in use clears after a fixed timeout period. BUG=None BRANCH=None TEST=Passes all unit tests. Tested that the EC console works when in deep sleep. Tested that it is possible to run flash_ec when in deep sleep and using the low speed clock. Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rambi: Support USB port power controlRandall Spangler2013-10-212-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rambi shares several of the control signals (CTL1, ILIM_SEL) between both ports, and hard-wires some of the others (CTL2, CTL3). It still has separate enable lines for each port. BUG=chrome-os-partner:18343 BRANCH=none TEST=boot system; gpioget shows (in part) 1 USB_CTL1 0 USB_ILIM_SEL 1 USB1_ENABLE 1 USB2_ENABLE Then do 'apshutdown' and gpioget shows 1 USB_CTL1 0 USB_ILIM_SEL 0 USB1_ENABLE 0 USB2_ENABLE Change-Id: Ib3d321ca2b0aa7dce08ddd6633810a75641bc9a8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173737 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* cleanup: Consolidate power interruptsRandall Spangler2013-10-2125-163/+64
| | | | | | | | | | | | | | | | Every chipset had its own header file just to declare a GPIO interrupt handler. Since this seems to be a common feature of the power interface, make a standard power_interrupt() API provided by chipset.h. This lets us get rid of 4 include files, and makes it easier to add more chipsets in the future. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I1fc5612d42625ea46e0a8e16a83085b66d476664 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173745
* Clean up documentation of RCIN# open-drain workaroundRandall Spangler2013-10-216-32/+35
| | | | | | | | | | | | | | | | | | | On many of the Haswell boards, RCIN# was attached to PL6, which is not an open-drain capable GPIO. As a workaround, we toggle it to an input to get it into a high-Z state. Now that we understand the problem, document it and remove the FIXME tag from the comments. Baytrail systems map RCIN# to a different pin, so don't need this workaround at all. BUG=chrome-os-partner:20173 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I545a90a523e2967fad40bd47cb47a51983a37bdb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173796 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: Make RCIN_L be open drainDuncan Laurie2013-10-211-1/+1
| | | | | | | | | | | | | | This pin should not be driven, it is the source of massive leakage from PP3300_EC rail into PP3300_PCH. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec, verifed with scope Change-Id: I8b4ba7e2e842505244b2c7c55cd661ae9363dbad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173839 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add the pause_in_s5 support and fix CPU throttleDuncan Laurie2013-10-211-2/+36
| | | | | | | | | | | | | | | | These are changes ported from other haswell systems that are useful in development. Pause in S5 can be used for power cycle testing and the CPU throttle is important for runin since there is no other active throttle methods. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I8774a466141f2cdc671a5e14705ae29433f94981 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173838 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Add common i2cxfer console commandDuncan Laurie2013-10-213-179/+93
| | | | | | | | | | | | | | | | | This console command is useful during bringup to interrogate devices on the EC I2C interfaces. Ported from STM32 into the common file. This command now takes an additional argument for the port to be used. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec, tested on samus Change-Id: I8308fbc2f34e369a20051dca9c5d43872f239777 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173837 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add hook/hack to enable backlight PWMDuncan Laurie2013-10-213-2/+112
| | | | | | | | | | | | | | | | | | | | | | The backlight controller EEPROM is not enabling PWM mode and it is reloaded every time the backlight state is changed. Since we no longer have signals indicating when the PCH is enabling or disabling backlight this hack will read the controller every second at runtime to determine if it needs to enable PWM mode. This should be removed with the next build when the EEPROM is changed to enable PWM mode by default. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I5c4acb1115acb7a4a5b04d09c1317778eeb2998d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173836 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add TMP006 sensorsDuncan Laurie2013-10-212-7/+73
| | | | | | | | | | | | | Add the 6 on-board TMP006 sensors and I2C addresses. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: Id7fe37a9dda12c63dfbe5b8e2865902976f4b476 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173835 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: changes from bringup to bootDuncan Laurie2013-10-213-13/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | These were the changes from bringup to get the first boards booting successfully. Mostly minor stuff, some may not be entirely correct still. - disable internal clkrun so it behaves the same as other boards, this can be experiemented with later but is too much extra change during bringup - enable 1.8V internal pullup since it is missing external - wait for 1.5V and 1.2V PGOOD to ensure 5V rail is up - turn on 3.3V DSW rail in S5, it can be disabled later at runtime in theory but it is required for booting - turn on USB in S3 - specific wireless bringup sequencing, WLAN power should be first but the generic wireless function does it in the other order. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I698438f21651ce001e74790855bb7f7260d8bdaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173834 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: switch chip variant to STM32L100RBT6Vincent Palatin2013-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | The new boards will be populated with STM32L100RBT6, so let's update the CHIP_VARIANT accordingly. This is backward-compatible with the STM32L151RBT6 which is soldered on older boards (it just doesn't use the full memory). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=boot the system on Nyan reworked with STM32L100RBT6 Change-Id: I73a4c587c7dc3646777166606e06f3dfaed2400c Reviewed-on: https://chromium-review.googlesource.com/173633 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* stm32: add stm32l100 variantVincent Palatin2013-10-192-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | stm32l100 is mostly identical to stm32l151, excepted that the RAM is smaller (10kB instead of 16kB for the RB SKU), the EEPROM is smaller, there is no touch capability (but we are not using those 2 features). So, in the new stm32l100 variant configuration, we adjust the memory size to 10kB and keep the regular UART RX buffer size (512 B) rather than putting a 2kB buffer to fit in the new constraints. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run on discovery board reworked with stm32l100rct6 and Nyan reworked with stm32l100rbt6. Change-Id: Ifd78f59a102b3079f0f794af8058211dc724153d Reviewed-on: https://chromium-review.googlesource.com/173632 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* ec: add nyan boardYen Lin2013-10-1710-1/+1036
| | | | | | | | | | | | | | | | | | | This is to add nyan board support: - new files in board/nyan folder, including battery.c - new common/chipset_tegra.c, which is mostly based on chipset_gaia.c - new include/tegra_power.h - modified build.mk and flash_ec for nyan BUG=none BRANCH=nyan TEST=tested on Venice 2 board Change-Id: I36895f34f2f4d144a9440aff358c8274797ebbd6 Signed-off-by: Yen Lin <yelin@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/168078 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Re-enable basic tests for most LM4-based boardsVic Yang2013-10-171-6/+2
| | | | | | | | | | | | | | | | | | | Basic tests are actually working for most LM4-based boards. Let's re-enable them except for Bolt and Samus. These two boards have board-specific chipset code, which fails test compilation. BUG=chrome-os-partner:18598 TEST=Run affected tests on Link TEST=util/make_all.sh TEST='make tests' for all board BRANCH=None Change-Id: I46bc39c14ec43ccc29e9b0c46f349cac2755e684 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
* Correct the EC name in the build.mk comments for some boardsDavid Hendricks2013-10-174-4/+4
| | | | | | | | | | | | | | | | | | One of our partners was getting confused by the incorrect comments. Daisy, Snow and Pit use STM32xxxx parts with 128KB flash, but the comments indicated that they use 64KB parts. BUG=none BRANCH=none TEST=locally compiled Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I13035ca9fb0e4cb05f46df250f6b9079a799dd64 Reviewed-on: https://chromium-review.googlesource.com/172663 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org>
* cleanup: Config definesRandall Spangler2013-10-1611-61/+69
| | | | | | | | | | | | | | | | Add some missing descriptions in config.h and rename a few defines to be more consistent. No functional changes, just comments and symbol renaming. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I05a9a2ed6fd7bc8b14a18a0dc57d7d22430de21a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173111 Reviewed-by: Vic Yang <victoryang@chromium.org>
* x86: x86indebug command should print bit defintionsRandall Spangler2013-10-161-0/+12
| | | | | | | | | | | | | | | | | The chipset module prints debugging information about the state of power good lines and chipset signals, but those have previously been decodable only by looking at the EC source code. Change the 'x86indebug' command to print a decoder ring. BUG=chrome-os-partner:22895 BRANCH=none TEST=x86indebug prints a list of bit meanings Change-Id: I10eb653e23d19ece10635e5de61cd53b0d4d33d5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173089 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rambi: pullup SUS_STAT#Aaron Durbin2013-10-151-1/+2
| | | | | | | | | | | | | | | | The SUS_STAT# from the SoC doesn't have a pullup resistor stuffed on the other side of the FET separating the 1.8V and 3.3V signals. Therefore use the internal pull. BUG=None BRANCH=None TEST=Built and loaded on a rambi. SUS_STAT# doesn't appear to float any more. Change-Id: I7478697b68b4539c17876722a7a913901bf1c0bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172851 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: GPIO interrupt handler scans through fewer GPIOsRandall Spangler2013-10-151-2/+4
| | | | | | | | | | | | | | | | | | | | | Rather than scan the entire GPIO table, stop as soon as all interrupt bits have been handled. We hand-order the table so GPIOs with interrupts are first, so this should reduce interrupt overhead. BUG=chrome-os-partner:23296 BRANCH=none TEST=boot rambi x86indebug -1 apshutdown powerbtn ...That should print lots of 'x86 in' debug messages as pins change state, showing that the interrupt handlers are still responding. Change-Id: I7942cd51870ad51de068d90d68cf6634ff2fb1a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173031 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Do not compile Baytrail chipset code if chipset task is absentVic Yang2013-10-151-0/+1
| | | | | | | | | | | | | | | Like other chipset code files, we shouldn't compile Baytrail chipset code if chipset task is absent. BUG=None TEST=basic tests now compile on Rambi without error BRANCH=None Change-Id: I231de06310b2e0d7ff7b3e1e21bbff89636cd5c0 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172980 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-1522-141/+552
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* Enforce a minimum number of clocks between keyboard scansRandall Spangler2013-10-144-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | When the EC CPU is running at a decreased clock frequency, frequent keyboard scans can starve other EC tasks of CPU and lead to dropped data or watchdog timeouts. Enforce a minimum number of EC clocks between keyboard scans to prevent this from happening. The default chosen (16000 clocks) is equal to the shortest post-scan delay (1 ms) of any current board when the AP is in S0, so this should have no effect when the AP is in S0. When the AP is in S3 or S5, we don't need to scan the keyboard as frequently anyway. This can be overridden on a per-board basis for future boards if needed. BUG=chrome-os-partner:23247 BRANCH=pit TEST=apshutdown, then hold down a key for 10 seconds. Should not see a watchdog reset. Change-Id: I228f53a32ad4769f6a137a9ab06903111bea115d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172895 Reviewed-by: Vic Yang <victoryang@chromium.org>
* rambi: Fix driving keyboard column 2Randall Spangler2013-10-141-0/+8
| | | | | | | | | | | | | | | Rambi's Silego chip inverts the pull as well as the signal. So it has a pulldown for the signal instead of a pullup. The EC must drive the signal push-pull, since open-drain only works for signals with pullups. BUG=chrome-os-partner:23198 BRANCH=none TEST=type on keyboard; C/D/E/3/F1-F4 should all work Change-Id: Iaea4f540c523824571a568b70cca3e0fb467f79c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172915 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Return hash status on HAST_START commandVic Yang2013-10-141-5/+4
| | | | | | | | | | | | | | | On HASH_START command, we should also fill in hash status in response so that the caller sees BUSY status in response. BUG=chrome-os-partner:23067 TEST=Along with u-boot change, corrupting EC RW followed by a warm reset doesn't result in shutdown. BRANCH=All Change-Id: Ie0c1b35d71bc0420b011f0413f92feb88138db4d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172380 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* falco: fixed backlight bugAlec Berg2013-10-141-0/+1
| | | | | | | | | | | | | | Fixed backlight bug on Falco. BUG=chrome-os-partner:23270 BRANCH=none TEST=Tested to make sure the backlight comes on for Falco. Change-Id: Ia74801fdae8ce2d96d03223a95cb0704ddc1f4b0 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172940 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
View Lorry Controller Status