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* bolt: Implement prochotstabilize-4856.BRandall Spangler2013-10-221-1/+2
| | | | | | | | | | | | | | | | This code is pretty much the same across all x86 chipsets. In the long run, maybe it should be moved to x86_common.c, but for now, simply implement on bolt what we did on samus and all the other haswell systems. BUG=chrome-os-partner:20372 BRANCH=none TEST=build bolt; don't have a bolt to test on Change-Id: I01c2795192fcbd3980ed464c1e3e1dfb64fdb228 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173798 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cleanup: Thermal commentsRandall Spangler2013-10-221-3/+11
| | | | | | | | | | | | | | No code changes, just replacing a FIXME from the comments with a more thorough explanation. BUG=chrome-os-partner:20805 BRANCH=none TEST=build falco Change-Id: Ibd98322c2b9fd6e0447771ce5fe43e0283743c60 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173930 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Remove battery temperature fixmes for falco and slippyRandall Spangler2013-10-222-2/+1
| | | | | | | | | | | | | | | | | | Falco has shipped, so those numbers are evidently good enough. Slippy is not being developed and won't be fixed. Simply note that numbers are estimates. Comment changes only; no code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build falco and slippy. Change-Id: I064896235626af8a5b7214b410908bba91434f7f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173911 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Comments in extpower_falco.cRandall Spangler2013-10-221-7/+13
| | | | | | | | | | | | | | | | | Note that adapter current limits are specific to the given battery charger chip used in falco. Since the file is named extpower_falco.c, no additional fixing needed. Comment change only; code is the same. BUG=none BRANCH=none TEST=compile falco Change-Id: I28d8b6c9335ec188c30f7c47fb2f8ecdda276bae Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173914 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Use low speed clock in deep sleep.Alec Berg2013-10-2119-21/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | Changed the low power idle task to use the low speed clock in deep sleep. The low power idle task is currently only enabled for Peppy, Slippy, and Falco. This change decreases power consumption when the AP is not running. Note that the low speed clock is slow enough that the JTAG cannot be used and the EC console UART cannot be used. To work around that, this commit detects when the JTAG is in use and when the EC console is in use, and will not use the low speed clock if either is in use. The JTAG in use never clears after being set and the console in use clears after a fixed timeout period. BUG=None BRANCH=None TEST=Passes all unit tests. Tested that the EC console works when in deep sleep. Tested that it is possible to run flash_ec when in deep sleep and using the low speed clock. Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rambi: Support USB port power controlRandall Spangler2013-10-212-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rambi shares several of the control signals (CTL1, ILIM_SEL) between both ports, and hard-wires some of the others (CTL2, CTL3). It still has separate enable lines for each port. BUG=chrome-os-partner:18343 BRANCH=none TEST=boot system; gpioget shows (in part) 1 USB_CTL1 0 USB_ILIM_SEL 1 USB1_ENABLE 1 USB2_ENABLE Then do 'apshutdown' and gpioget shows 1 USB_CTL1 0 USB_ILIM_SEL 0 USB1_ENABLE 0 USB2_ENABLE Change-Id: Ib3d321ca2b0aa7dce08ddd6633810a75641bc9a8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173737 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* cleanup: Consolidate power interruptsRandall Spangler2013-10-2125-163/+64
| | | | | | | | | | | | | | | | Every chipset had its own header file just to declare a GPIO interrupt handler. Since this seems to be a common feature of the power interface, make a standard power_interrupt() API provided by chipset.h. This lets us get rid of 4 include files, and makes it easier to add more chipsets in the future. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I1fc5612d42625ea46e0a8e16a83085b66d476664 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173745
* Clean up documentation of RCIN# open-drain workaroundRandall Spangler2013-10-216-32/+35
| | | | | | | | | | | | | | | | | | | On many of the Haswell boards, RCIN# was attached to PL6, which is not an open-drain capable GPIO. As a workaround, we toggle it to an input to get it into a high-Z state. Now that we understand the problem, document it and remove the FIXME tag from the comments. Baytrail systems map RCIN# to a different pin, so don't need this workaround at all. BUG=chrome-os-partner:20173 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I545a90a523e2967fad40bd47cb47a51983a37bdb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173796 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: Make RCIN_L be open drainDuncan Laurie2013-10-211-1/+1
| | | | | | | | | | | | | | This pin should not be driven, it is the source of massive leakage from PP3300_EC rail into PP3300_PCH. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec, verifed with scope Change-Id: I8b4ba7e2e842505244b2c7c55cd661ae9363dbad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173839 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add the pause_in_s5 support and fix CPU throttleDuncan Laurie2013-10-211-2/+36
| | | | | | | | | | | | | | | | These are changes ported from other haswell systems that are useful in development. Pause in S5 can be used for power cycle testing and the CPU throttle is important for runin since there is no other active throttle methods. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I8774a466141f2cdc671a5e14705ae29433f94981 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173838 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Add common i2cxfer console commandDuncan Laurie2013-10-213-179/+93
| | | | | | | | | | | | | | | | | This console command is useful during bringup to interrogate devices on the EC I2C interfaces. Ported from STM32 into the common file. This command now takes an additional argument for the port to be used. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec, tested on samus Change-Id: I8308fbc2f34e369a20051dca9c5d43872f239777 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173837 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add hook/hack to enable backlight PWMDuncan Laurie2013-10-213-2/+112
| | | | | | | | | | | | | | | | | | | | | | The backlight controller EEPROM is not enabling PWM mode and it is reloaded every time the backlight state is changed. Since we no longer have signals indicating when the PCH is enabling or disabling backlight this hack will read the controller every second at runtime to determine if it needs to enable PWM mode. This should be removed with the next build when the EEPROM is changed to enable PWM mode by default. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I5c4acb1115acb7a4a5b04d09c1317778eeb2998d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173836 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: Add TMP006 sensorsDuncan Laurie2013-10-212-7/+73
| | | | | | | | | | | | | Add the 6 on-board TMP006 sensors and I2C addresses. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: Id7fe37a9dda12c63dfbe5b8e2865902976f4b476 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173835 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: changes from bringup to bootDuncan Laurie2013-10-213-13/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | These were the changes from bringup to get the first boards booting successfully. Mostly minor stuff, some may not be entirely correct still. - disable internal clkrun so it behaves the same as other boards, this can be experiemented with later but is too much extra change during bringup - enable 1.8V internal pullup since it is missing external - wait for 1.5V and 1.2V PGOOD to ensure 5V rail is up - turn on 3.3V DSW rail in S5, it can be disabled later at runtime in theory but it is required for booting - turn on USB in S3 - specific wireless bringup sequencing, WLAN power should be first but the generic wireless function does it in the other order. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec Change-Id: I698438f21651ce001e74790855bb7f7260d8bdaf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173834 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: switch chip variant to STM32L100RBT6Vincent Palatin2013-10-191-2/+2
| | | | | | | | | | | | | | | | | | | | | The new boards will be populated with STM32L100RBT6, so let's update the CHIP_VARIANT accordingly. This is backward-compatible with the STM32L151RBT6 which is soldered on older boards (it just doesn't use the full memory). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=boot the system on Nyan reworked with STM32L100RBT6 Change-Id: I73a4c587c7dc3646777166606e06f3dfaed2400c Reviewed-on: https://chromium-review.googlesource.com/173633 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* stm32: add stm32l100 variantVincent Palatin2013-10-192-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | stm32l100 is mostly identical to stm32l151, excepted that the RAM is smaller (10kB instead of 16kB for the RB SKU), the EEPROM is smaller, there is no touch capability (but we are not using those 2 features). So, in the new stm32l100 variant configuration, we adjust the memory size to 10kB and keep the regular UART RX buffer size (512 B) rather than putting a 2kB buffer to fit in the new constraints. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run on discovery board reworked with stm32l100rct6 and Nyan reworked with stm32l100rbt6. Change-Id: Ifd78f59a102b3079f0f794af8058211dc724153d Reviewed-on: https://chromium-review.googlesource.com/173632 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* ec: add nyan boardYen Lin2013-10-1710-1/+1036
| | | | | | | | | | | | | | | | | | | This is to add nyan board support: - new files in board/nyan folder, including battery.c - new common/chipset_tegra.c, which is mostly based on chipset_gaia.c - new include/tegra_power.h - modified build.mk and flash_ec for nyan BUG=none BRANCH=nyan TEST=tested on Venice 2 board Change-Id: I36895f34f2f4d144a9440aff358c8274797ebbd6 Signed-off-by: Yen Lin <yelin@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/168078 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Re-enable basic tests for most LM4-based boardsVic Yang2013-10-171-6/+2
| | | | | | | | | | | | | | | | | | | Basic tests are actually working for most LM4-based boards. Let's re-enable them except for Bolt and Samus. These two boards have board-specific chipset code, which fails test compilation. BUG=chrome-os-partner:18598 TEST=Run affected tests on Link TEST=util/make_all.sh TEST='make tests' for all board BRANCH=None Change-Id: I46bc39c14ec43ccc29e9b0c46f349cac2755e684 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
* Correct the EC name in the build.mk comments for some boardsDavid Hendricks2013-10-174-4/+4
| | | | | | | | | | | | | | | | | | One of our partners was getting confused by the incorrect comments. Daisy, Snow and Pit use STM32xxxx parts with 128KB flash, but the comments indicated that they use 64KB parts. BUG=none BRANCH=none TEST=locally compiled Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I13035ca9fb0e4cb05f46df250f6b9079a799dd64 Reviewed-on: https://chromium-review.googlesource.com/172663 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org>
* cleanup: Config definesRandall Spangler2013-10-1611-61/+69
| | | | | | | | | | | | | | | | Add some missing descriptions in config.h and rename a few defines to be more consistent. No functional changes, just comments and symbol renaming. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I05a9a2ed6fd7bc8b14a18a0dc57d7d22430de21a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173111 Reviewed-by: Vic Yang <victoryang@chromium.org>
* x86: x86indebug command should print bit defintionsRandall Spangler2013-10-161-0/+12
| | | | | | | | | | | | | | | | | The chipset module prints debugging information about the state of power good lines and chipset signals, but those have previously been decodable only by looking at the EC source code. Change the 'x86indebug' command to print a decoder ring. BUG=chrome-os-partner:22895 BRANCH=none TEST=x86indebug prints a list of bit meanings Change-Id: I10eb653e23d19ece10635e5de61cd53b0d4d33d5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173089 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rambi: pullup SUS_STAT#Aaron Durbin2013-10-151-1/+2
| | | | | | | | | | | | | | | | The SUS_STAT# from the SoC doesn't have a pullup resistor stuffed on the other side of the FET separating the 1.8V and 3.3V signals. Therefore use the internal pull. BUG=None BRANCH=None TEST=Built and loaded on a rambi. SUS_STAT# doesn't appear to float any more. Change-Id: I7478697b68b4539c17876722a7a913901bf1c0bc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172851 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: GPIO interrupt handler scans through fewer GPIOsRandall Spangler2013-10-151-2/+4
| | | | | | | | | | | | | | | | | | | | | Rather than scan the entire GPIO table, stop as soon as all interrupt bits have been handled. We hand-order the table so GPIOs with interrupts are first, so this should reduce interrupt overhead. BUG=chrome-os-partner:23296 BRANCH=none TEST=boot rambi x86indebug -1 apshutdown powerbtn ...That should print lots of 'x86 in' debug messages as pins change state, showing that the interrupt handlers are still responding. Change-Id: I7942cd51870ad51de068d90d68cf6634ff2fb1a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173031 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Do not compile Baytrail chipset code if chipset task is absentVic Yang2013-10-151-0/+1
| | | | | | | | | | | | | | | Like other chipset code files, we shouldn't compile Baytrail chipset code if chipset task is absent. BUG=None TEST=basic tests now compile on Rambi without error BRANCH=None Change-Id: I231de06310b2e0d7ff7b3e1e21bbff89636cd5c0 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172980 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-1522-141/+552
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* Enforce a minimum number of clocks between keyboard scansRandall Spangler2013-10-144-1/+49
| | | | | | | | | | | | | | | | | | | | | | | | When the EC CPU is running at a decreased clock frequency, frequent keyboard scans can starve other EC tasks of CPU and lead to dropped data or watchdog timeouts. Enforce a minimum number of EC clocks between keyboard scans to prevent this from happening. The default chosen (16000 clocks) is equal to the shortest post-scan delay (1 ms) of any current board when the AP is in S0, so this should have no effect when the AP is in S0. When the AP is in S3 or S5, we don't need to scan the keyboard as frequently anyway. This can be overridden on a per-board basis for future boards if needed. BUG=chrome-os-partner:23247 BRANCH=pit TEST=apshutdown, then hold down a key for 10 seconds. Should not see a watchdog reset. Change-Id: I228f53a32ad4769f6a137a9ab06903111bea115d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172895 Reviewed-by: Vic Yang <victoryang@chromium.org>
* rambi: Fix driving keyboard column 2Randall Spangler2013-10-141-0/+8
| | | | | | | | | | | | | | | Rambi's Silego chip inverts the pull as well as the signal. So it has a pulldown for the signal instead of a pullup. The EC must drive the signal push-pull, since open-drain only works for signals with pullups. BUG=chrome-os-partner:23198 BRANCH=none TEST=type on keyboard; C/D/E/3/F1-F4 should all work Change-Id: Iaea4f540c523824571a568b70cca3e0fb467f79c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172915 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Return hash status on HAST_START commandVic Yang2013-10-141-5/+4
| | | | | | | | | | | | | | | On HASH_START command, we should also fill in hash status in response so that the caller sees BUSY status in response. BUG=chrome-os-partner:23067 TEST=Along with u-boot change, corrupting EC RW followed by a warm reset doesn't result in shutdown. BRANCH=All Change-Id: Ie0c1b35d71bc0420b011f0413f92feb88138db4d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172380 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* falco: fixed backlight bugAlec Berg2013-10-141-0/+1
| | | | | | | | | | | | | | Fixed backlight bug on Falco. BUG=chrome-os-partner:23270 BRANCH=none TEST=Tested to make sure the backlight comes on for Falco. Change-Id: Ia74801fdae8ce2d96d03223a95cb0704ddc1f4b0 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172940 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add baytrail power sequencingRandall Spangler2013-10-116-6/+377
| | | | | | | | | | | | | | | | | This is an initial version of power sequencing for the rambi rev.1 boards. It has a workaround for a rev.1 board problem; this requires turning on PP5000 early. BUG=chrome-os-partner:22895 BRANCH=none TEST=AP should power on to S0 (PLTRST# deasserts) automatically when EC boots Then 'apshutdown' should drag it back to G3. Then 'powerbtn' should take it back to S0. Change-Id: Id9bc6fe9b55fce3eb46ce1265891724ec7a4ae20 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172675 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* rambi: Keyboard output column 2 must be invertedRandall Spangler2013-10-113-17/+25
| | | | | | | | | | | | | The Silego chip used on Rambi inverts column 2. So the EC should pull the signal low when NOT scanning column 2, and release it at all other times. BUG=chrome-os-partner:23198 BRANCH=none TEST=not yet; need to probe on scope Change-Id: If6a784493533f11ae54d18f27591697e69aa2282 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172674 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lm4: Modified clock gating to allow easy expansion to low power.Alec Berg2013-10-1018-74/+264
| | | | | | | | | | | | | | | | | | | | | Created a new function to enable or disable clocks to various peripherals. This new function makes it easy to specify if you want the clock enabled in run mode, sleep mode, and/or deep sleep mode. Added infrastructure to specify which GPIOs should interrupt the EC from deep sleep. BUG=none BRANCH=none TEST=Passes all unit tests. Ran on a peppy and verified that the clock gate control registers in run mode (LM4_RCGC regs) were the same before and after this change. Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix bug with hibernate delay when running off batteryAlec Berg2013-10-101-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes hibernate delay logic for chipset x86. With this change the machine will go in to hibernate one hour after going into G3 when running off battery. BUG=chrome-os-partner:23224 BRANCH=none TEST=Used console command hibdelay to set a reasonable hibernate delay time and tested all combinations of running off battery vs. AC and shutting off before or after the machine has been on for a hibdelay amount of time. Change-Id: Idd94d3677669dcd405732195b8cbbc1edca1e171 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172512 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rambi: fix leakage on pp3300_pch_s5 railAaron Durbin2013-10-101-1/+1
| | | | | | | | | | | | | | | | | PWRBTN_L is pulled up to PP3300_PCH_S5 through a 30K resistor. However, the PWRBTN_L pin was configured push-pull. So we are leaking into that rail. Fix this by configuring it to be open drain. BUG=chrome-os-partner:23221 BRANCH=None TEST=Loaded new EC with change and noted the PP3300_PCH_S5_PG is driven low correctly once the PP5000_DSW rail is up an SUSP_VR_EN=0. Change-Id: Id6d5079ca0c11c36b00ed913be378f53b48f27f3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172520 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Don't use [N] = {} when initializing arraysBill Richardson2013-10-1012-34/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we do this: enum foo_v { FOO_A, FOO_B, FOO_COUNT }; struct foo_t foo[] = { {...}, {...}, }; BUILD_ASSERT(ARRAY_SIZE(foo) == FOO_COUNT); Then we can be sure we're at least initialized all the elements of foo, although there's no particular guarantee that the order is correct. However, if we use this: struct foo_t foo[] = { [FOO_A] = {...}, [FOO_B] = {...}, }; and we accidentally get one wrong: struct foo_t foo[] = { [FOO_B] = {...}, [FOO_B] = {...}, }; Then the assertion still passes, but we've only initialized one element. Don't do that. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Refactoring only. Build everything. It should still work. Change-Id: I58f659207990f18c6fb74b1cac2ec1163cdb07ea Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172115 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rambi: Control LEDs using PWMRandall Spangler2013-10-0812-21/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | Rambi has a pair of LEDs which are attached to the PWM fan controller. Add support for them. Also add a generic 'pwmduty' command which can be used to get/set the duty cycle for any PWM channel. Also fix rounding errors in pwm module, so that set/get duty doesn't keep rounding down. BUG=chrome-os-partner:22895 BRANCH=none TEST=Boot rambi. LEDs are off. pwmduty -> both are 0% pwmduty 0 10 -> green LED on dimly pwmduty 1 10 -> red LED on dimly pwmduty 0 99 -> green LED on brightly pwmduty 1 100 -> red LED on brightly pwmduty 1 0 -> red LED off pwmduty 1 -1 -> red LED turns back on because fan controller is disabled pwmduty -> channel 0 at 99%, channel 1 disabled Build all platforms. Pass all unit tests. Change-Id: Ib0a6289a757554e696a9a0153a85bdc34e2ee2ae Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172094
* cleanup: Battery header files and filenamesRandall Spangler2013-10-0738-244/+328
| | | | | | | | | | | | | | | | | | | | battery.h is the high-level interface. battery_smart.h is the low-level interface. Most things don't need the low-level interface, but were including smart_battery.h solely to get at battery.h. Fixed this. Also merged battery_pack.h into battery.h, since it was odd to split that data across multiple header files. Tidied the function comments in battery.h as well. No functional changes, just renaming files and adding comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I5ef372f0a5f8f5f36e09a3a1ce24008685c1fd0d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171967 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Move board-specific LED state machines to board dirsRandall Spangler2013-10-0718-13/+15
| | | | | | | | | | | | | | | | | | | | | | The LED state machine ends up being very board-specific, as does the specific configuration of LEDs and whether they're PWM'd or just GPIOs. dparker has some clever ideas for how to move more of the functionality to common/led_common.c (used at present only by peppy); that will be done as a follow-on to this CL. There's a unit test for the spring LED implementation. To keep that compiling, just use a symlink to the spring-specific implementation. No code changes; just moving around files. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I5973e701a29a72575db9a161dc146855ab21cca6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171771 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Replace awkward I2C_PORTS_USED macro with constantBill Richardson2013-10-0732-47/+26
| | | | | | | | | | | | | | | | | | | | We only used I2C_PORTS_USED to iterate through the list of hardware ports actually in use, but we defined it in board.h at the same place where we matched particular I2C devices to the (possibly shared) buses they're on. This CL makes I2C_PORTS_USED into a global constant, so it can be set automatically where we initialize the ports, and doesn't have to be related to the list of attached devices. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build everything, run all tests, should still work. Change-Id: I65f22f5cadfc4b3afe51af48faa5fb369bc3aa09 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171884
* bolt: Make fan min/max be the same as linkDuncan Laurie2013-10-051-2/+2
| | | | | | | | | | | | | | | The fan was not spinning enough to cool the system because it thought the max fan speed was 5000. BUG=none BRANCH=bolt TEST=build and boot on bolt, generate load and see that the fan comes on to a reasonable level to cool the system. Change-Id: Ifa5023534a6be8625abf7df7fa44aed649f4fabc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171969 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* samus: Add battery_is_connected checkBill Richardson2013-10-042-0/+11
| | | | | | | | | | | | | | | | | | | | | | | Copied from Bolt. This is so the 30-second wait when no battery is installed can be skipped. Note that if we ever decide to monitor the battery temp through the BAT_TEMP line, we'll have to rethink how battery_is_connected() is implemented, since we can't reliably treat that GPIO as both digital and analog simultaneously. BUG=chrome-os-partner:22870 BRANCH=none TEST=manual cd src/platform/ec make BOARD=samus make runtests Change-Id: Ifea952c8f99b2b40c2fab382e949958a2f71d157 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171796 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* samus: alternate functions, chargerBill Richardson2013-10-043-15/+38
| | | | | | | | | | | | | | | | Adding some more board-specific configurations for Samus. BUG=chrome-os-partner:22870 BRANCH=none TEST=manual make runtests Change-Id: I86c909e899fb5bdb6ba75f476ced58bae2c75c29 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171809 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* bolt: Add battery_is_connected checkDuncan Laurie2013-10-042-0/+11
| | | | | | | | | | | | | | | | | | | | This is so the 30 second wait when no battery is installed can be skipped. Since Bolt needs a complete AC+Battery disconnect when updating the BIOS this 30 second wait is aggravating. BUG=chrome-os-partner:20448 BRANCH=bolt TEST=disconnect AC+Battery, then connect AC and watch it boot without waiting for 30 seconds. Change-Id: Ibaf42fe1dba9c74aa465aa0a1a5381ba6981f66e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171689 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cleanup use of config.h macrosBill Richardson2013-10-049-21/+13
| | | | | | | | | | | | | | | | | | | | | | | | include/config.h should have the canonical list of all CONFIG_* macros used everywhere else. This fixes some that weren't included, and some that had been changed in one place but not in others. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build everything. It should still work. cd src/plaform/ec make runtests for i in bds bolt daisy discovery falco kirby link mccroskey peppy pit puppy rambi samus slippy snow spring; do make BOARD=$i || touch died.$i; done There shouldn't be any died.* files. Change-Id: I0a1ec2d57668509c514dc5a521e547836a3e9894 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171690 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: First pass at GPIOsBill Richardson2013-10-023-135/+79
| | | | | | | | | | | | | | | | | | | This is the first attempt at wiring the GPIOs for Samus. More to come, of course. BUG=chrome-os-partner:22870 BRANCH=none TEST=manual The only thing we can check is that it compiles and doesn't break anything. cd src/platform/ec make BOARD=samus make runtests Change-Id: Ia9dc94c420c21551c5db3e28e749954cea3055a1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171528
* Fix typo: s/GPOI_/GPIO_/gBill Richardson2013-10-023-3/+3
| | | | | | | | | | | | | | | | Slippy, Peppy, and Falco should learn to spell. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual make runtests Nothing uses this, it's just annoying to look at. Change-Id: I61e09fc6a804c1de972b34520db1db8f0b874dbe Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171567
* Internalize magic numbers for smart USB chargingBill Richardson2013-10-022-4/+4
| | | | | | | | | | | | | | | | | | | | | Link is the only platform that uses smart usb ports. Link's board.h defines USB_CHARGE_PORT_COUNT, yet the usb_port_power_smart.c file is peppered with assumptions that that constant is always 2. This moves the constant into usb_port_power_smart.c where it belongs. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual make runtests Code refactoring only, no visible changes, Change-Id: Id45e11d88585a98348105b1399c7e18c554add50 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171565 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Always enable tpschrome low current chargingRong Chang2013-10-021-20/+4
| | | | | | | | | | | | | | | | | | | | | The PMU charger loop is conservative. And there is no need to set hardware low charging current termination. BRANCH=pit BUG=chrome-os-partner:22946 TEST=manual Discharge the battery to level < 40%. Issue console command 'pmu', check register 0x09 output. The NOITERM bit(5) should be set to 1. That means no low charging current termination. Signed-off-by: Rong Chang <rongchang@chromium.org> Change-Id: I45532dcaab3bab566407b209f26693e2c3451014 Reviewed-on: https://chromium-review.googlesource.com/170906 Reviewed-by: Hung-ying Tyan <tyanh@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jaehoon Kim <jh228.kim@samsung.com> Tested-by: Jaehoon Kim <jh228.kim@samsung.com>
* lpc: Clean up processing wake eventsRandall Spangler2013-10-029-122/+18
| | | | | | | | | | | | | | | | | | | | | | Every board other than link does the same thing - filter out the power button event, then set the WAKE_L gpio level based on the remaining events. This code doesn't need to be duplicated 7 times, so make it common. Link didn't filter out the power button wake signal, but works fine with the common implementation. Like the other boards it gets a power button wake event via the dedicated PCH PWRBTN# signal. BUG=chrome-os-partner:18343 BRANCH=none TEST=suspend link, then wake using power button press compile all platforms; pass unit tests Change-Id: Ib3a6d310d0f5e337374b3c331ab2872fe377bdf6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171405 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* bolt: Fix panel power passthruDuncan Laurie2013-10-023-2/+4
| | | | | | | | | | | | | | | | | The Bolt board does not use the standard CHIPSET_HASWELL and with a recent commit that meant haswell_interrupt() was defined to NULL and it would not turn on the panel power. BUG=chrome-os-partner:20372 BRANCH=bolt TEST=build and boot on bolt and see magic working panel Change-Id: I6174e2b4a8337acc2f395b8b2b18a00107661af1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171112 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Randall Spangler <rspangler@chromium.org>
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