| Commit message (Collapse) | Author | Age | Files | Lines |
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The unimplemented fields in tcpm_drv may cause ec jumping into some
undefined address. Prevent this happen by checking flags at compile
time.
BUG=None
TEST=make buildall -j
BRANCH=master
Change-Id: I68f47cdc34046e7551f00f72267850b4f0464200
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1710211
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Implement the common code to provide a friendly interface to control the
IOs of IO expander. It adopts a similar concept to GPIO.
1. Define the IO expander IO in gpio.inc by the format:
IOEX(name, EXPIN(ioex, port, offset), flags)
- name: the name of this IO pin
- EXPIN(ioex, port, offset)
- ioex: the IO expander port (defined in board.c) this IO
pin belongs to.
- port: the port number in the IO expander chip.
- offset: the bit offset in the port above.
- flags: the same as the flags of GPIO.
2. The following APIs are supported:
1. ioex_get_flags_by_mask
2. ioex_set_flags_by_mask
3. ioex_get_flags
4. ioex_set_flags
5. ioex_get_level
6. ioex_set_level
7. ioex_init
3. The following console commands are supported:
1. ioexget [IO_EXPANDER_PIN_NAME]
2. ioexset IO_EXPANDER_PIN_NAME 0/1
BRANCH=none
BUG=none
TEST=No error for "make buildall"
TEST=Apply this and related CLs, manually test each API, make sure each
function works correctly with IO expander chip (NCT3807/NCT3808.)
Change-Id: I79c9813abccc67d5554e2ceb5c119dcf549b7dce
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657858
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
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These boards are the new FPMCU names that make it easier to separate out
the FPMCU from the underlying platform that the FPMCU is connected to.
We need to keep the old names around for legacy build and signing
purposes, so we just use symlinks.
BRANCH=none
BUG=b:136678758,b:137108509
TEST=make BOARD=bloonchipper -j
make BOARD=dartmonkey -j
make buildall -j
Change-Id: I792c182962f9699ac16f6cc29f4da10716808915
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715638
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch fixes how the console messages in isl923x.c are printed.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I81cd1fc9f0a20a4908013b7b3051fc23953eefc2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670699
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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The ACProchot register takes a value in multiple of 128 up to 6400
mA. This patch makes isl923x_set_ac_prochot return error when a
value exceeding the max is passed.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/130387567
BRANCH=Nami
TEST=buildall
Change-Id: I1854f091d6ee7eb042fefeff35094abeca452c2f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1669796
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
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For fingerprint firmware we are moving towards a model where the "board"
(in EC terminology) is a specific MCU+FP_SENSOR combination and not tied
to the main system board that it's connected to (e.g., "hatch",
"nocturne", etc.). This change decouples flash_fp_mcu from the EC
"board".
BRANCH=none
BUG=b:136678758,b:137108509
TEST=make buildall -j
hatch:
flash_fp_mcu /opt/google/biod/fw/hatch_fp_v2.0.1359-6f54be08d.bin
nocturne:
flash_fp_mcu /opt/google/biod/fw/nocturne_fp_v2.0.1765+87bb17a39.bin
nami:
flash_fp_mcu /opt/google/biod/fw/nami_fp_v2.2.144-7a08e07eb.bin
Cq-Depend:chromium:1705055
Change-Id: Idfe298f59ab9df8657a570cc47e956b4e94ee1a1
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1704808
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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BRANCH=none
BUG=b:125419658
TEST=Remove "-U" flag in STM32MON_READ_FLAGS in flash_fp_mcu_common.sh
flash_fp_mcu -r foo.bin => success
hexdump foo.bin => valid data
ectool --name=cros_fp flashprotect enable
ectool --name=cros_fp reboot_ec
flash_fp_mcu -r foo.bin => fails
Add "-U" flag back to STM32MON_READ_FLAGS in flash_fp_mcu_common.sh
flash_fp_mcu -r foo.bin => success
hexdump foo.bin => all 0xFF
Change-Id: Ic3ec18262e653b72baf239caa8db12186a63613c
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692220
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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report_no_payload_failure() function gets an input 'failure type',
but it always marks failure type as 'inconsistent flash content'
instead of that input.
BUG=None
BRANCH=cr50, cr50-mp
TEST=none
Change-Id: I5bac69478416eeabf735faf5333f5f7eaa98b54e
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715910
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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EC code changed over to a 7-bit slave address and stored in a uint16_t
to generically be able to handle 10-bit addresses, if they are ever
needed, as well as common bit flags in the most significant bits.
This code does not use more than the 8 least significant bits but to
be EC consistent, I am making this 16 bits.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ic5f4b3500ae7b3c18380b188efbc37c01d58d7e9
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714136
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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In case sighing failure happens, let's not delete temporary files and
let's report the full failed signer invocation command line so that it
is easy to debug the problem.
BRANCH=none
BUG=none
TEST=debugged failure to sign the MP image which happened after
transitioning into a new sighing environment.
Change-Id: I55accb6887ad00103c9aa7b69aa373f886bce64e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715325
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This is needed to support CCD testing of UART to USB bridging.
BRANCH=none
BUG=b:38448364
TEST=ran 'make BOARD=hatch -j', verified that command is included in
the symbol map.
Change-Id: I11a9dcf7c3204a4464eb5305d0b6b38f51205575
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688135
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The Hatch platform uses dedicated interrupt lines for the SN5S330
PPC. This patch helps to ensure that all PPC interrupts are processed,
even when interrupts happen during processing.
BUG=b:137783988
BRANCH=none
TEST=Verified that charging/discharging are still processed as expected.
Change-Id: I5c3b003f60aaa239d3ee7a477006913ce8f83ac5
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714137
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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In the original firmware (in the uart_buffering.c), it clears the
SLEEP_MASK_UART immediately after it pushes all characters from its Tx
buffer to UART's FIFO without checking the status of transmission. It
may break the transmission because EC goes to deep sleep before UART TX
(FIFO or shift register) becomes empty. This CL fixes it by:
(1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called.
(2) Enable the NXMIP (No Transmit in Progress) interrupt.
(3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is
set.
This fix only needs to apply to NPCX7 chips which have UART FIFO support.
BRANCH=none
BUG=b:137143640
TEST=No error for "make buildall"
TEST=run 10 iterations of uart_stress_tester on yorp with command:
./util/uart_stress_tester.py /dev/ttyUSB2 -t 360;
make sure no character lost in each iteration as below:
...
INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART
INFO | UartSerial| EC | Ready to test
INFO | ChargenTest | Ports are ready to test
INFO | ChargenTest | Test starts
INFO | UartSerial| EC | Test thread starts
INFO | UartSerial| EC | Test thread is done
INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %)
INFO | ChargenTest | PASS: lost 0 character(s) from the test
INFO | ChargenTest | Test is done
Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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This should apply to all Kranes.
BUG=b:131081336
TEST=factory accelometer test
BRANCH=master
Change-Id: I44313d73bf6dd484101973e153c6b5209128a789
Signed-off-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1687832
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Confirmed by HW eng, this fix should apply to all board revisions.
BUG=b:133655155
TEST=none
BRANCH=master
Change-Id: I20a72ec744c6d6fbf08d0cf57ad78902e35c2df9
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1679784
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Yilun Lin <yllin@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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Support an argument pol0/pol1 to the console command to change the CC
polarity. When CC polarity change, apply the Rd/Rp to the proper CC line
and fake the proper CC voltage.
BRANCH=servo
BUG=b:136014621
TEST=Tried the console commands:
* Typed "cc src pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946
* Typed "cc src pol1" on servo v4 and checked DUT detected CC2:
Port C0 CC2, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946
* Typed "cc snk pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608
* Typed "cc snk pol1" on servo v4 and checked DUT detected CC2:
Port C0 CC2, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608
* Typed "cc srcdts pol0" on servo v4 and checked DUT detected CC1:
Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x14946
* Typed "cc srcdts pol1" on servo v4 but resulted some hard reset issue
during PD negotiation; need further investigation.
Port C0 CC2, Ena - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x10608
TEST=Ran the entire PD FAFT suite passed on both CC polarities.
Change-Id: I7f983179b13e87a219bd26fe3665446df36de86e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693843
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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firmware_PDVbusRequest forces servo v4 to different max_voltage
limits to verify the PD negotiation. Add the firmware support for it.
The console command usbc_action is the same as Plankton. So the test
side doesn't need any change.
BRANCH=servo
BUG=b:134700685
TEST=Tried usbc_action command and ran firmware_PDVbusRequest passed.
Change-Id: I5f05d73d9a2f92fe26514285e7c251e9fa27aba8
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686221
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BRANCH=none
BUG=none
TEST=verified markdown rendering
Change-Id: Ibef37a8f9818d2cb9e2bd50097819d2c6a646398
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1713737
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The following bug
https://buganizer.corp.google.com/issues/136002955
indicates after my initial move of snowball to use the
linker map instead of hard defined addresses that
0xFF801E80 was reading back as all zeroes.
The change that was made for this is
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
I double checked the map files and everything looked
good. For some reason using the linker to map the location
of this structure, the system does not run properly.
If I remove the link map placement of this structure
then the issue goes away. I looked at how aon_share
was placed at the specific address in AON memory and
this CL is doing the same thing and it is working.
I think this is the way we should keep this fix and not
try to get the linker map to place this structure where
we want it.
BUG=b:136002955
BRANCH=none
TEST=make buildall -j
TEST=verify soft reboot does not indicate power reset
Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Support hooking on AC_CHANGE when external power plugged and unplugged.
BUG=b:137903027
TEST=on kukui, shutdown -h now, and plug power adapter on kukui, and see
battery LED turning on immediately, and also see console prints
"AC on"
BRANCH=master
Change-Id: I6e2704cfe2d3ed09cc6e1c76b8d03a5030a400ed
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1712400
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
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The extentions were added to make the compiler perform most
of the verification that the conversion was being done correctly
to remove 8bit addressing as the standard I2C/SPI address type.
Now that the compiler has verified the code, the extra
extentions are being removed
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
TEST=verify sensor functionality on arcada_ish
Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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* Update **test** directory description to README.md.
* Add ** fuzz** directory description to README.md.
* Add unit test and fuzzer make targets to `make help`
* Change showboards to print-boards to be more consistent
* Change showboards to use auto pretty print
* Add print-tests, print-host-tests, and print-host-fuzzers
This is necessary to remove the ambiguity about what a special
name is for a given unit test.
Documentation Story:
The idea is to give a brief overview of what the test and fuzz
directories are in README.md.
README.md also mentions you should see `make help` for more detail.
Running `make help` shows you more general test/fuzz commands,
including the print-* commands.
Running the print-* commands show you exact target names for all
possible unit/fuzz test (both the build-only and run target names).
BRANCH=none
BUG=none
TEST=make help
TEST=make print-tests
TEST=make print-host-tests
TEST=make print-host-fuzzers
TEST=make print-host-fuzzers | cat
TEST=make print-boards
TEST=make print-boards | cat
TEST=make buildall -j
Change-Id: I34b68196ac635ba71a1d45ceb5d35a3b36fd129f
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684714
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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For the normal lab use, emulating a sink has no PD comm, like a passive
hub. For the PD FAFT use, we need to validate some PD behavior, should
support sink roles with PD comm enabled. Two new roles "pdsnk" and
"pdsnkdts" are introduced.
BRANCH=servo
BUG=b:134700685
TEST=Typed "cc pdsnk" or "cc pdsnkdts" can transit the DUT port to
the PD state "SNK_READY", instead "SNK_DISCOVERY".
Change-Id: If6a7c39cd296986b8b28de1c1fbe66ee8438c709
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682920
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Support a new flag to enable DRP. The do_cc() function becomes having 4
arguments. So change to merge them into a single cc_config with
different bit masks.
For the force_source or force_sink role, we explicitly set the the Rp
or Rd resistors on CC lines. But for DRP role, the Rp/Rd toggling is
controlled by the PD state machine. So don't set any CC pull resistor
for DRP.
Support an "on" option in "cc" command to restore the previous role
before emulating detach.
Add "usbc_action drp" to toggle the DRP state, which is compatible with
Plankton.
BRANCH=servo
BUG=b:135691171
TEST=Ran the firmware_PDTrySrc test passed, and not break all the
existing PD FAFT tests.
Change-Id: I3b90611c9840f502e496c42f80354e7ee002f96e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682919
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Update the PD policy and comments:
* Only allow data role swap on DUT port;
* Remove the dts mode condition to initiate a data role swap
(not necessary to limit it to dts mode).
BRANCH=servo
BUG=b:135691171
TEST=Checked the CHG port is always UFP.
TEST=Checked the DUT port is SRC/UFP, a data role swap happened (but
it was initiated by DUT).
Change-Id: I668703209301a9542e94768f31f6ce8e2d9eb0f4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The pd_config_init() does two things:
* pd_tx_init() to init the GPIO MODULE_USB_PD;
* pd_set_host_mode() to set CC pull resistors.
The pd_config_init() is called on PD phy init hook.
For setting CC pull resistors, calling pd_set_host_mode() is enough.
Don't need to reinit GPIO MODULE_USB_PD.
BRANCH=servo
BUG=b:135691171
TEST=Set "cc" role to "src", "snk", "srcdts", "snkdts", and "off".
TEST=Unplugged and replugged the CHG port cable.
Change-Id: I1e783dfa5da4f8e8f1d9d591818eb1128b7a8caa
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682917
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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When the requester does not expect the chip information from the live
target, return the hardcoded vendor and product id.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=Boot to ChromeOS
Change-Id: I74affb00951411a3483258a8db165038e7eb683f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617894
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as
follows:
0 -> Return hard-coded info for Vendor ID/Product ID and cached info for
the Firmware Version
1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version
Also rename the 'renew' field to 'live' to match the new semantics.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS.
Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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The octopus baseboard should only declare the sensor CONFIG_ values
if we didn't define the NO_SENSORS variant
BUG=b:137758297
BRANCH=None
TEST=buildall
Change-Id: I32443f08ee7d1412b425bd55c8c40d67f22ef089
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706687
Reviewed-by: Enrico Granata <egranata@chromium.org>
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Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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In servo v4 hardware logic, both CC lines are wired directly
to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
and make the voltage high as vRd-3.0, which makes the PD
state mess up. As the PD state machine doesn't handle this
case. It assumes that CC2 is separated by a Type-C cable,
resulting a voltage lower than the max of vRa.
It fakes the voltage within vRa so the PD state machine
checks the value as expected.
This is an issue only happening on servo v4 as it wires both
CC lines to DUT.
BUG=b:134700685
BRANCH=servo
TEST=Servo v4 as snk, verified the CC2 is sensed vRa, i.e.
the output "CC1:0" (TYPEC_CC_VOLT_OPEN), instead of "CC1:7"
(TYPEC_CC_VOLT_SNK_3_0).
2019-06-18 15:05:47 > cc snk
2019-06-18 15:05:50 cc: on
2019-06-18 15:05:50 dts mode: off
2019-06-18 15:05:50 chg mode: off
2019-06-18 15:05:50 chg allowed: off
2019-06-18 15:05:50 > C1 st2 SNK_DISCONNECTED
2019-06-18 15:05:50 C1 st3 SNK_DISCONNECTED_DEBOUNCE
2019-06-18 15:05:50 C1 st5 SNK_DISCOVERY
2019-06-18 15:05:51 > tcpc 1 state
2019-06-18 15:05:53 Port C1, Dis - CC:2, CC0:6, CC1:0
2019-06-18 15:05:53 Alert: 0x00 Mask: 0x007d
2019-06-18 15:05:53 Power Status: 0x48 Mask: 0x00
TEST=Ran the PD FAFT test firmware_PDConnect passed.
Change-Id: I10f1ffe80768100ee3ed4c374598df7c2f9a8d05
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch let the tester exit with an error code on test failure.
It would make easy the future autotest to detect a failure.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
[before patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
...
$ echo $?
0
[after patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
Error: Test failed for losing 144888 character(s)
...
$ echo $?
1
$ ./util/uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
Error: /dev/ttyUSB1 does not exist.
$ echo $?
1
Change-Id: I210efd4ad7fdb8eb612206624eda6c39c5bb3b1c
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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During initialization, uart_stress_tester checks each of ports
exists, and raises an error if not.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSBX -t 120
Error: [Errno 2] No such file or directory: '/dev/ttyUSBX'
$ ./util/uart_stress_tester.py ./util/uart_stress_tester.py -t 120
Error: ./util/uart_stress_tester.py is not a character device.
Change-Id: I989a9e767796b04b059861aea2a3412877c1d739
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706626
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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According to the DisplayPort Alt Mode on USB Type-C specification, if
the DisplayPort Source device does not need to maintain HPD connectivity
information prior to entering a low power state, the device shall exit
the DP Alternate Mode. Previously, we were always entering DP Alt Mode
regardless of the SoC state. When we are shutting the device down to S5
or G3, there's no need to monitor the HPD connectivity information.
This commit simply does not enter DP Alt Mode when the SoC is off.
BUG=chromium:927636
BRANCH=firmware-nocturne-10984.B
TEST=Flash nocturne, shut DUT down to S5/G3, plug in a USB-C monitor
that can also act as a Source, verify with PD analyzer that DUT does not
Enter DP Alt mode, boot system up, verify that external display works.
Change-Id: I2ad3619cabeae5d90e8af1bfa9cab67452d9fc16
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1450815
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This patch adds a usual inclusion guard (#ifdef __CROS_EC_*_H) and
fixes API descriptions.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I96149cfe76cff7ab85be4785252a600b565e4a92
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696913
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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Markdown docs don't affect the build. Make presubmit slightly nicer.
BUG=none
BRANCH=none
TEST=run util/presubmit_check.sh after committing docs/ only changes
Change-Id: I273dd071e3cf5e859a0a4f0f97e9011cc4391f0d
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706613
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The power rail for the 5V used for sourcing is not available while the
chipset is off. Therefore pd_set_power_supply_ready() should return an
error if chipset is off.
BUG=b:118646299
BRANCH=firmware-nocturne-10984.B
TEST=Flash nocturne; plug in a USB Type-C ethernet adapter, run
`dut-control power_state:rec` and verify that VBUS is present at the
insert screen.
TEST=Repeat the above test 20 times and verify that it always succeeds.
Change-Id: Ie675d862dfbbe1e1ce08f6b203008ee784eb8ede
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/1307699
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit b6db88f25366a4519ad45d4b54e91cb40e7ea7fb)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1708266
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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In EMULATED_IRQ_EVENT mode, we try to estimate the time between a read
request and data ready. If the estimated time is shorter, an error
message is printed to the console on every retry.
On Kukui, this caused ec console spamming one line per second.
Change the behavior to print only when returning error.
No need to adjust the estimate time because one retry per read is still
good enough.
BUG=b:137345336
TEST=manually, verify that error message disappeared.
BRANCH=None
Change-Id: Ie85e8f1a80ea36ca5c50f57a19eba35f3f79f86d
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697889
Tested-by: Fei Shao <fshao@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Setting Type-C Port1 controller register 0xE8 (High Speed Signal
Detector threshold adjustment) to 0x80 (-25%).
BUG=b:136531130
BRANCH=master
TEST=Manual
Check Type-C Port1 register 0xE8.
Change-Id: I5957fcd3389296500992ea3075dcde4a3b690f98
Signed-off-by: Barney_Liao <barney_liao@pegatron.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703724
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch addresses a few issues with the current formatter.
The major points are as follows:
1. Cannot specify precision 0 (truncate all) for string or hexdump
2. Forced safe precision for malformed strings
3. No padding when using hexdump
4. Bad error EC_ERROR_INVAL in vsnprintf
5. Documentation errors
For (1), no piece of code explicitly sets the precision to 0 in
order to invoke the default behavior, which is currently no
precision limit.
You can check using the following grep line:
grep -rI '%[\*0-9]\{0,20\}\.0\{1,20\}[a-zA-Z]'
However, there are many cases where the precision is used to limit
the character output (as it should be).
grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]'
There are many more instances that use variable precision without
checking if the precision is zero. One of which is the following:
crrev.com/4a4e2c71a0f6aaa50e0728922f84a7d54c14380a/test/host_command_fuzz.c#116
https://clusterfuzz.com/testcase-detail/5699023975088128
Our current implementation will insert ERROR and stop processing,
if a precision of zero is detected when using the hexdump flag.
This results in a badly formatted console line or runtime string,
when the intended behavior would be to simply read no bytes.
In the aforementioned fuzzer case, outputting ERROR triggers
a false positive.
Our printf should handle explicit zero precision similar to
stdlib's printf, which means truncating all the way to zero
positions, if specified.
For (2), our current implementation uses strlen to identify the
length of the input string, regardless of the set precision.
Since this is an embedded platform, we should use strnlen to
impose safe limits, when a precision is specified.
For (3), our implementation should support padding and adjusting
of all formatter types, since that is a primary feature of a
printf formatter.
The remaining commented code highlights odd behavior that should
be fixed at some point, but is not critical.
BUG=chromium:974084
TEST=Checked for any format lines that rely on a set precision of 0
grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]'
TEST=make run-printf V=1
BRANCH=none
Change-Id: I897c53cce20a701fcbe8fb9572eb878817525cc3
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1659835
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This adds fake SPI Master and TRNG support to the
host target.
This change also adds the missing emulated gpio
interface function.
Although general purpose, these changes are setup for
allowing fuzzing of the FPMCU specific host commands.
Thus, they do not impact any outstanding code.
BRANCH=none
BUG=b:116065496
TEST=make buildall -j
Change-Id: Icfc40e7bf8ee421a4c3ad15377fd56ae68c763d7
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684223
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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By fixing the bug(b/136282898) to allow MKBP events to wake the system
in suspend, all MKBP events would wake the system which goes against our
chrome OS wake sources spec. By defining CONFIG_MKBP_EVENT_WAKEUP_MASK,
nocturne will not wake on any MKBP event.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, suspend DUT, plug in powered charge-thru
hub w/ an external display connected, verify that DUT does not wakes up
and display is not shown.
Change-Id: I0810d0ea625689ee39f0e52b62a8ee7c00c49aad
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685788
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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Previously, the EC could notify the AP that it had entered into
DisplayPort Alternate mode by sending a MODE_CHANGE host event.
However, there was no mechanism to disable that functionality if desired
without effecting the other MODE_CHANGE events (i.e. - base
attach/detach). By changing the DisplayPort Alternate mode entry to an
MKBP event, we can have more granularity and only affect this single
event.
- This commit adds a new MKBP event, EC_MKBP_EVENT_DP_ALT_MODE_ENTERED.
- The commit also changes the DP AltMode entry notification from sending
a MODE_CHANGE host event to this new MKBP event.
BUG=chromium:786721
BRANCH=None
TEST=Build and flash nocturne, verify that system still wakes up on
DisplayPort Alternate Mode entry.
Change-Id: Ia5f294b26701c3c98c9b7f948fc693d26234c835
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685787
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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MKBP was recently refactored to offer choice in the MKBP notification
method. However, if a board is using a GPIO to notify the AP of a MKBP
event, and the AP cannot wake from the GPIO, the MKBP event cannot wake
the system up from suspend as is. This commit simply adds a new config
option, CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT such that MKBP events can
wake the system from suspend. Note that the board will have to add MKBP
events to the host event sleep mask in coreboot. Typically on ARM
devices, EC_INT_L is already a wake pin, but on Intel devices it is not;
there's actually a different pin, PCH_WAKE_L which is set via sending a
host event and wakes the system.
BUG=b:136272898,chromium:786721
BRANCH=None
TEST=Enable config option on nocturne, flash nocturne, suspend DUT,
verify that MKBP events can wake the AP.
Change-Id: If5026bfe3efacbc051f99a180e061c6fd679ce5a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685786
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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crbug.com/982442 requests a way for developers to enable tracing of
i2c commands when debugging. This adds a new debug feature, the
i2ctrace command, which provides that. The command is guarded by
CONFIG_I2C_DEBUG.
BUG=chromium:982442
BRANCH=none
TEST=enabled CONFIG_I2C_DEBUG on arcada_ish, made sure that command
functioned as it says on the tin
Change-Id: I9c762271237cbf131e5ef7c0f605c89af4f209fd
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699347
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Includes System Clock, Timer, Uart, Watchdog
Change-Id: I195059c87d97e70c6a134304143613b86b623e22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647741
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Jerry Bradshaw <jerry.bradshaw@maximintegrated.com>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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CONFIG_SMBUS is not used. Cleaning up the code by
removing this.
Added a comment to document the removal and why. This will
give a way to find the code if we ever needed to bring it back
BUG=chromium:982316
BRANCH=none
TEST=make buildall
Change-Id: I40703a95bc849538e1aee32f6f96beab811285bd
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704279
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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EAR (extended address register) is used to access addresses above
16MiB when 3-byte address mode is used. These two functions allow to
write to and read from EAR to set up what addresses to access in
3-byte mode. For example, for a 64MiB EEPROM:
EAR value Addresses to access
0 0x0000000 - 0x0FFFFFF
1 0x1000000 - 0x1FFFFFF
2 0x2000000 - 0x2FFFFFF
3 0x3000000 - 0x3FFFFFF
BUG=b:132252340
BRANCH=none
TEST=manual
Testing:
1. Writing to EAR returns successfully.
2. Writing different values to EAR, verify that accessing EERPOM
in 3-byte mode is to the correct address, e.g., when EAR=2,
accessing 0x0FFFFFF is actually to 0x2FFFFFF.
Change-Id: I2a8bde7fc4b9069afc80a81042fb47359bffa015
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688150
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Pai Peng <paipeng@google.com>
Commit-Queue: Pai Peng <paipeng@google.com>
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There is no room in the flash for both dcrypto tests and the TPM
library. Let's disable TPM function (and not link the library) when
the image is compiled with dcrypto tests included.
BRANCH=cr50, cr50-mp
BUG=b:137659935
TEST=verified that there is plenty of room for tests now:
$ make BOARD=cr50 -j -k CRYPTO_TEST=1 CR50_DEV=1
.
.
.
*** 8124 bytes in flash and 61564 bytes in RAM still ... in cr50 RO ***
*** 66100 bytes in flash and 6000 bytes in RAM still ... in cr50 RW ***
- building without CRYPTO_TEST=1 still produces a functional Cr50
image;
- when building with CRYPTO_TEST=1, the version string reflects it:
$ strings build/cr50/ec.bin | grep cr50_v | head -1
DBG/CT/cr50_v2.0.1776-46b015f6a
- CCD of the images built with crypto test enabled is fully
functional, in particular USB updates are operational.
Change-Id: Iae91ca36dc203301ac423fe048fc67eb44ef5de6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704608
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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Presently the CR50_DEV environment variable is overloaded, if its
value is a number exceeding 1, it enables inclusion in the image of
the dcrypto tests.
To make things cleaner let's use a separate environment variable to
add dcrypto tests to the image. Note that the tests still can not be
enabled, as they do not fit into the flash code space.
BRANCH=cr50, cr50-mp
BUG=b:137659935
TEST=verified that image building with CRYPTO_TEST=1 fails due to
exceeded code size.
Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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