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* gsctool: Add options to print out RLZ codesstabilize-11151.59.Bstabilize-11151.113.Bstabilize-11151.100.Brelease-R71-11151.BBob Moragues2018-11-051-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This RLZ code is used by cr50-verify-ro.sh. The RLZ code selects the verify_ro db to use. BUG=b:90495590 BRANCH=none TEST=gsctool -i -M; gsctool -i -M -t CQ-DEPEND=CL:1309453 Unit Test Rewults: localhost ~ # gsctool -i -M open_device 18d1:5014 found interface 3 endpoint 4, chunk_len 64 READY ------- BID_TYPE=4e425153 BID_TYPE_INV=b1bdaeac BID_FLAGS=00007f7f BID_RLZ=NBQS <-- CORRECT DUT RLZ localhost ~ # gsctool -i -M -t BID_TYPE=58574a45 BID_TYPE_INV=a7a8b5ba BID_FLAGS=00007f7f BID_RLZ=XWJE <-- CORRECT Test Device RLZ localhost ~ # Change-Id: I12fbca6885e3a1453544a1d379ad12ef3f6fd290 Signed-off-by: Bob Moragues <moragues@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1309454
* gsctool: add machine output support (-M) to chip board ID (-i, -O)Wei-Cheng Xiao2018-11-054-16/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now gsctool can print out GSC board ID in a machine-friendly way. This allows other programs (e.g., debugd) to parse the output. This is the final CL that adds machine output support to gsctool during verify_ro migration. BRANCH=none BUG=None TEST=manually run gsctool -M -i and gsctool -O verify_ro.db -M on a soraka device connected with a naultilus and check the board ID part in the outputs. Sample output (the board ID part is identical in the outputs of both commands): BID_TYPE=5a534b4d BID_TYPE_INV=a5acb4b2 BID_FLAGS=00007f80 CQ-DEPEND=CL:1309052 Signed-off-by: Wei-Cheng Xiao <garryxiao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1286312 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Cheng Xiao <garryxiao@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Change-Id: Ia275806672c08841c5b5fcc7758d8e0c777b3fc9 Reviewed-on: https://chromium-review.googlesource.com/c/1309453 Tested-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Commit-Queue: Bob Moragues <moragues@chromium.org>
* gsctool: add machine output support (-M) to FW image info (-b)Wei-Cheng Xiao2018-11-051-91/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now can print out FW versions and board ID in the image in a machine-friendly way. This allows other programs (e.g., debugd) to parse the output. Add equality check to the firmware versions and board IDs in slot A and B. Now gsctool prints out an error message to stdout if the contents do not match; otherwise, it prints out only one copy of the contents instead of two. Sample runs: $ gsctool -b cr50.bin.prod RO_A:0.0.10 RW_A:0.3.10[ABCD:00000000:00000000] $ gsctool -b cr50.bin.prod -M IMAGE_RO_FW_VER=0.0.10 IMAGE_RW_FW_VER=0.3.10 IMAGE_BID_STRING=ABCD IMAGE_BID_MASK=00000000 IMAGE_BID_FLAGS=00000000 BRANCH=none BUG=None TEST=manually run gsctool -M -b cr50.bin.prod and gsctool -b cr50.bin.prod on a soraka device connected with a naultilus. Outputs are as the examples above. CQ-DEPEND=CL:1309051 Signed-off-by: Wei-Cheng Xiao <garryxiao@chromium.org> Change-Id: I1c4c5110fe236debb93b3db118abb4c922b98bdf Reviewed-on: https://chromium-review.googlesource.com/c/1309052 Tested-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Wei-Cheng Xiao <garryxiao@chromium.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Commit-Queue: Bob Moragues <moragues@chromium.org>
* gsctool: add a cmd line option -M to gsctool to allow machine-friendly outputs.Wei-Cheng Xiao2018-11-051-8/+73
| | | | | | | | | | | | | | | | | | | | | | | | | Add the option's support to remote firmware version output (-f). This allows other programs (e.g., debugd) to parse gsctool outputs without worrying about any future updates on current human-readable outputs. BRANCH=none BUG=None TEST=manually run gsctool -f -M on a soraka device connected with a nautilus. Sample output: RO_FW_VER=0.0.10 RW_FW_VER=0.3.10 Signed-off-by: Wei-Cheng Xiao <garryxiao@chromium.org> Change-Id: Ic6514a191b379d05acf2656e5e395d82086d93cd Reviewed-on: https://chromium-review.googlesource.com/1278073 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> (cherry picked from commit 974208f124b8272607f73f2d26244fbc9258f4c9) Reviewed-on: https://chromium-review.googlesource.com/c/1309051 Reviewed-by: Bob Moragues <moragues@chromium.org> Tested-by: Bob Moragues <moragues@chromium.org> Commit-Queue: Bob Moragues <moragues@chromium.org>
* delan: Add new grunt-family board.Edward Hill2018-10-118-0/+605
| | | | | | | | | | | | | | | | | Add Delan board. Initially just a copy of Liara. BUG=b:117173908 BRANCH=grunt TEST=build Change-Id: I7fda1c58ad6b61246a1d04153470a6a08a54d242 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/1269644 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> (cherry picked from commit cecced7d3ae46a19dc7a2199c0a15d3763701b39) Reviewed-on: https://chromium-review.googlesource.com/1277614 Commit-Ready: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* cr50: CCD Info indicates whether all CCD capabilities are default.Namyoon Woo2018-10-113-3/+41
| | | | | | | | | | | | | | | | | CR50 provides whether CCD capabilities are default or not. Factory process can utilize this value instead of CCD cap bitmap information. Users can use either 'gsctool -I' or CR50 console command 'ccd'. BRANCH=cr50_tools BUG=b:117200472 TEST=manually set and clear the password using gsctool -a -F and check the result of gsctool -I. Change-Id: Ic6be2ce880476c3a73150fe0e29007dd6a7e328f Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1272190 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Ampton: config the charger ic VARIANT_OCTOPUS_CHARGER_ISL9238James_Chao2018-10-111-1/+1
| | | | | | | | | | | | | | | BUG=b:117470429 BRANCH=master TEST=build Change-Id: I4a9f8449fb859eb843549d6d7f0574307df6e7ef Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1275467 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* tpcp: update comments for CC status for clarityJett Rink2018-10-111-5/+5
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I5c5c109a8cda96f62bac59a499ca619348e5e922 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1276705 Reviewed-by: Edward Hill <ecgh@chromium.org>
* cr50: minor code revision with macros regarding CCD capabilities.Namyoon Woo2018-10-113-9/+22
| | | | | | | | | | | | | | | | | | | | Defined "Number of bits in CCD cap expression", "Bitmask for a CCD cap expression", and "Number of CCD cap expressions in a Byte," and replaced constant uses with macros in CR50 and gsctool codes. No binary size changes in either CR50 or gsctool. BRANCH=cr50_ccd BUG=none TEST=manually tested with gsctool -I and CR50 console command 'ccd'. Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: If91305090444395b6a938f920f4e47e2acbba886 Reviewed-on: https://chromium-review.googlesource.com/1274007 Commit-Ready: Namyoon Woo <namyoon@chromium.org> Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* touchpad_st: touch_slot should be reset to 0Wei-Han Chen2018-10-111-0/+1
| | | | | | | | | | | | | | | | When we recover from touchpad error by resetting the touchpad, after TP reset, "touch_slot" should be reset to 0. BRANCH=nocturne BUG=b:117568885 TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I4dad1b2ad28885e376023d5e5274485aaa852ac3 Reviewed-on: https://chromium-review.googlesource.com/1274685 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/stm32/usb_hid_keyboard: Reload keyboard endpoint on resetNicolas Boichat2018-10-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | After the USB device is reset, force sending the keyboard data at least once to make sure the host is aware of the curreny key/switches status. In particular, this is necessary for the host to be aware that we are in tablet mode on host boot (this is not a problem on attach, as other routines in the EC init sequence cause the endpoint to be loaded anyway). BRANCH=nocturne BUG=b:117439202 TEST=Reboot nocturne with whiskers attached in tablet mode, see that nocturne is still in tablet mode after reboot: evtest --query /dev/input/event6 EV_SW SW_TABLET_MODE; echo $? => 10 Change-Id: I4b0e20a9f78c5262d7effd8bd37ace0d033b3f5a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1270297 Reviewed-by: Dmitry Torokhov <dtor@chromium.org>
* nocturne: Only advertise Rp-1.5A for sourcing.Aseda Aboagye2018-10-101-1/+0
| | | | | | | | | | | | | | | | | | BUG=b:117566802 BRANCH=firmware-nocturne-10984.B TEST=Flash nocturne; verify that 5V/1.5A SourceCaps are sent. Verify that Rp1.5A is advertised. Change-Id: Ibc5a45fb15ed5f50ac8609985c4de764c2e59503 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1274018 Reviewed-by: Benson Leung <bleung@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit d118ba10a0d5dfae118e85a898f2b467b41e79ff) Reviewed-on: https://chromium-review.googlesource.com/1274906 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* octopus: enable a1 redriver in S3+Jett Rink2018-10-101-0/+78
| | | | | | | | | | | | | | | | | | | | With the upcoming hardware changes, we need to ensure that TypeA port 1 has power during S3+. Previously other hardware signals controlled the power. We still want to optimize this signal to turn off power in S3/S0ix if we know that nothing is plugged in the port. BRANCH=none BUG=b:111406013 TEST=flashed on meep without issue, however the actually GPIO toggle is still untested since we don't have hardware that needs this yet. Change-Id: I99c548c317a3ec77fef8ece0cc710d072d5b862e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1262108 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Revert "tcpc: Check battery present to enable PD_SUSPEND"Wai-Hong Tam2018-10-101-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1028c039fb14ddf523bcf0786ed39e8a2c57648f. Reason for revert: The original remaining capacity check should work on the no-battery case. Don't need an extra check. Original change's description: > tcpc: Check battery present to enable PD_SUSPEND > > When doing TCPC firmware update, it suspends the PD port. There is > a check to make sure if the battery level is enough for the update > process. But when no battery presents, it still does the update. > Should also check the battery present. Otherwise, the update > process will make the power lost and result a reboot loop. > > BRANCH=none > BUG=b:117498337 > TEST=Do TCPC firmware update on the charging port and no battery: > Saw AP console: > Protect aux fw 0 > Update aux fw 1 > ps8751.1: PD_SUSPEND busy! Could be only power source. > Protect aux fw 1 > Saw EC console: > [9.165306 C1: Cannot suspend for upgrade, no battery!] > > TEST=Do TCPC firmware update on the charging port and battery plugged: > Saw AP console: > Protect aux fw 0 > Update aux fw 1 > ps8751.1: found SPI flash ID 0x1c11 > ps8751.1: erased 20KB in 434ms > ps8751.1: verified 0KB in 0s > ps8751.1: programming 20KB... > > Change-Id: I4ed3929d3234d115596f04245e698de8b1b3e662 > Signed-off-by: Wai-Hong Tam <waihong@google.com> > Reviewed-on: https://chromium-review.googlesource.com/1271257 > Reviewed-by: Furquan Shaikh <furquan@chromium.org> BRANCH=none BUG=b:117498337 TEST=Triggered TCPC firmware update on the charging port and no battery. Checked the update is not allowed and EC console showed: [9.284003 C0: Cannot suspend for upgrade, not enough battery (0mAh)!] Change-Id: I6a13324996b8fa535cd1035a893b1af01fe96a5c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1274006 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* touchpad_st: fix bug in dump_memoryWei-Han Chen2018-10-101-1/+1
| | | | | | | | | | | | | | | | in dump_memory, rx_len includes DUMMY_BYTE, but it should not be counted when we are printing. BRANCH=nocturne BUG=b:117398324 TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I9810e97b1fb0ce94973fc24963d6c6ea601759be Reviewed-on: https://chromium-review.googlesource.com/1267875 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* DragonEgg: Rely on BATT_PRES_ODL for battery_hw_presentScott Collyer2018-10-101-3/+11
| | | | | | | | | | | | | | | | | | P0 boards required a FW workaround for the battery present signal as it always read high. Starting with P1, this issue has been fixed in HW. This CL relies on the board id to determine which method to use for determing battery presence. BUG=b:117120739 BRANCH=none TEST=Tested on P0, verified that battery charging still works. Change-Id: I28eeca9f27244c6cac54ce032caf7c1073a110c2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1256183 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* DragonEgg: Add support to read board version from GPIO strappingsScott Collyer2018-10-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | In preparation for P1 boards, this CL adds support to report board version from gpio strapping pins. BUG=b:117120739 BRANCH=none TEST=Tested on DragonEgg P0 board: ver Chip: ite it8320 dx Board: 0 RO: dragonegg_v2.0.66-cd7027af7 RW: dragonegg_v2.0.66-cd7027af7 Build: dragonegg_v2.0.66-cd7027af7 2018-10-01 16:03:27 scollyer@scollyer.mtv.corp.google.com Change-Id: I62063d1c2e3dd685cc74beb42c962d112b9de4ae Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1256182 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* usb_i2c: extend protocol to allow longer writesVadim Bendebury2018-10-102-29/+61
| | | | | | | | | | | | | | | | | | | | | It is necessary to be able to send longer than 255 byte packets over the USB I2C bridge. This patch introduces a backwards compatible protocol extension to the to allow that. Namely, the top 4 bits of the byte previously used as the port number are now used as the top 4 bits of the 12 bit write counter field. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=tested along with patches modifying Cr50 and iteflash for operating over CCD. Verified that the ITE EC programming requiring 256 byte write transactions succeeds. Change-Id: I21475c8d87a6a858ff9ad96dae87388604bbbf2d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1256059 Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* atlas: run the TCPC I2C busses at 1MHzCaveh Jalali2018-10-101-2/+2
| | | | | | | | | | | | | | | | | | | this bumps up the I2C bus going to the TCPCs from 400KHz to 1MHz. we do see improvement in the firmware update speed, but definitely not by 2.5x. BUG=b:117525129 BRANCH=none TEST=updated ps8751 firmware on atlas in combination with other patches to enable TCPC firmware update Change-Id: I9cad1cbe8e5bf2523c9e132aa99c25957f510b4e Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1272875 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* tcpc: Check battery present to enable PD_SUSPENDWai-Hong Tam2018-10-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing TCPC firmware update, it suspends the PD port. There is a check to make sure if the battery level is enough for the update process. But when no battery presents, it still does the update. Should also check the battery present. Otherwise, the update process will make the power lost and result a reboot loop. BRANCH=none BUG=b:117498337 TEST=Do TCPC firmware update on the charging port and no battery: Saw AP console: Protect aux fw 0 Update aux fw 1 ps8751.1: PD_SUSPEND busy! Could be only power source. Protect aux fw 1 Saw EC console: [9.165306 C1: Cannot suspend for upgrade, no battery!] TEST=Do TCPC firmware update on the charging port and battery plugged: Saw AP console: Protect aux fw 0 Update aux fw 1 ps8751.1: found SPI flash ID 0x1c11 ps8751.1: erased 20KB in 434ms ps8751.1: verified 0KB in 0s ps8751.1: programming 20KB... Change-Id: I4ed3929d3234d115596f04245e698de8b1b3e662 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1271257 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Octopus: add reset logic for C0 TCPCDiana Z2018-10-097-5/+36
| | | | | | | | | | | | | | | | | This change adds a call to the C0 TCPC reset for standalone TCPC boards which have that pin hooked up in hardware, and adds the GPIO as unimplemented for boards which do not have this yet. BRANCH=None BUG=b:112756630 TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset, then verified that charging on C0 worked. Also imaged yorp proto 2 and rebooted, verifying C0 reset was not attempted. Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257647 Reviewed-by: Jett Rink <jettrink@chromium.org>
* touchpad_st: decide if full init is required by cx versionWei-Han Chen2018-10-091-5/+47
| | | | | | | | | | | | | | BRANCH=nocturne BUG=b:117203130 TEST=on whiskers: downgrade to v18, upgrade to v25, full init is triggered Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I74582aba181dab31eede1193b400abfc847c1151 Reviewed-on: https://chromium-review.googlesource.com/1258373 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* touchpad_st: refactor to support panel initializationWei-Han Chen2018-10-091-20/+24
| | | | | | | | | | | | | | | | | | | | | | After ST firmware update, there are two ways of initialization: 1. Panel initialization 2. Full panel initialization Full panel initialization is only required if CX table format is changed. In the future, we will track versions of CX table format, and only request full initialization if required. BRANCH=nocturne BUG=b:117203130 TEST=on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I05dc2203213606addb27fd03f1c9ff937e4941f0 Reviewed-on: https://chromium-review.googlesource.com/1258691 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* touchpad_st: make panel initialization synchronousWei-Han Chen2018-10-092-31/+40
| | | | | | | | | | | | | | | | the entire process would take up to 2 seconds. CQ-DEPEND=CL:1264236 BRANCH=nocturne BUG=b:117203130 TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I0cdcdb8caf3b1d9cf6a5787b93bf8cdb13832a74 Reviewed-on: https://chromium-review.googlesource.com/1264237 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Liara: Correct LEDs color of ectoolRuby Lee2018-10-093-14/+14
| | | | | | | | | | | | | | | | | | | The LED colors of Liara are White and Amber. This patch is for ectool led command, which is used to test basic LED connectivity. BUG=b:117129402 BRANCH=none TEST=Run 1. ectool led power white=0 2. ectool led power white=100 3. ectool led power amber=0 4. ectool led power amber=100 Change-Id: I9b8c6f1ee9c2e676708de471a674cef0e2fb056e Signed-off-by: Ruby Lee <ruby_lee@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1267879 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
* rammus: Fix power leakagemichael_chen2018-10-092-3/+10
| | | | | | | | | | | | | | | | | | | | | | | Modify PMIC and GPIO setting to fix power leakage. Dependent on EE request: 1. Init PMIC Discharge control register. 1.1. Discharge control register 1 (0x3C) = 0x00. 1.2. Discharge control register 2 (0x3D) = 0x55. 1.3. Discharge control register 3 (0x3E) = 0x44. 1.4. Discharge control register 4 (0x3F) = 0x04. 2. Remove gpio "TP_INT_CONN" GPIO_PULL_UP configuration. BUG=b:117194355 BRANCH=ToT TEST=Manual EE measure power and check it is improve. Change-Id: I8b0e5ff479fee0ebcc26e9e57073ec6b5fc8868f Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com> Reviewed-on: https://chromium-review.googlesource.com/1253369 Commit-Ready: michael chen <michael5_chen@pegatroncorp.com> Tested-by: michael chen <michael5_chen@pegatroncorp.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* atlas: add internal pullup to unused pinCaveh Jalali2018-10-091-0/+1
| | | | | | | | | | | | | | | | | | unused pins should be configured with internal pullups to save power. this adds GPOB6 (TP32) to our list of unused pins. BUG=b:75070158 BRANCH=none TEST=boots on atlas, no ill effects Change-Id: Ie0bbce30881e0ea77284570de48c7adc4750ba95 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1269646 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* atlas: fix chip variant configCaveh Jalali2018-10-091-1/+1
| | | | | | | | | | | | | | | | | | | | this updates the EC chip variant to the one actually used on atlas. saw an interesting note in https://b.corp.google.com/issues/117139495#comment22 BUG=b:75070158 BRANCH=none TEST=boots on atlas, no ill effects Change-Id: I288ab5e58f5247541ea6ab19239f87be52e39ce0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1269645 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cr50: rename a power-button press ISR.Namyoon Woo2018-10-081-3/+3
| | | | | | | | | | | | | | | crrev.com/c/1192691 added power_button_release_enable_interrupt() but didn't rename power_button_enable_interrupt(). This CL renames one of them to keep them symmetric. BRANCH=cr50 BUG=b:37351386 TEST=none Change-Id: I96a7705ba2684b26410618f177a95201d2ee0683 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1268856 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Ampton: confirm thermistor partsDiana Z2018-10-081-1/+0
| | | | | | | | | | | | | | | Confirmed that Ampton is using 4050b thermistors (as we'd previously guessed), so removing TODO BRANCH=None BUG=b:115502220 TEST=builds Change-Id: Ie037eba542ae50cf1f9fa1911e9c33fb839e53dd Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1265064 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* intel_x86: Clear SCI/SMI masks only after host enters S0ixFurquan Shaikh2018-10-081-42/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CL:1099968 cleared SCI/SMI masks on receiving host command indicating entry into S0ix. On the other hand, wake mask is programmed only after host actually enters S0ix based on the EC power state machine. However, if the host actually takes a long time to suspend, then it leaves a wide window open where none of the masks are programmed and hence user events like lidopen could get dropped. This change updates the behavior to ensure that SCI/SMI masks get cleared only after power state machine actually enters S0ix based on the SLP_S0 signal. This action is not done as part of a suspend hook because other hooks can result into host events getting set that can trigger SCI/SMI thus leading to the original problem of EC not going into low power idle. Hence, SCI/SMI masks are cleared before any suspend hook is run. BUG=b:116540387 BRANCH=nocturne TEST=None Change-Id: I463c12febc49eefe852bd6e2c2535e96ad94ada0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1258564 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* iteflash: make use of 256 byte pages when programming over CCDVadim Bendebury2018-10-081-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It turns out the write command used by iteflash requires exactly one flash page to be written at a time. Recent usb_i2c protocol enhancement allow to pass up to 4K bytes in one transaction. This patch makes sure that when using CCD exactly one page at a time is programmed. Also, there is no point in trying to sync up more than 10 times. BRANCH=none BUG=b:75976718 TEST=verified that both servo controlled write, running $ make BOARD=dragonegg -j $ ./util/flash_ec --board=dragonegg and direct write over Cr50, running $ make BOARD=dragonegg -j $ cd ./build/dragonegg $ util/iteflash -c -e -w ec.bin succeed. Change-Id: I39c10389dfcccbb32252d8c42fc54bef96330d3a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1266677 Reviewed-by: Jett Rink <jettrink@chromium.org>
* iteflash: tweak verify_flash()Vadim Bendebury2018-10-081-3/+4
| | | | | | | | | | | | | | | | | | | | There is no point in comparing read buffer with the file contents in case flash contents read back failed. BRANCH=none BUG=none TEST=verified that running $ make BOARD=dragonegg -j $ ./util/flash_ec --board=dragonegg still succeeds when servod is running and the DUT is connected through the servo-v2 board. Change-Id: I8cd33140be4e834490b368df58aa2fd4546fe280 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1266676 Reviewed-by: Jett Rink <jettrink@chromium.org>
* iteflash: do not erase by defaultVadim Bendebury2018-10-082-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | It could be beneficial to be able to write flash without erasing it explicitly, for instance when programming a brand new chip, or when testing modifications of the iteflash utility. This patch makes sure that flash is erased only if '-e' command line parameter is present. The only place this utility is used by a script in Chrome OS codebase is flash_ec, it is being updated to maintain current behavior. BRANCH=none BUG=none TEST=verified that running $ make BOARD=dragonegg -j $ ./util/flash_ec --board=dragonegg still succeeds when servod is running and the DUT is connected through the servo-v2 board. Change-Id: Ic238b895ff3324cf8c646908610ea3103d2b78c7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1266675 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb-pd: allow a task to prevent TCPC LPMJett Rink2018-10-052-2/+33
| | | | | | | | | | | | | | | | | | | If a particularly low priority task (like hooks) wants to access the TCPC, then we do not want the LPM debounce to trigger in the middle of the communication sequence. This is especially a concern if the TCPC access is on debug registers that do not push out the LPM debounce deadline. BRANCH=none BUG=b:111406013 TEST=TCPC communication on meep is much more reliable with this change. TCPC will still go into low power mode after all tasks stop preventing LPM. Change-Id: I58cee8e202ced4085f131ff86dbda9d366e1dcca Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1262107 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* usb_i2c: provide a way to communicate non-i2c commandsVadim Bendebury2018-10-052-1/+48
| | | | | | | | | | | | | | | | | | | | | On some occasions there might be a need to request an action from the DUT which is related to i2c operations but can not be performed through an i2c transaction. For instance when one need to generate the sync sequence on the EC i2c interface before the EC can be programmed. This patch introduces a facility which allows to register a handler for commands sent on this special address which is picked at 0x78, which becomes 0xf0 during write transaction address cycle. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=tested along with the rest of the patches to trigger generating of the ITE EC debugger sync sequence. Change-Id: I269d4b8073b0d02f96ca526f221c02c38a036f3d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1214542 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* touchpad_st: log heatmap enable / disableWei-Han Chen2018-10-051-1/+4
| | | | | | | | | | | | | BRANCH=nocturne BUG=None TEST=manual on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I6d336d6a35671b59e0821ecd38bd481b7c4e80e0 Reviewed-on: https://chromium-review.googlesource.com/1258692 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* touchpad_st: update touchpad hung detection logicWei-Han Chen2018-10-051-8/+41
| | | | | | | | | | | | | | When idle count does not change, reset the touchpad if there are no fingers on touchpad. BRANCH=nocturne BUG=b:113315759 TEST=tested on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I8336bac2b31963e4c2cb671ced8502e6b176424d Reviewed-on: https://chromium-review.googlesource.com/1261615 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* grunt: Raise some task sizesJonathan Brandmeyer2018-10-054-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A rough early (and therefore liberal) analysis of grunt task stacks shows that some of them will overrun on some infrequently-executed debugging statements. Raise those task sizes to reduce the risk of an overflow. On Careena: Task: HOOKS, Max size: 320 (96 + 224), Allocated size: 800 Task: USB_CHG_P0, Max size: 548 (324 + 224), Allocated size: 672 Task: USB_CHG_P1, Max size: 548 (324 + 224), Allocated size: 672 Task: CHARGER, Max size: 844 (620 + 224), Allocated size: 928 Task: MOTIONSENSE, Max size: 588 (364 + 224), Allocated size: 928 Task: CHIPSET, Max size: 812 (588 + 224), Allocated size: 928 Task: KEYPROTO, Max size: 516 (292 + 224), Allocated size: 672 Task: PDCMD, Max size: 344 (120 + 224), Allocated size: 800 Task: HOSTCMD, Max size: 524 (300 + 224), Allocated size: 800 Task: CONSOLE, Max size: 484 (260 + 224), Allocated size: 928 Task: POWERBTN, Max size: 812 (588 + 224), Allocated size: 928 Task: KEYSCAN, Max size: 556 (332 + 224), Allocated size: 672 Task: PD_C0, Max size: 820 (596 + 224), Allocated size: 928 Task: PD_C1, Max size: 820 (596 + 224), Allocated size: 928 Task: PD_INT_C0, Max size: 296 (72 + 224), Allocated size: 672 Task: PD_INT_C1, Max size: 296 (72 + 224), Allocated size: 672 Note that '224' is conservative right now with CONFIG_FPU cleared on Grunt. BUG=b:116610278 TEST=buildall and analyzestack BRANCH=grunt Change-Id: Ibf721acc3250aa1d1195546e943031c5c8617b95 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1262101
* grunt: Add minimal analyzestack configurationsJonathan Brandmeyer2018-10-055-0/+6
| | | | | | | | | | | | | | | | | Considerably more work is needed to support the various driver indirections that Grunt is using. This is a 'liberal' analysis, in the sense that it is failing to include some driver paths in its stack consumption analysis. BRANCH=grunt BUG=b:116610278 TEST=make BOARD=grunt analyzestack. Change-Id: I6ff034935a749049b1ce6b544ea627b1772c7a80 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1262100 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* careena, liara, aleena: Remove motion sensing supportJonathan Brandmeyer2018-10-0411-42/+20
| | | | | | | | | | | | | | | | | | | | | | | | These members of the grunt family do not include any motion sensors. Remove them entirely, both to save space and to disable some factory tests. build/aleena/RW/space_free_flash grew by 12716 bytes: (62400 to 75116) build/aleena/RW/space_free_ram grew by 9888 bytes: (30272 to 40160) build/careena/RW/space_free_flash grew by 12864 bytes: (61664 to 74528) build/careena/RW/space_free_ram grew by 9856 bytes: (30304 to 40160) build/liara/RW/space_free_flash grew by 12724 bytes: (61364 to 74088) build/liara/RW/space_free_ram grew by 9856 bytes: (30272 to 40128) BRANCH=grunt BUG=b:115649135 TEST=boot Careena. Observe that `ectool motionsense` returns an INVALID COMMAND error, and that the EC console shows no attempt is made to communicate with the sensors. Change-Id: I322978fc80e36b999e77f9e3d54b175c6814fdcf Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1262099 Reviewed-by: Edward Hill <ecgh@chromium.org>
* FIXUP: mkbp: add support for board-specific host notificationEnrico Granata2018-10-042-8/+34
| | | | | | | | | | | | | | This patch improves naming and documentation for the functionality introduced in crrev.com/c/1247000 TEST=build BRANCH=none BUG=b:112366846, b:112112483, b:112111610 Change-Id: Iedd2fc5492a5d35fa9c2475fe248c5aa41e83bb0 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1258562 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* flash_ec: Disable the flashing-mode trigger for normal UART operationWai-Hong Tam2018-10-041-8/+28
| | | | | | | | | | | | | | | On some recent hardware, the flashing-mode trigger for CCD UUT mode, i.e. UART_EC_TX_H1_RX, affects UART operation when it is grounded. Should disable it, back to high-Z, for UART flashing. BRANCH=none BUG=b:117226655 TEST=Run flash_ec script over CCD and servo. Change-Id: I48e7d6c4142ede13da0911bf99b2f3081ff864b2 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1259386 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* touchpad_st: read event fifo in heatmap modeWei-Han Chen2018-10-041-0/+4
| | | | | | | | | | | | | | | Beacon and error events are still available in heatmap mode. BRANCH=nocturne BUG=None TEST=manual on device Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I6ac2e20f62bedf7084edb567765fd5b5fe7ae800 Reviewed-on: https://chromium-review.googlesource.com/1258689 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tcpc: Resume suspended ports after an intervalJonathan Brandmeyer2018-10-048-7/+71
| | | | | | | | | | | | | | | | | | | | | When it appears that the TCPC queue handling logic may be stuck in an infinite loop, the EC will break the loop by disabling the port in order to avoid task starvation. However, nothing attempts to resume the port, and it therefore remains disabled until the next EC reset. Wake back up after a reasonable interval in order to automatically retry. On port suspend, completely drain the TCPM message queue. BUG=chromium:891713 TEST=On Careena hardware, with analogix TCPC firmware v1.5 and an electronically marked cable that sends SOP' messages, verify that the EC auto-retries every second. After removing the offending cable, and PD power supply will work. BRANCH=grunt Change-Id: I563b763501333eb36ee1f76e6f484ebb3245c82a Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1258571 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpc: Simplify ANX74XX device selectionJonathan Brandmeyer2018-10-042-3/+8
| | | | | | | | | | | BUG=none BRANCH=none TEST=buildall Change-Id: I8eb4a9027518aa1c7af18e850984a595bd2bbe23 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1258570 Reviewed-by: Jett Rink <jettrink@chromium.org>
* glados: Increase size of RO segmentJonathan Brandmeyer2018-10-041-1/+1
| | | | | | | | | | | | | | Glados is very tight on code space, but has some data RAM space free. Rebalance some .data allocation to .text. BUG=none BRANCH=none TEST=buildall Change-Id: I88d2ed4090eed04db620962065372c8cd4e8b87b Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1258569 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cheza: Reenable EC hibernateWai-Hong Tam2018-10-043-5/+28
| | | | | | | | | | | | | | | | | | | | | | This CL requires hardware rework or a new hardware revision, which * blocks the current drop to VCC1_RST pin; * makes the lid open and power button signals pulled-up by the EC standby rail. BRANCH=none BUG=b:79348203 TEST=Typed "hibernate" command on EC console and checked waking EC up using the 4 wake sources: * dut-control lid_open:no sleep:0.2 lid_open:yes * Unplug and plug the AC charger * dut-control pwr_button:press sleep:0.2 pwr_button:release * dut-control cold_reset:on sleep:0.2 cold_reset:off Change-Id: Iccc33e3df621da319d422942eda1ec9f01a4fd67 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1123157 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Turn off 3.3V rail on S5Wai-Hong Tam2018-10-042-4/+5
| | | | | | | | | | | | | | | Once the hardware bug is fixed, we can turn off the 3.3V rail on S5 to save power. BRANCH=none BUG=b:110988793 TEST=Tested the EC UART work properly in S5 on a r3 board. Change-Id: I5d1dfcf8a6887e962d761b93e25722de66f61d62 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1194345 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* kukui: Enable magnetometer.Yilun Lin2018-10-042-0/+28
| | | | | | | | | | | | | TEST=make BOARD=kukui BUG=b:113364863 BRANCH=None Change-Id: If56821b9018ae23f086f2d04f9bd15f54de77966 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1235483 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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