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* stack_analyzer_unittest: Unit test of analyze disassembly for Andes instructionstabilize-10985.Btim2018-08-201-2/+100
| | | | | | | | | | | | | | | | | | | | | | | | | Write a rough disassembly with Andes instruction in stack_analyzer_unittest.py which rough disassembly is analyzed by stack_analyzer.py to get some results. If these results are the same with expect results, the unit test will pass. In the rough disassembly, the file format is added in the second line, because the stack analyzer will be looking for the word of 'arm' or 'nds' in the line, and then get the corresponding Analyzer class. BUG=b:111746842 BRANCH=none TEST=./extra/stack_analyzer/run_tests.sh Change-Id: I3acbfb199f762a4e89ea95f6254628871a5beb5d Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1174331 Commit-Ready: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stack_analyzer: EC stack analyzer for Andes instruction architecturetim2018-08-201-38/+194
| | | | | | | | | | | | | | | | | | | | | Add the related stack instructions analysis for Andes architecture to calculate stack frame sizes of functions and find the maximum calling path with maximum stack usage in stack analyzer tool. The second line in each disassembly will present this core architecture, so we can be looking for the word of 'arm' or 'nds' in the line and then get the corresponding Analyzer class. BUG=b:111746842 BRANCH=none TEST=make BOARD=${BOARD} SECTION=RO or RW analyzestack Change-Id: I8414920ddee97ce913519ef878f770e6e3118ef7 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1174332 Commit-Ready: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "meowth_fp: Enable CONFIG_ROLLBACK_MPU_PROTECT"Nicolas Boichat2018-08-201-3/+0
| | | | | | | | | | | | | | | | | This reverts commit 331eaf99ce5376332442f2f1d83d277c6104bbb6, as it breaks flashrom. We'll want to reenable this after we fix flashrom. BRANCH=none BUG=b:111330723 BUG=b:112740263 TEST=/usr/sbin/fp_updater.sh works Change-Id: I3b1fc54a5f60f76f7d39481b1d7b90587c794c01 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1180789 Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* kukui: PMIC_WATCHDOG_L should follow status of PMIC_WATCHDOG_LAyo Wu2018-08-201-2/+2
| | | | | | | | | | | | | | BUG=b:112741115 BRANCH=none TEST=make flash_ec BOARD=kukui -j TEST=waveform in b:112741115 Change-Id: I53798356714289276a5fdaed9f6190a247a1db7d Signed-off-by: Ayo Wu <ayowu@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179494 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* keyboard: Move keyboard_special (lightbar demo) to samus/board.cHung-Te Lin2018-08-203-54/+55
| | | | | | | | | | | | | | | | | | Currently the keyboard_special has only one function - to enter demo or easter egg mode if lightbar task is running. However, only Samus has lightbar so we should not waste time doing keyboard_special on all boards. The better approach is to use the new CONFIG_KEYBOARD_SCANCODE_CALLBACK and provide the lightbar demo check inside samus board.c. BUG=None TEST=make buildall -j BRANCH=None Change-Id: Ie8ab994b5439309663328a75680d45230a6eaeea Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1168702 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "nocturne_fp: [HACK] Disable STOP mode by default"Nicolas Boichat2018-08-191-3/+0
| | | | | | | | | | | | | | | | | | This reverts commit 158e785ffa1cbab14023bcdef506ff49654ea2a5. BRANCH=none BUG=b:75105319 TEST=powerd_dbus_suspend => See that idlestats deep-sleep value increases. TEST=flashrom works. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: Ib675c559193809d861cf64215b485cf9e30abd19 Reviewed-on: https://chromium-review.googlesource.com/1177404 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Norvez <norvez@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* touchpad_st: handle new domeswitch APIWei-Han Chen2018-08-192-16/+10
| | | | | | | | | | | | | | | | In latest ST firmware, domeswitch level is already reported, there is no domeswitch_chg anymore. BRANCH=none BUG=b:70482333 TEST=manual on device Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I6ce21f48ec8aa62a4167a86581acd2e2abee7ce6 Reviewed-on: https://chromium-review.googlesource.com/1177524 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32mon: don't set UART attributes when programming over Cr50Vadim Bendebury2018-08-181-14/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | When EC console is connected over a Cr50 UART to USB bridge, there is no need to try setting up UART properties of the interface device as in this case the settings will not propagate to the target. BRANCH=none BUG=b:62539385 TEST=connect a Scarlet device over SuzyQ to the host and source the following script: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv echo gpioset EC_FLASH_SELECT 1 > /dev/ttyUSB0 echo bitbang 2 57600 even > /dev/ttyUSB0 echo ecrst pulse > /dev/ttyUSB0 sleep 2 <path to>/stm32mon -d /dev/ttyUSB2 -u -U -e -c -w <path to>/ec.bin echo gpioset EC_FLASH_SELECT 0 > /dev/ttyUSB0 echo bitbang 2 disable > /dev/ttyUSB0 echo ecrst pulse > /dev/ttyUSB0 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Change-Id: I5feeaffbc25c029fe6b5d8fa712d5927d00e26ce Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1175317 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* nocturne: Turn on UHALL_PWR_EN by default.Aseda Aboagye2018-08-181-1/+1
| | | | | | | | | | | | | | | | UHALL_PWR_EN needs to be enabled when the EC comes out of reset so that the top hall sensor is active when the EC boots. BUG=b:112110598 BRANCH=None TEST=Verify after EC reset that UHALL_PWR_EN is high. Change-Id: If0370dc462cb74b3f1b9bfb67aff7b9bc9c6e261 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180493 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* touchpad_st: fix heatmap modeWei-Han Chen2018-08-181-2/+6
| | | | | | | | | | | | | | | | The rx_buf was set incorrectly in heat map mode. Also add debug messages to help debugging. BRANCH=none BUG=b:70482333 TEST=test on full system, enable heatmap Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I325a9b7983a16634b95eecdc592c59222e48c7aa Reviewed-on: https://chromium-review.googlesource.com/1177093 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cheza: Don't need to set the switchcap register on initWai-Hong Tam2018-08-171-10/+0
| | | | | | | | | | | | | | The switchcap register should be OTP'ed. BRANCH=none BUG=b:77957956 TEST=On the rev-2 board, power cycle the board, check the switchcap register having a proper value. Change-Id: I558301772404618a1d189a567ea61e743f403e84 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179975 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* bobba: update EC GPIOs for Bobba EVTDiana Z2018-08-174-14/+14
| | | | | | | | | | | | | | | | | | | | - added volume button inputs to bobba's GPIO interrupts - removed USB_OTG pin from the baseboard code since it is unused - changed USB_OTG to USB_C0_PD_RST - added CAM_SOC_EC_SYNC as input for now Since most of the bobba protos use yorp firmware, it seems unlikely we will need to support the proto boards with this change. BRANCH=None BUG=b:112354316 TEST=builds Change-Id: I5a05a55ae731a6cdf293e93535c9256e5eb67520 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1178480 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nocturne: Enable TCPC low power modePuthikorn Voravootivat2018-08-171-0/+2
| | | | | | | | | | | | | | | BUG=b:112037915 BRANCH=none TEST=Lower power in S0ix "TCPC Enter Low Power Mode" log in ec console TCPC exit/enter low power mode when plug/unplug charger Change-Id: Iff44a3a54c3bb44b4d1d3f6ffa9c83689175e5ed Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1168110 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* adc: Add ectool command for reading ADC channels.Aseda Aboagye2018-08-173-1/+65
| | | | | | | | | | | | | | BUG=b:76155036, b:112757066 BRANCH=None TEST=Flash nocturne; update ectool; verify that `ectool adcread <ch>` works as expected. Change-Id: I42545d25f005a7eb9e0af54c8b5cb72d5d844084 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1180095 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* cr50: minor code style touch-up on a bitbang code.Namyoon Woo2018-08-172-55/+42
| | | | | | | | | | | | | | | | | | | | | | | | | Fix 1. removed unnecessary semicolons. Fix 2. enumerated parity types for code readibility. Fix 3. ensured the bool value is passed to gpio_set_level() as val. Fix 4. converted uart_bitbang_config() to static. Fix 2 and 3 save 56 bytes, and Fix 4 saves 72 bytes in flash. BUG=b:65253310 BRANCH=cr50 TEST=manually performed flash_ec, and checked version info at EC console. (chroot)$ ./util/flash_ec --board=scarlet --bitbang_rate 57600 --image=build/scarlet/ec.bin Changes to be committed: modified: chip/g/uart_bitbang.c modified: chip/g/uart_bitbang.h Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I6cea649b908e269d32e547987121621911301a72 Reviewed-on: https://chromium-review.googlesource.com/1179238 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: fix flash_ec stm32 serial EC programming modeVadim Bendebury2018-08-171-17/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Proper sequence of events when enabling STM32 monitor mode is as follows: - bootp0 pin level is set to 'high' - chip is reset - the programmer starts sending sync bytes over the UART This patch implements this sequence in flash_stm32(). In cases when 'cold_reset' control is not available this function will fail, as this means that the STM32 chip can not be reset. When programming over Cr50 a servod control to enter bit bang mode is issued. Newer Cr50 versions support baud rates up to 57600, but until the new Cr50 version is released, 9600 bps should be used as the default. A new command line option is being added to allow specify UART speed when programming in bit bang mode. BRANCH=cr50, cr50-mp BUG=b:62539385 TEST=successfully ran to completion (100 iterations) the following script when programming Scarlet when servo is connected over Cr50: count=0; while ./util/flash_ec --board scarlet --image <image path>; do count=$(( count + 1 )) echo "succeeded $count times" if [ $count == 100 ]; then break fi sleep 3 done Change-Id: Ib3242a92c94f64214ffd1f290b97c2660ce21360 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1171915 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* meep: Add batteries configurationDevin Lu2018-08-172-3/+180
| | | | | | | | | | | | | | meep plan to use batteries the same as careena. BUG=b:111838980 BRANCH=none TEST=make buildall -j Change-Id: I29955dfaecefd16a48b6b14a48c3f06de97e11c0 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1177096 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Bobba: Disable Base Accel/Gyro sensor for clamshellsTino Liu2018-08-172-1/+26
| | | | | | | | | | | | | BUG=b:112442777 BRANCH=none TEST=Verify screen will not rotate when sku id is clamshell Change-Id: I2cca78c05d52b8914018b9ea5f56918be93427f8 Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1172306 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Revert "**/build.mk: Set CROSS_COMPILE* to point to coreboot-sdk"Wei-Han Chen2018-08-174-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bcd6842fb861b99588039b0bb72fafd92853525e. Reason for revert: This breaks whiskers. Original change's description: > **/build.mk: Set CROSS_COMPILE* to point to coreboot-sdk > > board/servo_v4 used it already but doesn't need the override anymore, > nds32 also used it, therefore no change. > > BUG=chromium:851727,b:65441143 > BRANCH=none > TEST=builds with the new compiler > > Change-Id: I59a7181b87293da2a8515b158c17417b5ba05404 > Signed-off-by: Patrick Georgi <pgeorgi@google.com> > Reviewed-on: https://chromium-review.googlesource.com/1172974 > Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> > Tested-by: Patrick Georgi <pgeorgi@chromium.org> > Reviewed-by: Stefan Reinauer <reinauer@google.com> Bug: chromium:851727, b:65441143 Change-Id: If09eca04efc6461b951879ad528832bc50ca50d2 Reviewed-on: https://chromium-review.googlesource.com/1177221 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne_fp: Disable sleep when AP in S0Nicolas Boichat2018-08-171-3/+6
| | | | | | | | | | | | | | | | | Only allow STOP mode when AP in S0ix/S3. BRANCH=none BUG=b:75105319 TEST=powerd_dbus_suspend => See that idlestats deep-sleep value increases. TEST=flashrom works. Change-Id: I69b48adc3bd7033f88c1b606436aff0c68d5d1ac Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1177403 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* cheza: Support battery cutoffPhilip Chen2018-08-172-0/+19
| | | | | | | | | | | | | | BRANCH=none BUG=b:112611441 TEST=verified on Cheza rev1, battery enters ship mode through 'cutoff' ec command and then wakes up through AC attach Change-Id: I1cd2083d3f01da3f60af312d5af9af0d3bab15df Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178477 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* nocturne: Control UHALL_PWR_EN based on lid state.Aseda Aboagye2018-08-172-1/+13
| | | | | | | | | | | | | | | BUG=b:112110598 BRANCH=None TEST=Flash nocturne; verify board still boots. Check that the logic would do the right thing if the board version matched. Change-Id: I39bd7eb6f3d73dde4c42b3abfbb38d0de424dcf5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1179314 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne: Enable low power idlePuthikorn Voravootivat2018-08-171-0/+1
| | | | | | | | | | BUG=b:112037915 TEST=25mW lower in s0ix Change-Id: Ie7e6c3e3d1372f64730d322864e4315afdf7c2e6 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1178973 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* keyboard: Add CONFIG_KEYBOARD_SCANCODE_CALLBACK for board-specific hooks.Hung-Te Lin2018-08-173-0/+31
| | | | | | | | | | | | | | | | | | | | | Many devices may want board-specific keyboard hooks, for example allowing easter egg (to replace the key_special today), or to provide dynamic translation. Both can be done by having a callback whenever the key state is changed (after scancode is found). The new CONFIG_KEYBOARD_SCANCODE_CALLBACK allows boards to define their own hook keyboard_scancode_callback so the keystrokes can be either changed or monitored. BUG=b:72200093 TEST=make buildall -j BRANCH=eve Change-Id: I02e3bf5c217b2f30b942d96ecb2c493ce200638f Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1168281 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nocturne: Add board_set_tcpc_power_mode().Aseda Aboagye2018-08-172-0/+12
| | | | | | | | | | | | | | | | | | | | When depthcharge needs to update the TCPCs, it needs to reset them at the end of the update procedure. Conveniently, this function will be called if it exists, therefore this commit implements that function. It simply resets the TCPCs and then waits about 50ms for the part to come up. BUG=b:69010531 BRANCH=None TEST=With other patches, flash nocturne; verify that TCPC FW can be updated. Change-Id: Ie3dfd913b376a60fbf8de4c9f53cc9c6a497aa19 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1173024 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* Bobba: Modify the LED behavior for factory mode.Ryan Zhang2018-08-171-0/+2
| | | | | | | | | | | | | | | | | | | | 2s for Blue led, 2s for Amber led, iterations. BUG=b:111775507 BRANCH=master TEST=`chgstate idle on`, `chgstate idle off`, `chgstate discharge on`, `chgstate discharge off` all sees correct LED color. Change-Id: I6710466a45a7b3b74f20e8e9d0d93828726607df Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1177204 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Paris Yeh <pyeh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* board: eve: Do not set accelerometer ODR beyond 200HzGwendal Grignou2018-08-172-3/+4
| | | | | | | | | | | | | | | | | | | | When ODR is set above 200Hz, the EC can not keep up with the accelerometer, causing deadlock. ODR was set at 400Hz for double tap detection. However, that high frequency is only needed for LSM6DS0 where tap detection is done in software (samus). 200Hz is good enough when tap detection is done in hardware. BUG=b:112672627 BRANCH=eve TEST=Check eve is done dead locking at boot. Check double tap still works. Change-Id: Id41dc06eb357b1cdc78d22b89440f01c44a3c16c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1179182 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Fleex: Enable adc vbus sensingelthanhuang2018-08-172-0/+20
| | | | | | | | | | | | | | | | | | Enable adc vbus sensing ADC CH9 read real USB_PD_PORT_ANX7447 input voltage ADC CH4 read real USB_PD_PORT_PS8751 input voltage BUG=b:112576391 BRANCH=none TEST=Excute "ectool usbpdpower" to check SNK Charger PD voltage. Change-Id: Ia7ef58905219e0392e4ca4fba4694c144741b0a8 Signed-off-by: elthanhuang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1177528 Commit-Ready: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chgstv2: Use lower charge threshold for boot if AC power is presentDaisuke Nojiri2018-08-173-6/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | If one of the following conditions is met, EC boots AP: 1. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON 2. AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 3. Battery charge >= CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC and AC power >= CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON_WITH_BATT This reduces users' wait time significantly when a battery is drained. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:112172032 BRANCH=Nami TEST=Verified Akali and Sona boot and perform soft sync successfully. The power consumption is measured during boot and verified even worn out battery can supply enough power to sustain the system together with a 15W charger. Change-Id: I3220b4660a1b50ba5ead8f570cb6992c0a30e390 Reviewed-on: https://chromium-review.googlesource.com/1177722 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Nami: Report error for disconnected battery on SonaDaisuke Nojiri2018-08-161-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Sona, when a battery is cutoff, the gas gauge does not clear BATTERY_DISCHARGING_DISABLED or BATTERY_CHARGING_DISABLED until a precharge current is supplied. This patch makes battery_is_present return BP_NOT_SURE for the first 5 seconds after the battery is found electrically disconnected. After 5 seconds, it reports BP_NO as it normally does. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:112292720 BRANCH=nami TEST=Verify the battery wakes up from cutoff mode. Verify a bad battery eventually stops being charged. Change-Id: I4d0e9e5ed0e9631b7bbf8565ce62c17da8a0a848 Reviewed-on: https://chromium-review.googlesource.com/1171259 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 4363e098c546f09cdfcc9c10de09b0c517d52e63) Reviewed-on: https://chromium-review.googlesource.com/1177721 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: Split i2c_xfer into locked/unlocked versions.Jonathan Brandmeyer2018-08-1618-153/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename i2c_xfer to i2c_xfer_unlocked. Audit all users of i2c_xfer to see if they can use simple locking semantics or require their own locking. Since locked accesses are only safe for I2C_XFER_SINGLE transactions, remove the flags parameter from i2c_xfer. This also makes the audit a bit easier. Some remaining applications hold the bus locked across several transactions that would otherwise be atomic, and a few others implement complex I2C transactions in multiple commands. Add a (nondeterministic) verification on the I2C port locking correctness. This will catch all statically incorrect locking patterns, although dynamically incorrect locking patterns may not be caught. Related: Revise the i2c_port_active_count to be a bitmap of the active ports instead of a count of the active ports. The EC's mutex does not provide an is_locked() primitive, and we would prefer not to have one. - board/glados: Custom locking for battery reset - board/mchpevb1: Custom locking for battery reset - board/oak: Custom locking for battery reset - board/samus: Custom locking for lightbar reset - board/sweetberry: simple locking - board/servo_micro: Custom locking for funky i2c transfers - capsense: simple locking - host_command_master: multi-command transactions - lb_common: manual locking to support samus power sequence - smbus: multi-command transactions - usb_i2c: simple locking - driver/tcpm/fusb302: simple locking and multi-command transactions - driver/tcpm/tcpi: Forward _unlocked and implicitly locked interface to fusb302 - driver/touchpad_elan: simple locking BUG=chromium:871851 BRANCH=none TEST=buildall; very careful audit TEST=grunt clamshell and Coral clamshell, test boot, battery charging, PD communication, and TCPC port low-power mode. Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: Ieabf22bcab42780bdb994fca3ced5d8c62519d56 Reviewed-on: https://chromium-review.googlesource.com/1169913 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui: Set AP_SYS_RST_L to GPIO_OUT_LOW instead of ODRtonycwlin2018-08-161-1/+1
| | | | | | | | | | | | | | | | | AP_SYS_RST_L should be able to drive high to MT8183's SYSRSTB pin. The reset map is in link for reference. (https://drive.google.com/file/d/1pR6PZGHA2QLAWjSNHoIema4WmtpOuXyR/view) BUG=b:112678658 BRANCH=none TEST=make flash_ec BOARD=kukui -j Signed-off-by: tonycwlin <tonycwlin@google.com> Change-Id: I02018114d5c3dbdcd1f840cbb7712c80d2b6c90e Reviewed-on: https://chromium-review.googlesource.com/1177419 Commit-Ready: Tony Lin <tonycwlin@google.com> Tested-by: Tony Lin <tonycwlin@google.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* keyboard: Change scan code magic values to enum.Hung-Te Lin2018-08-163-22/+74
| | | | | | | | | | | | | The key codes are now always scan code set 2 so we can create a list of scan codes and use them easily. BUG=None TEST=make buildall -j; boots properly BRANCH=None Change-Id: I1fdd7ab81bc13c97c4139afc19d71f5898e22f96 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1166743
* bip: config NC pinsDino Li2018-08-162-0/+23
| | | | | | | | | | | | | | | | | This CL enables internal pull-down for unused pins to prevent leakage current caused by floating state. Disable keyboard scan module by setting KSO/KSI pins as GPIO input in hibernate. BUG=b:111006203 BRANCH=none TEST=Check power consumption drops in hibernate. Change-Id: I7e383153aa61ff939b9bc709fc6672718d9ec5fc Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1163585 Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: host_command_fuzz: fuzzing testNicolas Boichat2018-08-1615-16/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | Writing fuzzing tests is a little tricky, as clang takes over the main function. Instead, we start the test main function in a thread, and have LLVMFuzzerTestOneInput prepare the host command buffer, and wake the TEST_RUNNER task. To make fuzzing faster, we only send somehow correctly formed requests, with a valid checksum and length (this can be disabled with an option). We also make sure that the emulator does not hibernate, reboot or jump to a different image when fuzzing is enabled. BRANCH=none BUG=chromium:854975 TEST=make buildfuzztests -j ASAN_OPTIONS="log_path=stderr" \ build/host/host_command_fuzz/host_command_fuzz.exe -timeout=5 Change-Id: I27b25e44c405f118dfc1296247479245e15e54b4 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1107523 Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jonathan Metzman <metzman@chromium.org>
* ppc: nx20p3483: Rename driver to nx20p348x to support NX20P3481Scott Collyer2018-08-1611-214/+214
| | | | | | | | | | | | | | | | | | | | | | This CL doesn't change any functionality, but renames the driver from 3483 to 348x. The motivation for this is that we need to support the NX20P3481 PPC as well. Those chips use the same registers, but the 3481 adds FRS support and sink/source control is done via I2C writes instead of gpio controls. Because the chips are slighlty different the config option CONFIG_USBC_PPC_NX20P3483 needs to remain. BUG=b:111281797 BRANCH=none TEST=make -j buildall Change-Id: Ie1085140eb2ef23c0b6e1a79a6f2d7f823326c6d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1176382 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: speed up bit bang EC programmingVadim Bendebury2018-08-168-282/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original bit bang programming implementation attempted to provide a fully functional alternative UART interface for the case when EC programming is required, so that proper UART parity can be ensured. Come to think of it, this is not really necessary: - EC programming over UART does not require full duplex. - when EC is being programmed, the AP is held in reset, there is no need to support AP console or TPM at that time, as a result interrupts could be disabled for somewhat longer intervals. This patch introduces the following modifications: - remove uartn interface redirections - when bitbang mode is enabled regular EC console is not available. - instead of waiting for fixed amount of cycles on every bit, wait for the deadline calculated when character transmission started on tx side or when the original start bit was detected on rx side and recalculated after each clock. - when finishing receiving a character do not exit ISR right away, spin for a duration of a character polling the rx line, in case the EC keeps transmitting. The rx buffer is allocated on the ISR stack and is limited to 20 bytes, which would probably cause an overrun if this interface were used for reading flash contents from the EC. - connect USB EC console flow directly to the bit bang driver when bit bang mode is enabled and disable interrupts from the EC UART. - do not use the GPIO wrappers for bit bang interrupt processing - it takes too long. - when starting a bit bang session set the clock timer value to zero, this allows not to worry about wraparound, which will happen in almost 3 minutes, programming session should not take this long. - for the duration of 'bit bang enabled' state servo detection interrupt is disabled, it gets re-enabled after bit bang mode is disabled and servo_detect() gets to run on 1s hook. - it is not enough to check the DIOB5 pinmux state to tell if EC UART is connected or not, as this pin could be connected in bit bang mode as well; always report EC TX UART as disconnected when bit bang mode is enabled. - for the duration of bit bang programming session suppress 'aggregate' GPIO interrupts, triggered per port when GPIO interrupt is asserted. Additional speed up could be achieved if gpio driver wrappers were replaced with direct register accesses, but even as presented this patch allows to reliably program the STM32 on Scarlet at 57600 baud, which is 6 times faster than the current state. BRANCH=cr50, cr50-mp BUG=b:62539385 TEST=with some flash_ec modifications which make sure that bit bang mode is enabled properly (fixing timing of setting boot0 and resetting the EC), Scarlet device EC can be reprogrammed at 57600 baud 100 times in a row with and without logic analyzer connected to the EC UART pins. Change-Id: I2e3520f158943323cb015fa18650a7e177f03cc3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1171221 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: gpio: Set KSO/KSI pins to GPIO mode by gpio_set_flags_by_maskDino Li2018-08-161-6/+8
| | | | | | | | | | | | | | | With this change, we can reconfigure KSO/KSI pins as GPIO mode by calling gpio_set_flags_by_mask(). BUG=b:111006203 BRANCH=none TEST=Declare KSO/KSI signal with GPIO_INPUT flag and check if these pins work as GPIO input. Change-Id: I3b1fcc989745da08898d2f254dedc9655fd0ef83 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1163584 Reviewed-by: Jett Rink <jettrink@chromium.org>
* keyboard: Keep only scan code set 2 table and do translation for set 1.Hung-Te Lin2018-08-154-108/+92
| | | | | | | | | | | | | | | | | | | | | | | | | The 8042 scan code set 1 can be directly translated from set 2, with a 256 byte table. With this change, we can always process key stroke in scan code (set 2), and only translate in the single function `scancode_bytes`. This is very helpful when we need to do key processing, for example the buttons_8042 can now be simplified with only one scan code. And is extremely helpful if we want to do dynamic translation (i.e., to prevent something like CL:1164725). For `make BOARD=samus', the free space is also increased from 18472 to 18656 (+184) bytes. BUG=None TEST=make buildall; manually installed on Eve and tested by running 'keyboard' factory test to make sure all key scancodes are not changed. BRANCH=None Change-Id: Ieb303d84edcd4375bbeb1ea5f032d0462bbfd250 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1166742 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* servo_v4: add per port dualrole settingNick Sanders2018-08-1540-204/+312
| | | | | | | | | | | | | | | | | | | | | | | This adds support to configure dualrole setting per port, so that servo v4 can adjust charge and dut port separately. servo will detect charge capability on CHG port and choose source or sink as appropriate. Fix null dereference bug in genvif duel to dynamic src_pdo. "cc" command allows src, snk, srcdts, snkdts configurations. BRANCH=None BUG=b:72557427 TEST=charge through and also passive hub. Note Dru doesn't accept DTS hub. TEST=make buildall -j Change-Id: I19f1d1a5c37647fec72202191faa4821c06fb460 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096654 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* util/ecst: Fail on partial readsPatrick Georgi2018-08-151-6/+6
| | | | | | | | | | Change-Id: Iadc031195773f7f1eac6642de6995659eab42707 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Coverity Scan #58140, #58142, #58143 Reviewed-on: https://chromium-review.googlesource.com/1151187 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* **/build.mk: Set CROSS_COMPILE* to point to coreboot-sdkPatrick Georgi2018-08-154-5/+6
| | | | | | | | | | | | | | | | board/servo_v4 used it already but doesn't need the override anymore, nds32 also used it, therefore no change. BUG=chromium:851727,b:65441143 BRANCH=none TEST=builds with the new compiler Change-Id: I59a7181b87293da2a8515b158c17417b5ba05404 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1172974 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* nocturne: Change RCAM_VSYNC to rising edge.Aseda Aboagye2018-08-151-1/+1
| | | | | | | | | | | | | BUG=b:111282744 BRANCH=None TEST=`make -j BOARD=nocturne` Change-Id: I2588291e4daf336ad9365bc21faef0761386c989 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1175542 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* grunt: Enable LTOJonathan Brandmeyer2018-08-151-0/+1
| | | | | | | | | | | | TEST=buildall; boot grunt convertible and exercise keyboard, suspend, PD, and battery cutoff BUG=none BRANCH=none Change-Id: I95f2b8c214b20c2d733843647f398393fdd9e909 Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1175853 Reviewed-by: Edward Hill <ecgh@chromium.org>
* nocturne: Flip board version reporting.Aseda Aboagye2018-08-151-5/+5
| | | | | | | | | | | | | | | | | | | It turns out that BRD_ID3 was not actually the least significant bit in the board version strapping. In actuality, it turned out to be BRD_ID0. This commit simply flips the board version reporting to have BRD_ID0 to be the least significant bit. BUG=b:73260349 BRANCH=None TEST=Flash nocturne; verify that board revision match up with board version table in the schematics. Change-Id: I8a3f3e3dbb5dbdcbdd55793d55c711d8ec9670a4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1175557 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cheza: Fix LED mappingPhilip Chen2018-08-151-7/+7
| | | | | | | | | | | | | | | | | Map EC_LED_ID_RIGHT_LED to p0 and EC_LED_ID_LEFT_LED to p1. BRANCH=none BUG=b:112600822 TEST=switch LED colors by 'ectool led' for right/left LEDs TEST=verify the LED behavior for charge/discharge state doesn't change Change-Id: I12f5e542f9b25a55015c953c8c3814c8772f0c74 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1175132 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* it5205: put ite5202 mux into low power modeJett Rink2018-08-151-3/+18
| | | | | | | | | | | | | | | | When the SS MUX is fully disconnected, put the mux into a low power state. BRANCH=none BUG=b:111006203,b:111520593 TEST=BIP PD_A rail went from 3.97mW down to 2.65 mW during hibernate with the other corresponding PPC changes in CL:1166184 Change-Id: Ief636b569fe01db7f129ca2d457352c3799c14f9 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1169698 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ps8751: add low power mode for PS8751 when only MUXJett Rink2018-08-151-19/+75
| | | | | | | | | | | | | Enter lower power mode for PS8751 when acting as mux only. BRANCH=none BUG=b:111664205,b:111876407,b:10937880 TEST=PS8751 as MUX on C1 Bip goes into low power mode after disconnect. Change-Id: Ifac3b76556069e1e5f6acae550d8076c29d5f1cd Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1153835 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* ss-mux: move enter_low_power_mode method to drvJett Rink2018-08-152-14/+14
| | | | | | | | | | | | | | | | | After implementing this new method twice, I realized that the enter_low_power_mode method did not need to be configured at the board level so it can move to the more common mux driver. BRANCH=none BUG=none TEST=bip low power mux operation still works Change-Id: I33d7191ae22da089972929eb60b3bae568a2c447 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1169904 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* util/ecst: Also report copy failure on writesPatrick Georgi2018-08-151-2/+8
| | | | | | | | | | Change-Id: Ie01daa75b22fd1efca1c72d34c42c18abea53c2e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Coverity Scan #58172 Reviewed-on: https://chromium-review.googlesource.com/1163610 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
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