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* Documentation for CCD and servo_microstabilize-10575.58.Bstabilize-10575.54.Brelease-R67-10575.BMark Hayter2018-04-133-0/+176
| | | | | | | | | | | | | | | | | | | | Add markdown documentation (from reviewed doc) for the Servo Micro as an example of CCD. Tested with emacs markdown preview (markdown package) which is almost the same as gitiles. BUG=none BRANCH=none TEST=emacs markdown preview Signed-off-by: Mark Hayter <mdhayter@chromium.org> Change-Id: Ic5877a3b80313089ab9c79e376b4ee1f58e573eb Reviewed-on: https://chromium-review.googlesource.com/996893 Commit-Ready: Mark Hayter <mdhayter@chromium.org> Tested-by: Mark Hayter <mdhayter@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* it83xx: Add eSPI virtual wires for SMI & SCIVijay Hiremath2018-04-131-0/+12
| | | | | | | | | | | | | | | | | | eSPI virtual wires for SMI & SCI are missing in ITE chip code, added them to avoid compilation error if ESPI config is enabled. BUG=b:77798195 BRANCH=none TEST=make buildall -j Change-Id: Ibfceb3d0fff56ccb145358a776cf76e45d92a311 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1009110 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
* cleanup: it83xx: pull pnpcfg_settings[] to the chip-levelDino Li2018-04-125-275/+90
| | | | | | | | | | | | | | | | | With this change, we don't need to declare pnpcfg_settings[] for each it83xx based board. BUG=b:76022972 BRANCH=none TEST=make buildall -j, boot to kernel on reef_it8320. Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1009544 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cbi: always refersh data for cbi ec commandstabilize-meowth-10574.BJett Rink2018-04-121-19/+28
| | | | | | | | | | | | | Also updated the description of the cbi command in help BRANCH=none BUG=none TEST=wrote directly to flash and verified the cbi command updated Change-Id: I54b5d995a0f06b9566622a5079da11ce575fb309 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1008831 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* flash_ec: fix UART bitbang flashing with ccdMary Ruthven2018-04-121-12/+30
| | | | | | | | | | | | | | | | | | | Cr50 is pretty slow to update it's ccd state right now. Add some delays when flashing devices using uart bitbang, so cr50 will have enough time to enable bitbang and configure the uarts correctly. Also add some commands to cleanup to cleanup the cr50 state. BUG=b:77825616 BRANCH=none TEST=run util/flash_ec using ccd on reef and scarlet. Change-Id: I1c84e36c9bb290c49fd15971c7f61f9e1151a424 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1006484 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* flash_ec: add more verbose optionsNick Sanders2018-04-121-1/+5
| | | | | | | | | | | | | | | | Print stm32mon command in verbose mode. BUG=None BRANCH=None TEST=it prints Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I4b31d1212c139f64e34e92fa0def662202aa3b41 Reviewed-on: https://chromium-review.googlesource.com/1004436 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nocturne_fp: add flashing configurationVincent Palatin2018-04-121-1/+2
| | | | | | | | | | | | | | | | | Declare it in the proper category for flash_ec Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:77836478 TEST=./util/flash_ec --board=nocturne_fp Change-Id: If5b9882bb919505c724d4536521b57279a6a302b Reviewed-on: https://chromium-review.googlesource.com/1009842 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* stm32mon: terminate gracefully when failing to get commands listVincent Palatin2018-04-121-1/+3
| | | | | | | | | | | | | | | | | | | When the CMD_GETCMD transaction fails, terminate immediately rather than continuing and crashing when we use later the uninitialized 'erase' function. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:77825616 TEST=flash Scarlet EC through CCD. Change-Id: Ia40107fe27d81fdb9ee8220f73f4215d936a41c1 Reviewed-on: https://chromium-review.googlesource.com/1006595 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* atlas: manage USB-C high speed muxesstabilize-10569.BCaveh Jalali2018-04-122-0/+23
| | | | | | | | | | | | | | | | | | this adds control over the USB high speed muxes as a function of DP HPD. this allows an external monitor to be added/removed with chromeos extending the display as appropriate. BUG=b:77151172 BRANCH=none TEST=chromeos detects external monitor plugin and extends display Change-Id: I7df7a8136ddaa4eeaca800d29b46350dafd8f838 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1009208 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* yorp: Configure CONFIG_EXTPOWER_DEBOUNCE_MSDivya Sasidharan2018-04-111-1/+6
| | | | | | | | | | | | | | | | | | | | Without this configuration defined the board assumes battery only mode for G3->S5 boot up power sequence and thereby waits for power button press. BUG=b:76230069;b:75974377 BRANCH=None TEST=On yorp, with battery and external power connected reboot on EC console boot the SoC to S0. Verify on both ports. Change-Id: I837b7f99bd3c238ce74e394c773169d703ad9392 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1008247 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: substitute RMA keys when signing for prodVadim Bendebury2018-04-111-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | A recent codebase change included the test RMA reset server public key in the Cr50 image by default. Prod images must not include the test key, and luckily recent modifications of the cr50-codesigner utility allow to swap the keys before signing. This patch adds the command line option for swapping the keys and a check to ensure that the signed image includes the prod key and does not include the test key. Note that cr50-codesigner would fail to sign if the swap was requested but the test RMA key was not found in the input .efl file. Thus both conditions are verified: that the original image includes the test key and that the signed image includes the prod key. BRANCH=none BUG=b:73296144 TEST=prod signed an image, verified that it can be RMA reset using the prod RMA reset server. Change-Id: Ic084d0c5e1de9f027db05c63f82542c2b7cbd916 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000756 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* yorp: Disable config for DRP_AUTO_TOGGLEDivya Sasidharan2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Since there are known issues with ANX7447 driver to work reliably in low power mode, disable DRP_AUTO_TOGGLE option since TCPC_LOW_POWER mode config and this one should be disabled together. BUG=b:77544959 BRANCH=None TEST=On yorp; on port 0 and 1 test without and with battery boots up. Please note with battery we may still need to press power button to get the SoC to boot up to S0 b:76230069. Detaching the Type-C charger with battery connected also shuts down the system which is a known failure b:77606986. Change-Id: I1b744cd9aa063328845f9a1cc7e36d291dfec9f5 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1007629 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpci: Change role control setting for auto-toggle enableScott Collyer2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In tcpci_tcpc_drp_toggle the role control is being set to TYPEC_CC_OPEN. This works for the parade tcpci compliant tcpc, but does not work the anx7447. The tcpci spec has this description for the role control requirement (4.4.5.2): If DRP=1b, the only allowed values for CC1/CC2 are Rp/Rp or Rd/Rd. COMMAND.Look4Connection shall do nothing if CC1/CC2 are not Rp/Rp or Rd/Rd. This CL changes the role control setting associated with starting auto-toggle to be TYPEC_CC_RD. BUG=b:77544959 BRANCH=NONE TEST=Verfied that anx7447 does auto toggle between Rd and Rp. Previously, the TCPC_REG_COMMAND_LOOK4CONNECTION command was being ignored. Change-Id: Iea7ce963ebf57c0f3d43005385484913d97774fd Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1005795 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: bypass signing step if cr50-codesigner is not availableVadim Bendebury2018-04-1113-2434/+5
| | | | | | | | | | | | | | | | | When building EC targets in the setups where the Cr50 codesigner utility is not present let's just bypass the signing step. Also removing bitrotten source code of the old codesigner. BRANCH=none BUG=chromium:830302 TEST='make buildall' succeeds even if cr50-codesigner is not available. Change-Id: Ic6c4988455bcee6c45504e1fe781f6e03636d57a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1005401 Reviewed-by: Allen Webb <allenwebb@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* u2f: accept short APDUVincent Palatin2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | The ISO7816-4 standard for APDU format says the APDU header minimum size is 4 bytes (CLA, INS, P1, P2). The Lc field is absent if the command has no data. Update the size check to accept short APDU (the actual APDU len was already computed properly for this case). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=b:72788497 TEST=adhoc Change-Id: Ic60fa51bd4746b04016c488a38fe3ae7585e9942 Reviewed-on: https://chromium-review.googlesource.com/1005345 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* poppy: Move PMIC init to a deferred functionNicolas Boichat2018-04-111-1/+4
| | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to poppy board file) BUG=b:77336348 BRANCH=poppy TEST=while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done for 24 hours Change-Id: Icd9c2096ca026da6308b74582144886b30ea965f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1003436 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Disable ALS for Sonaraymondchou2018-04-101-1/+1
| | | | | | | | | | | | | | | | Use OEM ID to update motion_sensor_count to disable ALS for Sona. BUG=b:77185923 BRANCH=none TEST=Change oem id for Sona then to check the ALS was disabled. Change-Id: I25714d0a2d2c0f4e9855a70fcb12cb9e65bae9f8 Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/986034 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: stanley zhong <stanley_zhong@compal.corp-partner.google.com>
* cr50:usb_spi: add Cheza EC supportMary Ruthven2018-04-101-4/+11
| | | | | | | | | | | | | | | | | | | The Cheza EC requires EC_RX_H1_TX be held low while the EC is being reset to enter gang mode. This change adds another programming mode to ec usb spi programming to do that. BUG=b:74388083 BRANCH=cr50 TEST=The cheza boards aren't in, so I just tested EC_TX_CR50_RX_OUT gpioset EC_TX_OUT 0 and 1 setup EC_TX_CR50_RX_OUT correctly as an output when asserted and an input when deasserted. Change-Id: I7fc9cba954f2af5a841f00ce5bf8a27251b33bbe Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1003529 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: implement reboot wait-extNick Sanders2018-04-101-0/+9
| | | | | | | | | | | | | | This was missed on stm32, but is helpful for servod to work reliably. BUG=b:77830536 TEST=it waits 10 sec for external reboot. Change-Id: Ic4c905846c41b43f3b8542d70e021744716bd0c2 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1004437 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* chgstv2: Check charger power in prevent_power_on.Aseda Aboagye2018-04-105-29/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | charge_prevent_power_on() had sections which were gated on the following CONFIG_* option: CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT However, the block of code that this gated didn't even take the battery percentage into account and made it very confusing as to why. This commit simply changes the CONFIG_* option used to gate to be the following: CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON This better reflects the checks that were actually being made. Additionally, this CONFIG_* option is defined by default for boards that have a chipset task and is initialized to 15W, which is the power that indicates that the charger is likely to speak USB PD. BUG=b:76174140 BRANCH=None TEST=make -j buildall Change-Id: Ic9158dd7109ce6082c6d00157ff266842363b295 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/977431 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* yorp: Enable DP alternate modeDivya Sasidharan2018-04-102-6/+26
| | | | | | | | | | | | | | | | | | | This code enables alternate mode path for DP for both TypeC ports. BUG=b:77496487 BRANCH=None TEST=On yorp; check if the mux is set correctly for DP use cases. When PD message for hot plug is received by EC, EC (write register) ---> TCPC (GPIO) ---> SoC, and display comes up with both ports. Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1003330 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* iteflash: Continue call ftdi_read_data() until all data is readDino Li2018-04-102-21/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We found a symptom that iteflash always programming EC failed on a specific host machine. For this failed case, it is caused by the incomplete read from ftdi_read_data(). For example, we want to read 32 bytes by just call ftdi_read_data() one time, but ftdi_read_data() may return (number of bytes read) 10 or 20 but just not 32. This change will call ftdi_read_data() again and again until all data is read. Change draw_spinner() function to use fprintf(). We will show percentage increase from 0 percent to 100 percen during verifying. Change of flash_ec script: Move operations of reinitialize ftdi_i2c interface to cleanup() and we won't miss them if programming is failed. BUG=none BRANCH=none TEST=To run iteflash on that host machine and flashing is done. Change-Id: Ifa374652870737c8231fce5a699abe033a1f0237 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/979903 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nautilus: Shrink accelerometer FIFO to 512 entriesNicolas Boichat2018-04-101-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that the shared memory buffer on Nautilus starts at 200c7720 D __shared_mem_buf That's 29.78 kb into the RAM. Software sync needs 1kb, so we should be fine, expect that the last 2kb of RAM are supposed to be reserved for the "booter" (NPCX_BTRAM_SIZE). We shrink the accelerometer FIFO to 512 entries, freeing up 4kb of RAM, and increase the UART TX buffer to 4kb, to make use of 3kb of that freed up space: 200c7320 D __shared_mem_buf That's 28.78 kb into the RAM. BRANCH=poppy BUG=chromium:739771 TEST=make BOARD=nautilus -j, check that shared_mem_buf offset is < 29 kb. Change-Id: I361a439b847d31d3415f2ee66229bd32f8816e2d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1002712 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Add Cheza to use UUT flashingWai-Hong Tam2018-04-101-0/+1
| | | | | | | | | | | | | | | | | | | Cheza board doesn't have the SPI guag programming interface. Should use Uart to flash it. BRANCH=none BUG=b:74395451 TEST=Manual, steps: * Add Uartupdatetool to the PATH * Build the Cheza EC image * Run "flash_ec --board cheza" on a reworked Meowth, which uses the same EC chip as Cheza Change-Id: Ica0878778314ad016273877683a85a912890161c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/969419 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* tcpci: add vbus caching back for tcpci except in parade driverJett Rink2018-04-102-18/+32
| | | | | | | | | | | | | | This effectibly reverts CL:993394 except for the parade driver BRANCH=none BUG=b:77458917 TEST=yorp p1 still works Change-Id: I04a57cfcbd19e9f8fdf8165c228a24089c0e1b67 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1005403 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: fix assorted signer script issuesVadim Bendebury2018-04-101-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | - make sure DBG images could not be signed for prod When debug image marker was changed from "DEV" to "DBG", the script checking for this was not updated. Fix that and also use 'strings' generated output to not require grep to delineate input binary blobs into strings. - do not invoke cr50-codesigner as sudo, it is not necessary with the correct udev rules in place. BRANCH=none BUG=b:73296144 TEST=Tried signing for prod a DBG image, the attempt failed. Then built a non DBG image, signed it successfully. Change-Id: I7cec2d9eb344b40f7726d7e432689b0c0416dc47 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000755 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* battery: treat error codes properlyCaveh Jalali2018-04-101-4/+5
| | | | | | | | | | | | | | | | | | the "cutoff" command would print "Invalid argument" which is EC_invalid but the underlying funciton actually returned EC_RES_ERROR, so we need to map the error codes from the EC_RES_* (enum ec_status) number space to the EC_ERROR_* (enum ec_error_list) number space. BUG=none BRANCH=none TEST=cutoff command now prints "Unknown error" instead of "Unimplemented". Change-Id: I0b2928e629cc859bc3ba5587bf6c7fd70e1084d7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/999102 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nx20p3483: Fix VBUS OVLO threshold and dead battery mode checkScott Collyer2018-04-101-27/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the board is not powered until VBUS is connected, then that port will trigger dead battery mode in the PPC. This mode must be exited by the host (EC) writing to the control register. Until dead battery mode is exited, VBUS OVLO is fixed at 6.8V. Therefore the regular setting of this value must be done after exiting dead battery mode. This CL also changes the check for dead battery mode to use the mode value in the device status register. The bit in the control register does not reflect the status, but rather, if dead battery mode exit has been written by the host. The current check will result in the dead battery mode section being executed for both ports after every power up. However, only the port that has VBUS active would succeed because the HV_SNK mode can't be enabled unless VBUS is present. Lastly, this CL changes the verification check for the sink/source_enable functions to rely on the mode in the device status register instead of the switch state. The reason for this is that the switch state requires ~15 msec delay before it gets updated following SNK_EN to the nx20p3484 being set high. However, the mode reports the correct state without reqiuring a msleep. BUG=b:77561535 BRANCH=NONE TEST=Tested both port 0 and 1 and verified that Yorp can power up without a battery. In addition verified that nx20p3483_vbus_sink_enable returns EC_SUCCESS for both enable/disable cases. Change-Id: I2c993b592cd30e34a39d1c1b7e3c54be9f505844 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1005621 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_charger: initialize VBUS supplier at startupJett Rink2018-04-104-29/+12
| | | | | | | | | | | | | | | | | | | | | | | | | When using VBUS_DETECT_TCPC the charger code relied on the TCPC alert to initialize the VBUS supply, but that happens too late in board startup sequence to allow an initally plugged in USB-C power supply to be chosen as the active charging port. We can and should initialize the the supplier sooner as to prevent the charge_manager_is_seeded() check from failing thus preventing the board from choosing a charging port. BRANCH=none BUG=b:77458917 TEST=PS8751 on yorp will negotiate 20V over USB-C (which was prevent by the charge_manager not being seeded) Change-Id: I6f612c508932a90ece0036ce8310a20de02d8467 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/994707 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ppc: Add tcpci snk/src control via the COMMAND registerScott Collyer2018-04-106-0/+84
| | | | | | | | | | | | | | | | | | | | | | | The ANX7447 has a sink/source control lines which can be connected to a PPC. The NX20P3483 PPC requires this control to set it's sink/source switch control. The ANX7447 contols these lines via the tcpci COMMAND register. This CL adds new tcpm_set functions to set either SNK or SRC control via the COMMAND register. BUG=b:77583452 BRANCH=NONE TEST=Tested on port 0 of Yorp with an external charger. Prior to this CL the PPC would remain in standby state because both snk/src control remained low. With these changes, verifed that snk_ctrl is driven high and vbus_sink_enable() function no longer returns an error. Change-Id: Icbea0d3edb63ad19f3d2c76636208497b6939a72 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/996239 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: add more USB-C power logicJett Rink2018-04-103-14/+106
| | | | | | | | | | | | | | | * TCPC reset * PPC input charging (current/voltage limits) * PPC output charging * VBUS presence detection BRANCH=none BUG=b:74127309,b:77458917,b:77579760 TEST=yorp C1 can negotiate 20V at 3A Change-Id: Ifa84071be1617a060a217d00bc102d836edffe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/991081
* Add nocturne_fp board configurationVincent Palatin2018-04-101-0/+1
| | | | | | | | | | | | | | | | | Just alias it for now. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:77836478 TEST=make BOARD=nocturne_fp CQ-DEPEND=CL:1004735 Change-Id: I81a956213c626be19b48a4e8ee6f6c23e8e391e4 Reviewed-on: https://chromium-review.googlesource.com/1004755 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* gsctool: add support for CCD infoVadim Bendebury2018-04-101-10/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new option allows to retrieve CCD information from the device. It is reported similar to the way it is reported on the Cr50 console with a few deviations: - current capability setting is spelled out (instead of stating that it is at default); - default capability setting is reported only if it is different from the current value. - a bitmap of enabled capabilities is added in the end for ease of verifying CCD state during factory process. BRANCH=cr50, cr50-mp BUG=b:72718383 TEST=ran the command on a Coral device: $ gsctool -a -I State: Locked Password: None Flags: 000000 Capabilities, current and default: UartGscRxAPTx Y Always UartGscTxAPRx Y Always UartGscRxECTx Y Always UartGscTxECRx - IfOpened FlashAP - IfOpened FlashEC - IfOpened OverrideWP - IfOpened RebootECAP - IfOpened GscFullConsole - IfOpened UnlockNoReboot Y Always UnlockNoShortPP Y Always OpenNoTPMWipe - IfOpened OpenNoLongPP - IfOpened BatteryBypassPP Y Always UpdateNoTPMWipe Y Always I2C - IfOpened FlashRead Y Always CCD caps bitmap: 0x16607 - then took the device through 'ccd open' sequence and tried again, observed that all capabilities were set to 'Y' and caps bitmap was set to 0x1ffff. - then on the Cr50 console modified UnlockNoShortPP capability to be set 'UnlessLocked', ran the command again, observed the default value (Always) reported. - locked the CCD on Cr50 console, ran the command one more time: $ gsctool -a -I State: Locked Password: None Flags: 000000 Capabilities, current and default: UartGscRxAPTx Y Always UartGscTxAPRx Y Always UartGscRxECTx Y Always UartGscTxECRx - IfOpened FlashAP - IfOpened FlashEC - IfOpened OverrideWP - IfOpened RebootECAP - IfOpened GscFullConsole - IfOpened UnlockNoReboot Y Always UnlockNoShortPP - UnlessLocked (Always) OpenNoTPMWipe - IfOpened OpenNoLongPP - IfOpened BatteryBypassPP Y Always UpdateNoTPMWipe Y Always I2C - IfOpened FlashRead Y Always CCD caps bitmap: 0x16207 Change-Id: I0fd5e6bd9402ae518e3f2a3ed82589f8696dfd44 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/999826 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: add vendor CCD subcommand to report CCD informationVadim Bendebury2018-04-102-53/+122
| | | | | | | | | | | | | | | | | | | | | | | It is important for the OS to be able to find out the state of CCD and current capabilities settings of the device. This patch defines a structure to use to report information about CCD state from Cr50 to the host and adds a CCD vendor subcommand to allow to retrieve the information from Cr50. Some structure and variable definitions had to be moved into the .h file to make it possible to share them between Cr50 and gsctool. BRANCH=cr50, cr50-mp BUG=b:72718383 TEST=with the following patch applied verified that CCD info is properly reported. Also verified that other CCD subcommands still work as advertised. Change-Id: I4a783e6817ed364b9e64522ebbe968d4a657a84c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/999825 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpc: verify that i2c_read for vbus succeedsJett Rink2018-04-101-3/+5
| | | | | | | | | | | | | | | | If we cannot contact the TCPC, then we need to assume the safer value of VBus level (i.e. off) BRANCH=none BUG=b:77458917 TEST=yorp C1 still works Change-Id: I1fc1898a7dc554d050cd3612616531cb74de7261 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/995959 Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* FIXUP: driver: lsm6dsm/lsm6dsl: Add FIFO supportGwendal Grignou2018-04-101-0/+2
| | | | | | | | | | | | | | | Returns an error if the ODR set is less than 13Hz instead of silently put the sensor in suspend mode. BUG=b:77601149 BRANCH=None TEST=Check with accelrate we get an error instead of "Data rate for sensor 0: 0" Change-Id: Iead740f4205bbce1cfbccf2407f2a3a0dcf0ddaf Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000399 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* FIXUP: meowth: Add Gyro/FIFO supportGwendal Grignou2018-04-102-2/+1
| | | | | | | | | | | | | Remove SPI define, set EC period properly. BUG=None BRANCH=none TEST=check accel and gyro data. Change-Id: Ic2af6ca9721d127867a39b76e80aa396403a628d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/999815 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cleanup: CONFIG_USB_PD_CUSTOM_VDM is not usedDivya Sasidharan2018-04-0931-39/+0
| | | | | | | | | | | | | | | | | | | The pd_custom_vdm is called in common/usb_pd_protocol no matter you have this defined or not. No where else I see pd_vdm being used. So we should not have to deal with this CONFIG_USB_PD_CUSTOM_VDM. BUG=None BRANCH=None TEST=make buildall -j Change-Id: I4e8b710240ee27b12625d797e7824f29044e6462 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/998520 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Touch watchdog during initDuncan Laurie2018-04-091-0/+4
| | | | | | | | | | | | | | | | | | Touch the watchdog during init to prevent it from firing prematurely during HOOK_INIT processing before the tasks are started and watchdog_reload() will be called with HOOK_TICK. BUG=b:77336348 BRANCH=eve,poppy,fizz,reef,kevin TEST=run stress test for several days: while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done Change-Id: I79e744a4678ab1808870d0e7647d2ce273ddeb8f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/1001532 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* bip: add initial power sequence usb-pdJett Rink2018-04-097-17/+767
| | | | | | | | | | | BRANCH=none BUG=b:75972988,b:76218141 TEST=buildall Change-Id: I8d03f10828821c6d8e096d882db9f82cc901003a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982562 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nautilus: Support tristate board id strapping pinPhilip Chen2018-04-092-0/+29
| | | | | | | | | | | | | | | | | | | | | With 3 binary strapping pins, we only have 7 available board ids: 000, 001, 010, 011, 100, 101, 110, 111. Let's make the MSB of board id tristate. So we can have 4 more board ids to use: Z00, Z01, Z10, Z11. BUG=b:77731277 BRANCH=poppy TEST=build nautilus Change-Id: I7aebb89437d2ccb9eea6c477155b25d964983232 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1000875 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: watchdog: disable ITIM16 before updating ITCNT registerMulin Chao2018-04-091-0/+2
| | | | | | | | | | | | | | | | | | | | | During watchdog initialization, the driver doesn't disable ITIM16 module which used for detecting watchdog timeout before updating new preload value. Although the ITEN bit on reset is zero, it caused preload value is not updated to module successfully since ITEN won't be reset (ITIM16 is still enabled) in sysjump case. Despite WDCNT will be reloaded by touching watchdog in HOOK_TICK hook function later, it's better to disable any ITIM16 module before updating ITCNT register. BRANCH=none BUG=b:77336821 TEST=No build errors for npcx5 series. Change-Id: I19baa47bca347b9dca2fc1dcaacca81519facf21 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/999458 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: add Make variable for controlling blob swappingVadim Bendebury2018-04-071-0/+5
| | | | | | | | | | | | | | | | | | | The upcoming cr50-codesigner change will allow to use it for swapping arbitrary blobs in the Cr50 image before signing. Let's use this feature to replace test RMA public key with the prod one. BRANCH=cr50, cr50-mp BUG=b:73296144 TEST=with the rest of the patches in place verified that invoking make with CR50_SWAP_RMA_KEYS=1 causes swapping the RMA public key in the generated image. Change-Id: I4c9994c1a542f456b24d2066ecada9f92f1bfaf3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/996514 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* FIXUP: board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-04-071-1/+1
| | | | | | | | | | | | | | Enabled forced mode for BMI160 accelerometer on soraka by mistake. BUG=b:67112751,b:75533383 BRANCH=poppy TEST=Compile Change-Id: I429a1d527a56c371351f8248912c580f8680447f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000726 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Increase console buffer size to 4096 bytesNicolas Boichat2018-04-071-1/+4
| | | | | | | | | | | | | | | | | | | | | | | Increase the size from 1024 to 4096 to reduce the likelihood of overflows. To make space for the larger buffer, we reduce CONFIG_ACCEL_FIFO to 512 entries (from 1024 entries: saves 4096 bytes of RAM). grep shared_mem_buf build/lux/RW/ec.RW.smap Before this patch: 200c74e0 D __shared_mem_buf After this patch: 200c70e0 D __shared_mem_buf (we saved 1024 bytes of RAM) BRANCH=poppy BUG=b:77159941 TEST=Flash lux, see that we do not lose EC logs in /var/log/cros_ec.log. Change-Id: I320c370369364b280e59f490a86f057fbb502da3 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/983080 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: fix inverted logic for dead battery modeJett Rink2018-04-061-1/+1
| | | | | | | | | | | BRANCH=none BUG=b:77561535 TEST=yorp P1 can still boot without battery Change-Id: Ifa327e2989ac3dfe260b570edbc23add4910e09f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/998410 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* fpsensor: fix bug in fpcapture console commandVincent Palatin2018-04-061-1/+1
| | | | | | | | | | | | | | | | | | | Since the last update of the 'fpcapture' debug console command, the requested capture mode was ignored. Fix the 2 identically-named variables stepping on each other (dear compiler, why are you so distracted too ?) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:72360575 TEST=on ZerbleBarn, run 'fpcapture 0' and 'fpcapture 1' Change-Id: I1fefd24b988f0db8bcbb90cc3370135d01cbddee Reviewed-on: https://chromium-review.googlesource.com/999600 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* atlas: Add new boardDuncan Laurie2018-04-067-0/+1815
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on the initial code from Caveh here: https://chromium-review.googlesource.com/959861 Most things are functional, with some workarounds for P0 boards. The type-c hotplug is not working in this commit, the HPD will be run from the tcpm in the next board build. For now we might be able to get it working on P0 with some more tweaking.. The other known issue is that the battery takes ~2 seconds to come back online after a cutoff (the auto-power-on timeout is one second so the board will not power on like it should) and sometimes the battery is not responding properly on i2c and it requires an EC reset. BUG=b:75070158 BRANCH=none TEST=tested on P0 boards Change-Id: I438cb93b78d6f501426842d6cbe3d6a994563358 Signed-off-by: Duncan Laurie <dlaurie@google.com> Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982498 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* ppc: enter SNK mode before leaving dead battery modeJett Rink2018-04-051-5/+14
| | | | | | | | | | | | | | | If we don't enable the SNK mode before leaving dead battery mode (which does keep the inflow path open), then we will brown out our only source of power. BRANCH=none BUG=b:77561535 TEST=yorp can boot into ec without battery Change-Id: I095e3cb1ed466fd6497bbc9e7b6851fc92005c75 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/999024 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* rma: mark key ID volatile so that it can be replaced post compilationVadim Bendebury2018-04-051-1/+1
| | | | | | | | | | | | | | | | | | | | | Swapping binary blobs in the image post compilation/linking is not working quite as expected, because some of the const data values seem to be inlined by the compiler, the values are not looked up at run time. This happens to the RMA public key ID field, which is just one byte in size. Marking the field 'volatile' seems to be fixing the issue. BRANCH=cr50, cr50-mp BUG=b:73296144 TEST=with the rest of the patches applied public key substitution between test and prod works as expected. Change-Id: I12d5d1243e7988ab59bf3bba8cdfa46f27116bd2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/996513 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
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