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* cr50: move dev version to 0.2.3stabilize-10443.BVadim Bendebury2018-02-261-1/+1
| | | | | | | | | | | | | | | This will make sure that Cr50 images built from dev branch can take over images built from either MP or pre-MP branches. BRANCH=none BUG=none TEST=verified that it is possible to overwrite pre-MP Cr50 version of 0.2.2. Change-Id: I929cb2be857ea90c544f83160d6820c73e23c69d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/938946 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx/fan: Avoid turning on disabled fansDaisuke Nojiri2018-02-261-0/+3
| | | | | | | | | | | | | | | Fan enable state is controlled in common/fan.c. This patch prevents npcx fan driver from enabling it. BUG=b:73127788 BRANCH=none TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the fan spins in S0. Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/937941 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: make fw upgrade less chattyMarius Schilder2018-02-261-2/+1
| | | | | | | | | | | | | | | | | | When running w/ blocking usb console output (CONFIG_USB_CONSOLE_CRC) and the host is not polling the console, upgrade will fail. Signed-off-by: mschilder@google.com TEST=buildall -j8; gsctool update succeeds on mn50 BRANCH=none BUG=none Change-Id: I5c09694c146ba0fbf7562b86ab0fad0d578bc5ff Reviewed-on: https://chromium-review.googlesource.com/938392 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add rw_product_family field to signed_header.h.Jeff Andersen2018-02-261-1/+3
| | | | | | | | | | | | | | | | | This field allows multiple product families to be independently versioned and released, without risk of having one product family's image flashed to another product family's chip. BUG=b:73728151 BRANCH=none TEST=make buildall -J Change-Id: I53f5e5b1e9ac7ea19997f8d1228a568e66c43d39 Reviewed-on: https://chromium-review.googlesource.com/935759 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Nadim Taha <ntaha@google.com>
* charger/rt946x: Initialize earlierPhilip Chen2018-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | Thermal protection is by default enabled on rt946x, but we disable it in rt946x_init() and only rely on the fuel gauge to do thermal measurement. Thus when we init rt946x too late, rt946x could trigger thermal protection during boot and brown out the fuel gauge temporarily. BUG=b:72697658 BRANCH=scarlet TEST=boot scarlet rev3 w/o battery on AC and don't see VBAT drops Change-Id: I54eadd80bd4fd8a6e47309b13c4d46ee01dec04a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/933703 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* battery/max17055: Report battery presence properlyPhilip Chen2018-02-261-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | For boards using max17055 and dumb battery, we can always read battery parameters from max17055 regs, even if the read values are out of whack. So it doesn't make sense to determine battery is present because we can read these parameters from max17055. Meanwhile, we have to set CONFIG.TSEL on max17055 as early as possible because this is required for max17055 to detect battery presense. BUG=b:72697658 BRANCH=scarlet TEST=boot scarlet rev3 w/o battery on Type-C/PD chargers Change-Id: Id190f0c2aa5bcd62dbe3edccca6460bf145cff01 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/933702 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32mon: skip empty blocksVincent Palatin2018-02-261-12/+18
| | | | | | | | | | | | | | | | | | | Skip the empty blocks when writing even if they are in the middle of the firmware. This greatly improves flashing speed when the firmware contains a signature at the end of the RW. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36125319 TEST=./util/flash_ec --board=meowth_fp Change-Id: I3cd1c1bd2670be23d3d9daf9b87d9af0bdfc8963 Reviewed-on: https://chromium-review.googlesource.com/880956 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* stm32: trigger watchdog hard reset immediatelyVincent Palatin2018-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | When using the watchdog (IWDG) to perform the cold reset, set the Key register to 'RELOAD' (0xAAAA) rather than 'START' (0xCCCC) to ensure that the reset is performed immediately rather than at the end of the current watchdog period (which might be 1 to 5s away). Replace the Key register special values by their symbolic constants. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=On ZerbleBarn using a STM32H7, run 'ectool reboot_ec cold' and see the MCU rebooting immediately rather than after 5s. Change-Id: Ib49c703e3ec973389e4d774eda53f3be7ec4dd2e Reviewed-on: https://chromium-review.googlesource.com/936764 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* g: add CONFIG_USB_CONSOLE_CRCMarius Schilder2018-02-243-0/+39
| | | | | | | | | | | | | | | | | This option will cause usb console output to block and also compute a crc32. Signed-off-by: mschilder@google.com TEST=make buildall -j BRANCH=none BUG=none Change-Id: Icf66d5ddbea52008a9c97094e7c83194caa7db79 Reviewed-on: https://chromium-review.googlesource.com/936281 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ec: add crc32_ctx..() to take context parameter.Marius Schilder2018-02-236-7/+144
| | | | | | | | | | | | | | | | | | Add crc32_ctx.. functions to take context parameter. This allows for multiple instances to exist in parallel. Signed-off-by: mschilder@google.com TEST=make buildall -j8 succeeds BRANCH=none BUG=b:73832883 Change-Id: I66bbc56377eeebf01c790caad0bc4c7a51a1bc58 Reviewed-on: https://chromium-review.googlesource.com/935825 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* gsctool: add open box RMA optionVadim Bendebury2018-02-234-6/+376
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enhances the gsctool utility to allow to verify RO sections of the target AP and EC flash memory. The only command line parameter required for the new option ('O') is the file name of the target descriptors database, containing memory description sections for one or more Chrome OS devices. Memory description sections are of two types (both types could be referring AP or EC memory): - hash descriptor, this section includes the address range of the memory and one or more hash values for the contents of that address range. Multiple hashes are needed in case when the same device has mnore than one RO firmware releases in circulation. - dump descriptor, this is a request for this utility to display on the console the contents of the certain area of flash memory on the target. When this utility starts the process, the target might request that the operator confirms physical presence, in this case the utility keeps prompting the operator to press the physical presence button until DUT is satisfied, BRANCH=none BUG=b:73668125 TEST=created a descriptor database for a Robo device feeding it with values retrieved on the device by locally running spihash command on the device. Then ran this utility to verify successful hash and dump retrievals, comparing dump values with values obtained through Cr50 console directly. Created additional dummy hash variants and verified that the utility succeeds only if all matches happen at the same variant index in different hash sections. Change-Id: Ib43cf4eb642d141b7cd7f129ef412e14bd59f30b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/933545 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* gsctool: move common objects and definitions into a .h fileVadim Bendebury2018-02-232-74/+126
| | | | | | | | | | | | | | | | | | This is a lateral move allowing to share some data structures and functions previously limited to the gsctool.c scope. This will allow adding new functionality in a separate .c file, and further refactor gsctool.c which little by little became quite unwieldy. BRANCH=none BUG=b:73668125 TEST=gsctool utility still works for uploading Cr50 images. Change-Id: Ib56db3e0b983c53a228a658467a3059abcf2166e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/933543 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: add RO descriptor parserVadim Bendebury2018-02-235-2/+528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code which would parse the RO hash/dump descriptor file including a database listing expected values of hashes for various ranges of target SPI flash devices, or areas which need to be printed out (hex dumped) for operator inspection. Lines starting with '#' are completely ignored. The rest of the logical lines could actually split into multiple text lines in the file, so to separate one logical line from another at least one empty line is required. Hash descriptor database file consists of sections for various Chrome OS boards. Each board description section starts with a logical line of 4 characters which is the board ID (the same as the board's RLZ code). Each board description section includes variable number of range descriptor entries, each entry being a logical line, potentially split into multiple text lines. Each entry consists of semicolon separated fields: {a|e|g}:{h|d}:base_addr:size[:value[:value[:value...]]]] Where - the first sindgle character field defines the way the range is accessed: a - AP flash e - EC flash g - EC flash requiring gang programming mode - the second single character field defines the range type h - Cr50 returns the hash of the range d - Cr50 returns actual contents of the range (hex dump) - the third and and forth fields are base address and size of the range - ranges of type 'h' include one or more values for the hash of the range, each hash is a 64 byte hex string. Ranges of type 'd' do not include any data. All values are expressed in hex. The parser API provides functions to open the passed in hash descriptor file and find there the section for a particular board, a function to advance to the next entry in the board's section, and a function to close the file when board entries scanning is completed. When scanning the entries, the parser verifies their sanity, i.e. conformance with the above described format, that all hashes are of the right size, that there are no hashes attached to 'dump' entries and there is at least one hash attached to the 'hash' entries, and that there are no invalid characters in the hashes and address range definitions. The parser is not yet used by the gsctool, but when the new module is compiled stand alone with -DTEST_PARSER passed to the compiler, it becomes an executable which can be given the test hash database (the new file, sample_descriptor) to interpret and report success or failure. BRANCH=none BUG=chromium:812880 TEST=ran the following commands: $ gcc -DTEST_PARSER desc_parser.c -o dp $ ./dp sample_descriptor Section 1, rv 0 Section 2, rv 0 Section 3, rv 0 Unexpected data in section 4 Section 4, rv -22 Invalid hash 1 size 0 in section 5 Section 5, rv -22 Invalid hash 1 size 0 in section 6 Section 6, rv -22 Invalid hash 1 size 63 in section 7 Section 7, rv -22 Invalid hash 1 size 65 in section 8 Section 8, rv -22 Invalid hash 1 value in section 9 Section 9, rv -22 Unexpected number of variants in section 10 Section 10, rv -22 Invalid hex value 10x in section 11 Section 11, rv -22 Section 12, rv -61 $ Change-Id: I14b2754a5f6ba26b3c56ddc26d45cb4574514b69 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/923419 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* scarlet: Update battery profile for Simplo batteryPhilip Chen2018-02-231-8/+13
| | | | | | | | | | | | | BUG=b:69634899 BRANCH=scarlet TEST='battery' command shows the full cap is updated to 8734 mAh Change-Id: I090d80e7c889c044ba2dfbdf02527a0791419320 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/933861 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* g: optionally check board_id match at upgrade timeMarius Schilder2018-02-231-0/+17
| | | | | | | | | | | | | | | | | | CONFIG_IGNORE_G_UPDATE_CHECKS currently drops all upgrade checks. Now with CONFIG_BOARD_ID_SUPPORT only check for board_id match. CR50_DEV still retains full no check behavior. TEST=buildall -j8 BRANCH=none BUG=none Change-Id: I0d085a26c814cd0f35450f0a0db06fe8525ab896 Reviewed-on: https://chromium-review.googlesource.com/933589 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nautilus: Disable sensor in S5Furquan Shaikh2018-02-232-4/+5
| | | | | | | | | | | | BUG=b:73292704 BRANCH=None TEST=None Change-Id: I6f2f09232daed87fcd54a356ee13e69bfeda994c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/918381 Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Jerry Parson <jwp@chromium.org>
* ectool: Print tool versionDaisuke Nojiri2018-02-232-3/+9
| | | | | | | | | | | | | | | | | | | | | | ectool can be older or newer than the EC's firmware. The version of the tool needs to be found to debug compatibility issue. This patch makes ectool print its own version in addition to EC's version. BUG=none BRANCH=none TEST=Run 'ectool version': RO version: fizz_v1.1.7833+5a0bbd8fe RW version: fizz_v1.1.7833+5a0bbd8fe Firmware copy: RW Build info: fizz_v1.1.7833+5a0bbd8fe 2018-02-20 09:56:26 foo Tool version: fizz_v1.1.7831+d173cf4d6 2018-02-20 16:57:43 bar Change-Id: Iac641c76e450368175213ab6d277e56d43742429 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/927305 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CBI: Share common code between host tool and firmwareDaisuke Nojiri2018-02-234-60/+89
| | | | | | | | | | | | | | This patch makes EC firmware and cbi-util share the common code. BUG=b:70294260 BRANCH=none TEST=Set fields using ectool. Verify the contents by cbi command. Verify cbi-util creates the same binary as before. Verify emerge ec-utils ec-devutils pass. Change-Id: If5e65e48dd03960e0adf23ef775f67aecf785d85 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/932001
* cr50: expose spihash PP polling to the hostVadim Bendebury2018-02-232-6/+52
| | | | | | | | | | | | | | | | | | | | When running the spihash command using gsctool (as opposed to the running it from the Cr50 console), the operator needs to be prompted when the PP button needs to be pressed. This patch extends spihash command implementation by adding a new subcommand for polling physical presence. BRANCH=cr50, cr50-mp BUG=b:73668125 TEST=with the appropriate gsctool changes the user is periodically prompted to press the physical presence button, and eventually it is possible to set up spi hash access to AP and EC. Change-Id: I96aed1619d364c80a2f35ca8dc41241f1a444103 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/930568 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: refactor PP polling into a functionVadim Bendebury2018-02-231-42/+61
| | | | | | | | | | | | | | | | Both CCD and SPI_HASH commands need to enforce physical presence. This patch separates PP polling into a function which can be used by both commands. BRANCH=none BUG=b:73668125 TEST=verified that running 'gsctool -a -o' on a Robo device still allows to unlock CCD with PP enforced. Change-Id: I49abb0e56ad37664eaad7cc34de44e1ac06e2d1b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/930567 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CBI: Make cbi command dump EEPROM contentsfirmware-kbl-10431.BDaisuke Nojiri2018-02-221-16/+21
| | | | | | | | | | | | | | | | | | | | | | | Currently, cbi console command dumps the buffered contents. This patch will make the command dump the entire EEPROM. BUG=b:70294260 BRANCH=none TEST=Run cbi command on Fizz: CBI_VERSION: 0x0000 TOTAL_SIZE: 18 BOARD_VERSION: 514 (0x202) OEM_ID: 2 (0x2) SKU_ID: 0 (0x0) 43 42 49 5c 00 00 12 00 00 02 02 02 02 01 00 01 01 02 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... Change-Id: I39f3335a38eb72c95d53264ddc7386dd0910e946 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/930322 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: use single __packed definitionVadim Bendebury2018-02-225-6/+6
| | | | | | | | | | | | | | | | | | | Various parts of Cr50 code and Cr50 related utilities duplicate definition of __packed available in include/common.h. Let's use the same definition everywhere. BRANCH=cr50, cr50-mp BUG=none TEST=make buildall succeeds verified that linker generated map files for Cr50 RW are the same before and after this change. built and used gsctoo and rma_reset Change-Id: Ib91f9bbad1f6822b347f32b393630f592df80d60 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/931929 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: fix Board ID retrieval functionVadim Bendebury2018-02-211-8/+6
| | | | | | | | | | | | | | | | | | The function used to read or write Board ID value, when invoked for reading, reports the value on the console, but does not save the read value in the passed in structure. Let's always save it in the structure so that the caller of this function has access to the retrieved value. BRANCH=none BUG=chromium:812880 TEST=verified that 'gsctool -i' still operates as expected. Change-Id: I9bc713386758ca6701e6b853e042652e2f392871 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/925692 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: allow multiple source filesVadim Bendebury2018-02-212-3/+14
| | | | | | | | | | | | | | | | | | | | | | | With the upcoming extensions it would be beneficial to be able to keep gsctool functionality spread among multiple source files. The current Makefile is also not generating proper dependencies, which was fine when gsctool utility was first introduced, but is not adequate any more, and would be even more noticeable when more source files are added. In preparation let's just convert the build scheme into separately compiling .c files, generating .d files while at it, and then linking the .o files together in a separate link operation. BRANCH=none BUG=chromium:812880 TEST=verified that gsctool still builds fine and allows to update Cr50 image. Change-Id: I537bbe6bf76ac71e8d30040b276b78513d390bbf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/923418 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: fix AXI memory corruption on STM32H743Vincent Palatin2018-02-212-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15 'Reading from AXI SRAM might lead to data read corruption': """ Read data might be corrupted when the following conditions are met: - Several read transactions are performed to the AXI SRAM, - and a master delays its data acceptance while a new transfer is requested. """ We can actually hit this under a fair interrupt load and two tasks running (e.g polling with the AP with host commands while doing fingerprint image acquisitions). So apply the proposed workaround and limit concurrent read access on AXI master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD register. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor', poll in a tight loop with 'ectool fpmode'. No longer see random panics. Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576 Reviewed-on: https://chromium-review.googlesource.com/926009 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pd: retry DR_SWAP after a WAITVincent Palatin2018-02-211-1/+4
| | | | | | | | | | | | | | | | | | | | | If the other side answers our DR_SWAP request with a WAIT message (as bizarre as it might be), we want to retry later rather than giving up. Set again the PD_FLAGS_CHECK_DR_ROLE flag in order to do so. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=fizz BUG=chromium:814098 TEST=do repeated cold reset on Fizz connected to the 'interesting' USB-C screen and see the DP alternate mode negotiated. Change-Id: Icfb9fa209ce8cbe3c42c1e6946b43464544bdaea Reviewed-on: https://chromium-review.googlesource.com/921141 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* cr50: Allow spihash extension command over USBVadim Bendebury2018-02-201-0/+1
| | | | | | | | | | | | | | | Execution of this command requires physical presence on the DUT, this is why it is save to allow it over USB. BRANCH=cr50, cr50-mp BUG=chromium:812880 TEST=using modified gsctool verified that the command goes through and physical presence indication is requested Change-Id: I0aa371d8aaa5a480cc12d5d16edad8497142f4b4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/927796 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: Set ESPI_MAXFREQ based on FMCLK valueFurquan Shaikh2018-02-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should be decided based on the value of FMCLK. Since we are setting FMCLK to 30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz. This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK. BUG=b:73504527 BRANCH=fizz? TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran some reboot tests to ensure that there is no regression in boot time. Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/925843 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy/soraka: Enable VR decay for runtime and suspend S0ixFurquan Shaikh2018-02-201-48/+1
| | | | | | | | | | | | | | | | We have been using upstart script to force VR decay in runtime S0ix for a while now and haven't seen any issues. This change pushes the fix in EC so that we don't need the upstart script hack any more. BUG=b:70881268 BRANCH=None TEST=Verified by reverting upstart script that PMIC registers are programmed as required to enable VR decay in S0 and S0ix. Change-Id: I19729e907d2ae065758e69933d0b1d3e5b43d5e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856856 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: remove set capabilities from powerbtnMary Ruthven2018-02-203-68/+2
| | | | | | | | | | | | | | | | | | | | Cr50 cannot override the state of the power button. It was possible with dev cr50 chips, but the capability was removed in prod chips. Change the console command, so it is only used to get the state of the power button. Remove all of the commands used to override the power button. BUG=b:73557298 BRANCH=none TEST=none Change-Id: I99cb5e8a18dd972fba460c434364702f06a26305 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/926964 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* CBI: Update cbi-util printing formatDaisuke Nojiri2018-02-201-14/+41
| | | | | | | | | | | | | | | | | | | | | | | This patch makes cbi-util print the tag and the size of each field. It also fixes help message and adds indendation for readability. BUG=b:70294260 BRANCH=none TEST=Run the command as follows: $ cbi-util --show /tmp/cbi.bin CBI blob: /tmp/cbi2.bin TOTAL_SIZE: 18 CBI_VERSION: 0 Data Field: name: value (hex, tag, size) BOARD_VERSION: 514 (0x202, 0, 2) OEM_ID: 2 (0x2, 1, 1) SKU_ID: 3 (0x3, 2, 1) Data validated successfully Change-Id: I5f0fde4690c29c0ee58c798e8cc35bac3ed1b6f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/926781 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Nami: Read board info from EEPROMraymondchou2018-02-172-8/+10
| | | | | | | | | | | | | | | | | Eanble CONFIG_CROS_BOARD_INFO to read board info from EEPROM. 1. Change the EEPROM address to 0xa0. BUG=none BRANCH=none TEST=Read data from EEPROM. Change-Id: I81fbada6dd64627cc438d6ed405b696e442c3a83 Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/880525 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* meowth_fp: more reliable flashing sequenceVincent Palatin2018-02-171-4/+6
| | | | | | | | | | | | | | | | | | | | Release the reset of the FP MCU later after loading the proper spidev kernel module else the STM DFU bootloader is confused by the SPI state and fails half of the time. Also update the SPI device for the current board configuration. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36125319 TEST=On Meowth, run a lot of 'flash_fp_mcu ec.bin' Change-Id: I634fbc91fc5da52b07c48696594661f88338d986 Reviewed-on: https://chromium-review.googlesource.com/924284 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cr50: fix DEBUG_DRIVE commentBrian Norris2018-02-161-1/+1
| | | | | | | | | | | | | | This is the DEBUG_DRIVE register, not the DEBUG_BLOCK_OUTPUT. Copy/paste error? BRANCH=none BUG=none TEST=none Change-Id: Ic915b8675559d6f43d153f3a309becc621416dbe Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924698 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* host_command: Count suppressed host commands individuallyDaisuke Nojiri2018-02-165-23/+63
| | | | | | | | | | | BUG=chromium:803955 BRANCH=none TEST=Verify counters are printed every hour and before sysjump as follows: [12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0] Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912150
* CBI: Update cbi-util to support variable data offset & sizeDaisuke Nojiri2018-02-161-23/+72
| | | | | | | | | | | | | | | | | | | | | | | This patch makes cbi-util support variable data offset & size. BUG=b:70294260 BRANCH=none TEST=Run the command as follows: $ cbi-util --create /tmp/cbi.bin \ --board_version 0x202 --oem_id 2 --sku_id 3 --size 256 $ cbi-util --show /tmp/cbi.bin CBI blob: /tmp/cbi2.bin TOTAL_SIZE: 18 CBI_VERSION: 0 BOARD_VERSION: 514 (0x202) OEM_ID: 1 (0x1) SKU_ID: 2 (0x2) Data validated successfully Change-Id: Id290c33e8625223c8f3fa34fdf8a13ea9308c42e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/922272 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CBI: Make data offset and size variableDaisuke Nojiri2018-02-165-156/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CBI data offset and size are fixed. This patch makes them variable. Each data item consists of <tag><size><value> where <tag> is a numeric value assigned to each data item, <size> is the number of bytes used for <value>. BUG=b:70294260 BRANCH=none TEST=Use 'ectool cbi set' to set board version, oem, sku. Verify the contents by cbi console command and ectool cbi get. 1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2) 2. ectool cbi set 1 1 1 (write oem id of size 1) 3. ectool cbi set 2 2 1 (write sku id of size 1) 4. ectool cbi get 0 514 (0x202) 5. ectool cbi get 1 1 (0x1) 6. ectool cbi get 2 2 (0x2) 7. Run cbi console command: CBI_VERSION: 0x0000 TOTAL_SIZE: 18 BOARD_VERSION: 514 (0x202) OEM_ID: 1 (0x1) SKU_ID: 2 (0x2) 43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02 01 02 Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/920905 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* meowth_fp: update pins configurationVincent Palatin2018-02-162-2/+15
| | | | | | | | | | | | | | | | | Disable the system lock (ie ignore Write-protect) until we have fully defined our secure update scheme. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:73337313 TEST=On Meowth, run 'ectool --name=cros_fp gpioget WP' Change-Id: I3323f5d1e48debae9e2ca6e18f4439e2849a3683 Reviewed-on: https://chromium-review.googlesource.com/924125 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* fpsensor: add quality test capture typeVincent Palatin2018-02-163-18/+29
| | | | | | | | | | | | | | | | | | | Add support for an additional finger image capture type used for quality testing. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575, b:71770455 TEST=On Meowth, run 'ectool --name=cros_fp fpmode capture qual' then 'ectool --name=cros_fp fpframe raw > finger_mq.bin' Change-Id: I1b9525dc2adf0b91aef2f7124803c90d6a3bb0ca Reviewed-on: https://chromium-review.googlesource.com/924124 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* grunt: Add power/battery LED supportSimon Glass2018-02-164-173/+58
| | | | | | | | | | | | | | | | | | | | | | | | Replace the current led code with an implementation that uses the new led_pwm interface. Grunt has a blue LED which we use for power and an amber LED which we use for battery. The colours used are documented in update_leds() in led_pwm.c BUG=b:71902053 BRANCH=none TEST=manual Check for the various states: * Solid Amber == Charging * Solid Blue == Charging (near full) * Fast Flash Amber == Charging error or battery not present Did not test low / critical battery Change-Id: Ie46075855ab17e6e7301025b62e57db2c596b2a4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919765 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* grunt: Add pull-up to EC_BATT_PRES_ODL GPIOEdward Hill2018-02-161-1/+1
| | | | | | | | | | | | | | | | The EC_BATT_PRES_ODL is an open drain signal. The SN74LVC1G07 IC which drives that signal is an open drain buffer. There is no external pull. Therefore, an internal pullup is required. BRANCH=none BUG=b:73286869 TEST=gpioget shows 0 with battery and 1 without Change-Id: I98e18f54b62ddd558bedd9cec65aa003589a0681 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/923102 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Removing unnecessary register writesJett Rink2018-02-161-6/+1
| | | | | | | | | | | | | | | | | | | | According to Nuvoton datasheet, when SHM windows are in IO mode, only the bottom 16-bits of registers @ offset xF4 and xF8 are used. "This register is ignored when WRAM1_IO bit in WIN_CFG register is set to 1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This register is set to its default value by Host Domain reset." BRANCH=none BUG=none TEST=boot grunt and verify host communication still works. Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919006 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Fizz/CBI: Buid cbi-util as host-utilDaisuke Nojiri2018-02-162-33/+2
| | | | | | | | | | | | | | | This patch also removes make rules to stop producing CBI blobs. CBI blobs will be produced by another protage package. BUG=b:73123025,chromium:809250 BRANCH=none TEST=emerge-fizz chromeos-firmware-fizz and verify /build/fizz/firmware/cbi contains EEPROM images. Verify emerge ec-utils ec-devutils succeeds. Change-Id: I13744b0ab97675afa0247046bffa3edac3e62ceb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/909692
* tpm: ccd: allow alternative commands when ap is held in resetVadim Bendebury2018-02-151-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical CCD use case is when the DUT is not fully functional, or even completely dead, including corrupted AP/EC firmware. We still want to be able to enable CCD in this case, but routing CCD commands through TPM task context (necessary to ensure the large stack size some CCD commands require) is blocked if TPM was not reset after startup. Let's allow both reset requests and alternative commands when AP is held in reset after reboot. The only situation when the alternative command arrives would be the CCD use case of the system not generating TPM reset pulse at startup and the operator is trying to execute a CCD or RMA reset command. BRANCH=cr50, cr50-mp BUG=b:73292631 TEST=on a reef device: destroyed AP firmware and observed that the 'ccd open' command indeed results in the hung Cr50 console after Cr50 is reset in this state. Loaded the new Cr50 image, (which caused another Cr50 reset), successfully took it through the 'ccd open' sequence resulting in enabling AP flash write access, restored the AP flash and observed the DUT boot into Chrome OS. Change-Id: I4413bc200f5b2be563ba666ff80dd2d889ae5790 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/920924 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* led_pwm: Add a few more features to the ledtest commandSimon Glass2018-02-151-5/+10
| | | | | | | | | | | | | | | | | | | Add a way to report the current state using this command. This is useful when debugging. BUG=b:71902053 BRANCH=none TEST=manually > ledtest 0 PWM LED 0: led_id=0, auto_control=1 > ledtest 0 enable amber > ledtest 0 PWM LED 0: led_id=0, auto_control=0 Change-Id: I478980d82573b60b536ea0f4dcf324b7ccfb6fdb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919764
* grunt: Remove pull-up on UART pins.Aseda Aboagye2018-02-151-1/+2
| | | | | | | | | | | | | | | BUG=b:73135908 BRANCH=None TEST=Flash grunt; verify EC UART still functional. Reboot Cr50 a bunch without servo connected, verify that Cr50 never reports servo as "connected". Change-Id: I1ec402b4e3d0e9debdbb2af3a1ba5e1c45aa655a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917182 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: Convert spihash to TPM vendor commandRandall Spangler2018-02-152-128/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The console command now calls the vendor command to do the work. Otherwise, the same as before. BUG=chromium:804507 BRANCH=cr50 release (after testing) TEST=manual: # Sample sequence spihash ap -> requires physical presence; tap power button spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin spihash dump 0 128 -> dumps first 128 bytes; compare with image.bin spihash 128 128 -> offset works spihash 0 0x100000 -> gives a hash; doesn't watchdog reset spihdev ec spihash 0 1024 -> compare with ec.bin spihash disable # Test timeout spihash ap # Wait 30 seconds spihash 0 1024 -> still works # Wait 60 seconds; goes back disabled automatically spihash 0 1024 -> fails because spihash is disabled # Presence not required when CCD opened ccd open spihash ap -> no PP required spihash 0 1024 -> works spihash disable # Possible for owner to disable via CCD config ccd -> HashFlash is "Always" ccd set HashFlash IfOpened ccd lock spihash ap -> access denied # Cleanup ccd open ccd reset ccd lock Change-Id: Ife9335a1e402a7596d99bf515ec89ff94e8a0044 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910083 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* meowth: zoombini: enable CONFIG_CMD_PD_CONTROLCaveh Jalali2018-02-151-0/+2
| | | | | | | | | | | | | | | | we need to enable CONFIG_CMD_PD_CONTROL so the AP (depthcharge) can do TCPC firmware update. this was left disabled for bringup. BUG=b:69010531 BRANCH=none TEST=booted on meowth, was able to update TCPC firmware Change-Id: If383cff27c7b79f46f451c6380585d1300fc3413 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910322 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: set eSPI speed to max supported by hardwareCaveh Jalali2018-02-152-3/+12
| | | | | | | | | | | | | | | | | | the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up to 66MHz. so, set the max speed to whatever the hardware can actually do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's not even define it in the npcx7 case. BUG=b:72838699, b:71859563 BRANCH=none TEST="make buildall" passes; boots on meowth Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910321 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* meowth: zoombini: Remove internal pullups on UART.Aseda Aboagye2018-02-141-2/+2
| | | | | | | | | | | | | | | | | Cr50 requires no pullups on the EC UART pins. BUG=b:73135908 BRANCH=None TEST=Flash meowth; Reboot Cr50 a bunch, verify that servo is never seen as "connected". Change-Id: I88e4a2e510c1c795f2b240c3d742a7466acf696b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917181 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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