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* charger/rt946x: Disable charge timerPhilip Chen2018-02-142-0/+9
| | | | | | | | | | | | | | | | | If the charge timer expires, rt946x would stop charging. We don't need this function. BUG=b:72571372 BRANCH=scarlet TEST=read reg 0x12 and confirm TMR_EN == 0 Change-Id: I38137ac39c7e7dfd15f12342428708697f81922c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/915501 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* signer: advance to new version number and erase new bit in the rollback mapVadim Bendebury2018-02-132-4/+4
| | | | | | | | | | | | | | | | | | | This will prevent earlier released images from running on the device unless Info1 is erased. BRANCH=cr50, cr50-mp BUG=b:70891959 TEST=verified that two bits in the rollback mask have been erased now: > sysinfo Reset flags: 0x00000800 (hard) [...] Rollback: 2/2/128 Change-Id: Ic345c79010fbe0e075e14e652ea1eba263226ab1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/916737 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: move to prod RMA keyVadim Bendebury2018-02-131-6/+7
| | | | | | | | | | | | | | | The new key ID is set to zero. BRANCH=cr50, cr50-eve BUG=b:70891959 TEST=verified that prod server properly responds to the challenge generated by a CR50 running on Robo device. Change-Id: I1e0da4a2cebca7f985c5f2a6da509c850924a874 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/915503 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Michael Tang <ntang@chromium.org>
* npcx: do not power down eSPI when enabledCaveh Jalali2018-02-122-4/+11
| | | | | | | | | | | | | | | | | | | | if we're using eSPI for connectivity to the AP, we should never power it down... powering it down just causes transient errors on eSPI. BUG=b:72838699 BRANCH=none TEST=booted on meowth, no more eSPI bus errors. Change-Id: I737a03bb745868c7e8e02ffd5607db4d2da74c30 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910320 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* power_button_x86: Honor power_button_pulse setting on sysjumpFurquan Shaikh2018-02-121-2/+7
| | | | | | | | | | | | | | | | | | | On sysjump, if power button is held down, first check power_button_pulse_enabled setting to decide if powerbtn to pch should be asserted. This is important to prevent accidental shutdowns when user is attempting to do an EC reset with Vup+Pwr held down. BUG=b:73129177 BRANCH=None TEST=Verified following: 1. Reset EC by holding Vup+Pwr. 2. Keep holding Vup+Pwr until AP reaches depthcharge. 3. Ensure that AP does not shutdown. Change-Id: I0375fc8e8baabb40807dfdc6d4c9fa70c9b3b87d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912364 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usb-pd: Apply Vconn before Vbus as per USB TypeC spec (v 1.3)Jett Rink2018-02-121-7/+16
| | | | | | | | | | | | | | | | | | According to table 4-25 in USB TypeC spec version 1.3, Vconn should be sourced before Vbus or within 2ms. On Grunt I am see tVconnON around 2.3 ms, which is out of spec. We can simply source Vconn first to comply with spec. BRANCH=none BUG=b:72811851 TEST=Grunt's tVonnOn is now <2ms Change-Id: I52ca6a52bf576487061b2c33f348edf58eb06ca0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911928 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* grunt: Disable system power (_A rails) in G3Edward Hill2018-02-122-34/+49
| | | | | | | | | | | | | | | | | | | | | | EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A. These should be off in G3 and on in S5 and higher. VGATE (S0 power) is pulled high in G3 when SPOK (system power, S5) is low because PP5000_A turns off, so add a check for this and only pass through high VGATE when SPOK is also high. Leave kahlee behavior unchanged (power stays on in G3). BUG=b:72744306 BRANCH=none TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3 Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/904729 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* eve: Use PCH ACOK signal to control Deep Sleep entryDuncan Laurie2018-02-123-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deep Sleep states (DS3, DS5) are a special mode of the Intel PCH chipset that has very limited wake capabilities and breaks a number of common user expected behahviors. In particular, when in Deep S3 the USB ports are turned off and cannot continue to charge, wake the system, or maintain their internal state as they will lose 5V power. This is particularly painful with gnubby devices as they will need unlocked after every DS3 suspend/resume cycle. The only external signal that the PCH uses to determine whether or not to enter Deep Sx states is the ACPRESENT (aka ACOK) pin. Currently this pin is simply buffered from the charger and will be asserted whenever a charger is connected. This change extends the EC control over the pin to also assert ACPRESENT if either Type-C port is currently supplying VBUS. Now when a USB device is inserted the system will be enter S3 state, but not go into Deep S3 state. This allows the USB device to continue to charge, maintain it's internal state, and wake the system. BUG=b:64406191 BRANCH=eve TEST=verify GPIO_PCH_ACOK pin from the EC in different scenarios and test that system goes into S3 or DS3 state as expected: 1) no charger, no USB device: ACOK not asserted, DS3 enabled 2) charger but no USB device: ACOK asserted, DS3 disabled 3) no charger but USB device: ACOK asserted, DS3 disabled 4) charger and USB device: ACOK asserted, DS3 disabled Change-Id: I1cd132459194382e418970d29b1b195d8132cfad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/896164 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Enable hibernate using silegoElthan_Huang2018-02-125-12/+14
| | | | | | | | | | | | | | | | | | | | Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the EC. Thus, we don't use the internal hibernate/wake-up feature in npcx. BUG=b:72641658 BRANCH=none TEST=Test system will shutdown and doesn't auto wake up when type hibernate in ec console. And wake up by AC plugin, LID open, or power button. Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4 Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/890569 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* grunt: Turn PP1800_SENSOR off in S5Edward Hill2018-02-092-1/+19
| | | | | | | | | | | | | | | | | Disable sensor power (lid accel, gyro) in G3+S5. Enable it in S3+S0. We want it on in S3 for calculating the lid angle (needed on convertibles to disable resume from keyboard in tablet mode). BUG=b:72741289 BRANCH=none TEST=GPIO_EN_PP1800_SENSOR =0 in G3+S5 and =1 in S3+S0 Change-Id: I043b880b9fbd44242df0d2ac01c92a066d6b4377 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912452 Reviewed-by: Lann Martin <lannm@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/mchp: Default SPI image script verobse output to disabledScott Worley2018-02-092-44/+73
| | | | | | | | | | | | | | | | | Disable MCHP chip Python SPI image generator verbose output. Verbose output only enabled if V=1 passed on make command line. Implemented by importing print as function and overloading. BRANCH=none BUG=810731 TEST=Build mchpevb1 with command line V unset, V=0, and V=1. Change-Id: I3da02b97796a8fe95f5e54634b84c962e14a19bf Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/911749 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb-pd: Clear active contract bit before browning out systemJett Rink2018-02-091-1/+6
| | | | | | | | | | | | | | | | In the case where we are resetting Vbus and it is our only power source, then we will brown out before we set the active port to 0. BRANCH=none BUG=none TEST=Did a cold reset on grunt with no battery power. System booted as normal. Change-Id: I3823af6b0475e4cf8abbe12dd8ae4ceef26d1eab Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911613 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* grunt: Making control of SCI and SMI interrupt pins more clearJett Rink2018-02-091-2/+5
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I82d0a68f192fdc339af8682b99781cb16802ac32 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911590 Reviewed-by: Edward Hill <ecgh@chromium.org>
* sn5s330: Disable vSafe0V interruptsEdward Hill2018-02-091-10/+11
| | | | | | | | | | | | | | | | | | | | | | | Turn off vSafe0V interrupts. They were not being handled or cleared causing the interrupt line to be stuck low after unplugging a USB device. Also don't use read-modify-write for INT_STATUS_REG4 since this would clear the dead battery mode bit before it has been checked. BUG=b:73076662 BRANCH=none TEST=unplug USB device, see USB_C1_SWCTL_INT_ODL=1 TEST=USB2 mouse can be connected multiple times, PPC VBUS detection works, BC1.2 chip turns on and off correctly (USB_C1_BC12_VBUS_ON_L). Change-Id: I96980ee330dd6e5f98e447e5e87f11dd60768a5d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/909549 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* meowth_fp: put fingerprint code in RW onlyVincent Palatin2018-02-094-7/+70
| | | | | | | | | | | | | | | | | | | | | | | | | Configure the fingerprint to be compile only in the RW partition for size reason, and keep the RO for firmware update only. Enable the RW signature to jump automatically to RW. The dev key was generated with the following command: openssl genrsa -3 -out board/meowth_fp/dev_key.pem 3072 Enable the new STM32H7 internal flash support along the way. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=run on ZerbleBarn and see the firmware jumping to RW, then run 'fptest' console command and get a proper capture. CQ-DEPEND=CL:*552559 Change-Id: Icc894b8a59b255b4c6a139f177e99d0fde7c4e19 Reviewed-on: https://chromium-review.googlesource.com/880955 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scarlet: shutdown PP900_S0 power rail when S3Lin Huang2018-02-091-2/+2
| | | | | | | | | | | | | | | | | | | we need to shutdown PP900_S0 power rail when S3 to save power consumption, let's do it. BUG=b:62644399 BRANCH=none TEST=run suspend_stress_test, it pass 1000 cycles CQ-DEPEND=CL:890228 Change-Id: I366effe9d2a99cb608069dd5d599171d32a9b4ce Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/841902 Commit-Ready: Brian Norris <briannorris@chromium.org> Tested-by: Derek Basehore <dbasehore@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* charge_state_v2: No base/lid power transfer in S0ix/S5Nicolas Boichat2018-02-091-0/+10
| | | | | | | | | | | | BRANCH=none BUG=b:71881017 TEST=Suspend system, see that base does not provide power to lid, and vice-versa. Change-Id: I54e26c9b8decff2afdebc34adb62d4f5cef18e37 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/882524 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* battery: Allow 2 batteries to be fetched via ACPINicolas Boichat2018-02-095-15/+159
| | | | | | | | | | | | | | | | | | | | | We share the same shared memory fields for both batteries. When the host wants to switch battery to read out: - The host sets EC_ACPI_MEM_BATTERY_INDEX to the required index - EC then swaps the data is the shared memory fields, then update EC_MEMMAP_BATT_INDEX - Host waits for EC_MEMMAP_BATT_INDEX to have the required value, then fetches the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. TEST=Unplug base, BAT1 goes away, replug, BAT1 comes back. Change-Id: Icce12f9eef2f6f8cde9bae0a968a65e1703d0369 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/888382 Reviewed-by: Gwendal Grignou <gwendal@google.com>
* stm32: add internal flash support for STM32H7 familyVincent Palatin2018-02-096-8/+564
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32H7 family has 2 banks of flash (with 2 hardware controllers able to do 2 parallel operations at the same time). Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB variants). The flash can only be written by 256-bit word (with an additional 10-bit ECC computed by the hardware). For the flash write-protection, we cannot use our 'classical' PSTATE scheme as the erase-blocks are too large (128-kB) to dedicate one to this and the embedded word in the RO partition would not work as the flash has ECC and triggers bus-fault when the ECC is incorrect (which includes the case where the 256-bit word is written a second time). So we will do the following: - use the RSS1 bit in the option bytes as the Write-Protect enabled bit. - if the WP GPIO is set, lock at startup the option bytes until next reboot. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC console. Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6 Reviewed-on: https://chromium-review.googlesource.com/901423 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Fix shmalloc unit testVincent Palatin2018-02-092-2/+2
| | | | | | | | | | | | | | | | | | | | | We want to build the shmalloc common code in test mode *only* for the shmalloc test not for all test binaries (which are missing the helper functions). The previous version was broken for any board declaring CONFIG_SHMALLOC (but none were excepted cr50 which has tests disabled) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=emerge-meowth chromeos-ec Change-Id: Ic89c74569fbadbc75d9090b084adab8f40ddfa5d Reviewed-on: https://chromium-review.googlesource.com/909210 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add SPI hashing commandRandall Spangler2018-02-083-24/+487
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows hashing or dumping SPI flash from the Cr50 console even on a locked device, so you can verify the RO Firmware on a system via CCD. See design doc: go/verify-ro-firmware (more specifically, "Cr50 console commands for option 1") BUG=chromium:804507 BRANCH=cr50 release (after testing) TEST=manual: # Sample sequence spihash ap -> requires physical presence; tap power button spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin spihash 0 128 dump -> dumps first 128 bytes; compare with image.bin spihash 128 128 -> offset works spihash 0 0x100000 -> gives a hash; doesn't watchdog reset spihdev ec spihash 0 1024 -> compare with ec.bin spihash disable # Test timeout spihash ap # Wait 30 seconds spihash 0 1024 -> still works # Wait 60 seconds; goes back disabled automatically spihash 0 1024 -> fails because spihash is disabled # Presence not required when CCD opened ccd open spihash ap -> no PP required spihash 0 1024 -> works spihash disable # Possible for owner to disable via CCD config ccd -> HashFlash is "Always" ccd set HashFlash IfOpened ccd lock spihash ap -> access denied # Cleanup ccd open ccd reset ccd lock Change-Id: I27b5054730dea6b27fbad1b1c4aa0a650e3b4f99 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/889725 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tcpm/fusb302: Wake charger task on VBUS level changePhilip Chen2018-02-081-0/+1
| | | | | | | | | | | | | | | | | We need to wake up charger task right after AC is plugged so that the charge state can be updated immediately. BUG=b:71520398 BRANCH=none TEST=Confirm charger task wakes up immediately when AC is plugged in a Scarlet in G3. Change-Id: I4a65b3da363cdc204b800bd300824dae616770cb Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/869419 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mchpevb1: Add remaining board filesScott Worley2018-02-083-0/+803
| | | | | | | | | | | | | | | | | Add Microchip EVB plus SKL RVP3 remaining board files for battery, LED, and USB PD. BRANCH=none BUG= TEST=Review only. CQ-DEPEND=CL:840654,CL:841022 Change-Id: I34ccb33eb44e73ab841f96f4733bfe419b095678 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/841043 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mchpevb1: Add MCHP EVB board build filesScott Worley2018-02-084-0/+581
| | | | | | | | | | | | | | | | | | | | | Add Microchip MEC17xx eval board build makefile rules, GPIO file, and tasklist. EVB connected to Intel SKL RVBP is eSPI mode. EVB has smart battery and temperature sensor on I2C and a BMI160 gyro connected to GPSPI0. BRANCH=none BUG= TEST=Review only. CQ-DEPEND=CL:841022,CL:841043 Change-Id: Ie17b896766b80130e3cf2812f6239030027983d8 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/840654 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mchpevb1: Add mchpevb1 board filesScott Worley2018-02-082-0/+1582
| | | | | | | | | | | | | | | | | Add Microchip EVB plus SKL RVP3 main board files. BRANCH=none BUG= TEST=Review only. CQ-DEPEND=CL:840654,CL:841043 Change-Id: I2f3cc33989e911c464f761374c0d2d26b054b7d7 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/841022 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz: Execute PMIC reset before vboot_mainDaisuke Nojiri2018-02-083-1/+14
| | | | | | | | | | | | | | | | | | | When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb-pd: Adding port number to debug messagesJett Rink2018-02-081-15/+15
| | | | | | | | | | | | BRANCH=none BUG=none TEST=verified debug message on grunt Change-Id: Ibc1632d22b6e4bbc5b95c140db4a7cfb536687c8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/907417 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Fizz: Update thermal table by projectRyan Zhang2018-02-082-14/+53
| | | | | | | | | | | | | | | | | | | | | | | | | 1. Prochot/Shutdown Point a. Prochot on: >=81C, off: <=77C b. Shutodwn: >=82C 2. custom fan table There are three projects sharing two tables, and use Kench & Teemo's table before getting correct OEM ID because it raises fan speed quicker than the other one. a. Kench & Teemo & default b. Sion BUG=b:70294260 BRANCH=master TEST=EC can get two fan tables with different cbi value. Change-Id: Ie1bffbcf5c353a9aae5806f6c2b41554eed22b7d Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/886121 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* whiskers: Disable keyboard/USB interface when magnet sensor activeNicolas Boichat2018-02-084-3/+23
| | | | | | | | | | | | | | BRANCH=none BUG=b:72722179 TEST=lidopen/lidclose, see that USB interface is getting enabled/disabled TEST=Close/open sensor with a magnet, see that USB interface is getting enabled/disabled TEST=Boot with sensor open, USB interface is on Change-Id: Ic738fa2f2adea03cd29914bb5fc96a1fa6834122 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/894783 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lpc: Prevent watchdog reset caused by KBC IBF interrupt on chromebox.Mulin Chao2018-02-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc driver doesn't declare KBC IBF/OBE ISRs for these events. If host put data in ec's KBC input buffer unexpectedly, exception_panic() will be executed in default_handler. Then we will see ec print "=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without any hard fault and reset. This CL fixed this symptom by turning off KBC if there is no KEYPROTO task. We also run suspend stress test on fizz and no watchdog reset symptom occurred. BRANCH=none BUG=b:72353876 TEST=No build errors. Run suspend stress test on fizz and no watchdog reset occurred. Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/899706 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* Fizz: Monitor input current (version 2.0)Daisuke Nojiri2018-02-083-82/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fizz has three FETs connected to three registers: PR257, PR258, PR7824. These control the thresholds of the current monitoring system. PR257 PR7824 PR258 For BJ (65W or 90W) off off off For 4.35A (87W) on off off For 3.25A (65W) off off on For 3.00A (60W) off on off The system power consumption is capped by PR259, which is stuffed differently depending on the SKU (65W v.s. 90W or U42 v.s. U22). So, we only need to monitor type-c adapters. For example: a 90W system powered by 65W type-c charger b 65W system powered by 60W type-c charger c 65W system powered by 87W type-c charger In a case such as (c), we actually do not need to monitor the current because the max is capped by PR259. AP is expected to read type-c adapter wattage from EC and control power consumption to avoid over-current or system browns out. The current monitoring system doesn't support less than 3A (e.g. 2.25A, 2.00A). These currents most likely won't be enough to power the system. However, if they're needed, EC can monitor PMON_PSYS and trigger H_PROCHOT by itself. BUG=b:72883633,b:64442692,b:72710630 BRANCH=none TEST=Boot Fizz on 60W/87W/BJ charger. Verify GPIOs are set as expected. Change-Id: Ic4c0e599f94b24b5e6c02bbf1998b0b89ecad7bf Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/900491 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fizz: Uprev board version to 2.2Daisuke Nojiri2018-02-081-1/+1
| | | | | | | | | | | | | | This patch sets the board version for CBI blob to 2.2. BUG=none BRANCH=none TEST=Boot Fizz. Change-Id: Ibbb4083b82af3803d06bbdd157b16b369f7f6784 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/905403 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver/led/lm3630a: Disable Bank B, avoid race setting brightnessNicolas Boichat2018-02-071-9/+8
| | | | | | | | | | | | | | | | | | | | It is not necessary to enable Bank B, as we do not use it. Also, we have seen a race between enabling the banks and writing the brightness register to 0xFF, where the chip would reset the value after it has been set by EC. Adding a short 100us sleep fixes the issue. BRANCH=none BUG=b:69379749 TEST=Flash whiskers, pwm 0 50 works, even after a cold reset. Change-Id: Ic523a2475c3874c8433eb1b39e927793dd893e8f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/906165 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Benjamin Gordon <bmgordon@chromium.org>
* flash_ec: iteflash: modify processDino Li2018-02-071-0/+13
| | | | | | | | | | | | | | | | | | With this change, we can do flashing via flex cable. BRANCH=none BUG=b:35573714 TEST=To run "~/trunk/src/platform/ec/util/flash_ec --board=reef_it8320" and flashing is done and cold reset automatically. CQ-DEPEND=CL:855978 Change-Id: I078afa6d6f6f8f7bf60a1677e4c357dbe906e7dc Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/344481 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: prepare for pre-pvt images' revision bumpVadim Bendebury2018-02-082-2/+2
| | | | | | | | | | | | | | This will allow to make differences between pre-pvt and mp images better visible. BRANCH=cr50 BUG=none TEST=none Change-Id: I3abf24443a208482167231d93983b8edcace5f55 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/907170 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* rma: enable WP on RMA disableVadim Bendebury2018-02-083-6/+31
| | | | | | | | | | | | | | | | | | When RMA procedure is completed WP needs to be enabled back. BRANCH=cr50, cr50-mp BUG=b:37952913, b:73075443 TEST=on a Robo device, verified that WP is enabled, took the device through RMA unlock, verified that WP is disabled, took the device through RMA disable, verified that WP is enabled again. Also confirmed that after RMA is disabled WP status follows the battery. Change-Id: Iad6af7d16aadcd10d580f709aeb942cf508a8489 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/905926 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm: set waiting task ID earlier.Vadim Bendebury2018-02-071-3/+10
| | | | | | | | | | | | | | | | | | The TPM task is running on a higher priority than the hook task invoking TPM reset for RMA purposes. The waiting task ID value needs to be set before TPM task is signaled to reset. BRANCH=cr50, cr50-mp BUG=b:37952913 TEST=with the corresponding ccd_config.c changes fully verified RMA process (not just generating and processing the challenge). Change-Id: Id112d59ae0c3fd31a32e652c6a043fc3fd3bbe07 Signed-off-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: https://chromium-review.googlesource.com/905925 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charge_state_v2: Separate update_base_battery_infoNicolas Boichat2018-02-071-30/+30
| | | | | | | | | | | | | | | Indentation in charger_task is getting out of control, let's move the logic to a new function. BRANCH=none BUG=b:71881017 TEST=Flash lux and wand, battery algorithm works as expected. Change-Id: Ife008370218f0d9eb0f96088ec144b0aba40716f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/901442 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* charge_state_v2: Store battery information in new structuresNicolas Boichat2018-02-078-98/+126
| | | | | | | | | | | | | | | | | | | On dual battery systems, this allows to keep both batteries information in similar structures. This also means that battery information can only be fetched via host commands EC_CMD_BATTERY_GET_STATIC/DYNAMIC (next CL will make it possible to fetch the information via shared memory/ACPI). BRANCH=none BUG=b:65697620 TEST=Boot lux/wand, dual-battery algorithm works, AP can fetch both battery information via host commands. Change-Id: I3c087e8f378c5cef0006f6bfe58335228a880e5b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/888381 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Fizz/CBI: Create CBI blobsDaisuke Nojiri2018-02-061-0/+27
| | | | | | | | | | | | | This patch makes make create EEPROM blobs which contain Cros Board Info. BUG=b:72949522 BRANCH=none TEST=make buildall. make BOARD=fizz cbi_kench. Change-Id: Ie4c50f4707285b44c13afc7410a5ea823a26d98e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/902822 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charger/rt946x: Set up pre-charge currentPhilip Chen2018-02-062-0/+28
| | | | | | | | | | | | | | | | We should set up pre-charge current based on the battery pack we use. By default this parameter is 150mA. BUG=chromium:809246 BRANCH=none TEST=confirm IPREC register is written correctly Change-Id: I2cb0906c74bef144d80c38b5d15519d594ed42f2 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/902945 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* meowth: zoombini: Enable PWM LED support.Aseda Aboagye2018-02-053-125/+113
| | | | | | | | | | | | | | | BUG=b:69138917 BRANCH=None TEST=Flash meowth; verify that LEDs behave as expected. TEST=Repeat above test for zoombini. Change-Id: I07ae4b4d0f62c653d3d15c493a7ece573551212a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888221 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: Add support for PWM LEDs.Aseda Aboagye2018-02-054-0/+284
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for a common framework for PWM controlled LEDs. If there are multiple LEDs, they will all follow the same pattern. The pattern is such that it follows the Chrome OS LED behaviour specification, essentially a similar version of led_policy_std.c but for PWM controlled LEDs. To use this framework, a board must do the following: - First, define the number of logical PWM LEDs which will be controlled by this common policy, CONFIG_LED_PWM_COUNT. - Then declare those logical LEDs and define the PWM channels that comprise those LEDs. (struct pwm_led pwm_leds[]). - Next, define what each color should look like (struct pwm_led led_color_map[]). By default, the colors follow the recommended colors in the LED behaviour spec, which assume an LED with a red and green channel. If a board differs or wishes to change the colors in general, they can redefine the colors (CONFIG_LED_PWM_*_COLOR) as they see fit. The colors must be one in enum ec_led_colors. These colors are the ones that can represent the charging state, SoC state, etc. BUG=b:69138917,chromium:752553 BRANCH=None TEST=make -j buildall TEST=Enable led_pwm for meowth, and verify that LEDs behave as expected. Change-Id: I945b86a7f8ed30df58d7da835d83577192548bea Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888220 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* meowth: Enable discharge on AC.Aseda Aboagye2018-02-051-0/+1
| | | | | | | | | | | | | | | This is needed for testing. BUG=None BRANCH=None TEST=Flash meowth; verify can discharge on AC. Change-Id: I1cf1149fb90077deeb940737e8d103dcec8444fe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888225 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* cbi-util: Help GCC determine that variable is initializedMartin Roth2018-02-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GCC 6.3 can't tell that we enforce the variable 'size' being set, so initialize it to 0 to make the warning go away. The code does actually verify that size is set, but not by checking the size variable itself. util/cbi-util.c: In function 'main': util/cbi-util.c:139:8: error: 'size' may be used uninitialized in this function [-Werror=maybe-uninitialized] buf = malloc(size); ^~~~~~~~~~~~ util/cbi-util.c:233:11: note: 'size' was declared here uint32_t size; ^~~~ BUG=b:72609872 BRANCH=None TEST=Build with coreboot toolchain. Change-Id: Ide41a0fce40254f2fa3a8626dec75840a728d967 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/890703 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cleanup: adding port info and timing to debug messageJett Rink2018-02-051-1/+1
| | | | | | | | | | | BRANCH=none TEST=none BUG=none Change-Id: I5639be21b285beef61e939f1c70c5ab5a14ade7e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/900305 Reviewed-by: Edward Hill <ecgh@chromium.org>
* meowth: zoombini: Add HPD support.Aseda Aboagye2018-02-052-1/+51
| | | | | | | | | | | | | | | | | The HPD pins for meowth and zoombini go from the EC to the AP. This commit drives the HPD correctly. BUG=b:72413020 BRANCH=None TEST=Flash meowth; Use a couple charge-through hubs, unplug HDMI cable, replug, verify AP sees new DP sink. Change-Id: Ie1f86378c59fc4a717edc537ff8afe01b21d9b68 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888226 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* touchpad_elan: Power off when USB is suspended without wakeNicolas Boichat2018-02-051-2/+61
| | | | | | | | | | | | | | | | touchpad can be powered off when the USB interface is disabled without setting the remote wake feature (USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be ignored anyway. BRANCH=none BUG=b:72683995 TEST=touchpad is disabled when lid is closed. Change-Id: I688fce16ab8c75330e588ec130fb2aa499fc0ed1 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/897069 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* keyboard_scan: Disable when USB is suspended without wakeNicolas Boichat2018-02-053-0/+20
| | | | | | | | | | | | | | | | Keyboard matrix scanning can be disabled when the USB interface is disabled without setting the remote wake feature (USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be ignored anyway. BRANCH=none BUG=b:72683995 TEST=keyboard matrix scanning is disabled when lid is closed. Change-Id: I0b2346cc3426b9ef51127424f9953fd5c20ecd49 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/897068 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: prepare to release 0.1.1Vadim Bendebury2018-02-052-2/+2
| | | | | | | | | | | | | | The new release will include bug fixes and new features (line RMA reset, CCD debug, management, etc.). BRANCH=cr50 BUG=none TEST=none Change-Id: I25c22d00acd734ad0b7557cb9469d8b0f4db131e Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/902423 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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