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* common: mag_cal: Re-add bias inversionstabilize-quickfix-12871.27.B-masterstabilize-12871.91.B-masterstabilize-12871.65.B-masterstabilize-12871.57.B-masterstabilize-12871.253.B-masterstabilize-12871.24.B-masterstabilize-12871.103.B-masterstabilize-12871.102.B-masterrelease-R81-12871.B-masterGwendal Grignou2020-02-122-9/+9
| | | | | | | | | | | | | | | | | | | | | | | Sensors add offset to raw value. kaza_compute calculate the bias (the hard iron) and it has to be remove from the raw value. Invert the vector in magnetometer calibration code. Fixes: 994af4a65fa7e ("common: mag_cal: update magnetometer to leverage kasa") BUG=b:144027014,b:149116125 BRANCH=none TEST=Check that after successful online calibration, value reported to the host are closer to 0 than before calibration. Change-Id: I6cfd711c82287b1c877912e85d84d2725b063cb2 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2034675 Reviewed-by: Yuval Peress <peress@chromium.org> (cherry picked from commit d60a962c3a4907d2f18c236015aef7b989e1d384) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051100 Tested-by: Yuval Peress <peress@chromium.org> Auto-Submit: Yuval Peress <peress@chromium.org>
* ps8818: fix redriver configurationDenis Brockus2020-01-314-9/+200
| | | | | | | | | | | | | | | | | | | in driver Added software IN_HPD control Added compile time optional debug in board specific tune function in usb_retimer Added gain control Added DP lane control BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: Ida0cc243413b8fa469d3edb706040535e4a3f0e0 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031645 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Juniper: Add new LGC batteryDavid Huang2020-01-312-0/+29
| | | | | | | | | | | | | | | | Add new battery: LGC KT0020G010. BUG=b:148625782 BRANCH=master TEST=Make sure battery can cutoff by console "cutoff" or "ectool batterycutoff" and resume by plug in adapter. Change-Id: I24cb91642863ab881f4debd5b61de8045d973112 Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032549 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com> Tested-by: David Huang <david.huang@quanta.corp-partner.google.com>
* kappa: enable ledDevin Lu2020-01-314-6/+77
| | | | | | | | | | | | | | | This patch is enabling led temporally for incoming build. Will add gpio control for led after CL:1712887 merged. BUG=b:146844869 BRANCH=kukui TEST=make sure led is showing amber while battery is charging. make sure led is showing white after battery was fully charged. Change-Id: I5b55bbed45360807dceca9fe2896084619fb900a Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009540 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* puff: Fix a typo in the VBUS ADC config.Sam McNally2020-01-311-1/+1
| | | | | | | | | | | | | | | Matching the SNS_PP3300 entry, the |factor_div| field should multiply by the voltage divider numerator rather than divide. BRANCH=none BUG=b:148634825 TEST=make buildall; ectool usbpdpower reports correct voltage Change-Id: I1dd654229f027852ca818410d4883bd4daab55ae Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032544 Commit-Queue: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* waddledoo: Change PP1050_ST power goodAseda Aboagye2020-01-314-13/+5
| | | | | | | | | | | | | | | | | | The power good for VCCST is actually now a digital signal as opposed to an analog signal that it used to be. This commit updates the waddledoo GPIO configuration to account for this fact. BUG=b:148169171 BRANCH=None TEST=`make -j BOARD=waddledoo`; flash waddledoo, verify EC boots okay. Change-Id: I0fe64c07705fa3652b79414a3ec451ebf7204aae Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2028354 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* driver: bmi160: Fix rounding error in set_offset() and get_offset()Ching-Kang Yen2020-01-313-8/+26
| | | | | | | | | | | | | | | | | | | | | The original set_offset() and get_offset() codes in the driver/accelgyro_bmi160 use simple divisions to write the data. The more times the set_offset() and get_offset() is used, the data will get closer to 0. Fixing it by replacing simple division to round_divide(), division that round to nearest, in the common/math_util.c. BRANCH=octopus BUG=b:146823505 TEST=Testing on octopus:ampton on branch [firmware-octopus-11297.B]. Checking the data did not rounding to 0. Change-Id: Ide9df9e32fc501e63d6f952cb8254df7662afd23 Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002998 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* jinlon: add dual fan control by ecDevin Lu2020-01-318-10/+265
| | | | | | | | | | | | | | | | This patch allows the ec to manage two fans. Currently common/thermal.c cannot monitor more than 1 fan at the same time. This CL implements a board-specific thermal policy with multiple fans. BUG=b:141259174 BRANCH=hatch TEST=thermal team verified thermal policy is expected. Change-Id: I6ababcb0795408e8062b7605bc749e23b8bde45a Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1936077 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* dratini: change thermal configuration for DVTDevin Lu2020-01-311-7/+7
| | | | | | | | | | | | | | | | | BUG=b:147792204 BRANCH=hatch TEST=manually remove dptf control then do following: make sure system shutdown when over 75 degree with temp sensor 1. make sure system shutdown when over 70 degree with temp sensor 2. make sure fan works when over 40 degree with temp sensor 1. make sure fan fully on when over 70 degree with temp sensor 1. make sure fan works when over 40 degree with temp sensor 2. make sure fan fully on when over 55 degree with temp sensor 2. Change-Id: I51de773107df248b393e04e5ee6755a06712728c Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002992 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* usb_pd TCPMv1: Maintain independent MessageID for SOP PrimeAyushee2020-01-313-9/+68
| | | | | | | | | | | | | | | | | | | This patchset enables storage of MessageId counter received from the cable plug. Since SOP*(Cable) communication and SOP(Port Partner) have separate MessageID counters, it is necessary to store separate messageIDs to avoid the the incoming packets from getting dropped. BUG=b:148481858 BRANCH=None TEST=Tested on Volteer, able to maintain separate MessageId count for SOP and SOP' communication. Change-Id: Iac2dc616f99a9e19914588e59441df8b09068afa Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2026650 Reviewed-by: Keith Short <keithshort@chromium.org>
* volteer: Enable USB4.0 modeVijay Hiremath2020-01-311-0/+3
| | | | | | | | | | | | BUG=b:140819518 BRANCH=none TEST=With Gatkex creek 3 device volteer can enter to USB4.0 mode Change-Id: Ib20c14db42cae413322ca060c961fd67088a1a09 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1984608 Reviewed-by: Keith Short <keithshort@chromium.org>
* tglrvp: Enable USB4.0 modeVijay Hiremath2020-01-311-0/+3
| | | | | | | | | | | | BUG=b:140819518 BRANCH=none TEST=With Gatkex creek 3 device TGLRVP can enter to USB4.0 mode Change-Id: If4dadf4d146f80b9f41be1fafb283c0aa5fbf2e8 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1976683 Reviewed-by: Keith Short <keithshort@chromium.org>
* Burnside bridge retimer: Add USB4 mode bitsAyushee2020-01-312-22/+37
| | | | | | | | | | | | | | | | | | | | | | | | | Intel burnside bridge retimer supports the ability to train the link and operate both USB4 Gen2(10Gbps) and USB4 Gen3(20Gbps) Adding the following fields in the configuration register of the retimer to USB4 mode: 1. Active cable - Active/passive cable 2. Cable type - Optical or Electrical 3. Active link training - Unidirectional or bidirectional link training 4. USB4 cable speed - 10Gbps/20Gbps active/passive cable 5. USB4 Generation - 3rd Generation or 4th Generation Thunderbolt cable BRANCH=None BUG=b:140819518 TEST=Able to configure the retimer in USB4 mode on TGLRVP Change-Id: I3d6bfd92eccc4881dac2b892926aafc2281e2a12 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926383 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* TCPMv1: Add support for USB4.0Ayushee Shah2020-01-319-28/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB4 is based on the Thunderbolt 3 protocol specification. It supports 40 Gbit/s throughput, is compatible with Thunderbolt 3, and backwards compatible with USB 3.2, USB 2.0. USB4.0 PD Flow: Ref: USB Type-C Cable and Connector Specification 2.0 Figure 5-1 USB4 Discovery and Entry Flow Model USB PD Explicit Contract Discover ID SOP -------- USB4 compatible? | -------------yes------------|------No----- Exit USB4 Discovery | Discover ID SOP' --------- Product type | Passive cable----------|----Active Cable---USB4? | | | (Not implemented in this CL) USB Signaling ----------------------- | | | | USB4 with USB4 active cable Exit USB4 | Discovery --------------------------------------------- | | | | USB4 Gen3 USB3.2 Gen2 USB3.2 Gen1 USB2.0 | | | | Enter USB4 with | Enter USB4 with Exit USB4 Discovery USB4 Gen3 | USB4 Gen1 Passive cable | Passive cable | DFP Gen3 capable? | ------yes---- |---------No-------- | | Discover SVID SOP Enter USB4 with USB3.2 Gen2 Passive Cable | Discover SVID SOP' | Discover Mode SOP | Discover Mode SOP' --------Is TBT3? | -----yes----|-----No---- | | Enter USB4 with TBT3 Enter USB4 with TBT Gen3 passive cable Gen2 passive cable BUG=b:140819518 BRANCH=None TEST=With Gatkex creek 3 device, TGLRVP can enter to USB4.0 mode Change-Id: Id861661c66c53a0a32679388bb7e2e81aae3ceb5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926382 Reviewed-by: Diana Z <dzigterman@chromium.org>
* ioexpander: Fix IOEX_INT after ioex_signal numbering changeEdward Hill2020-01-312-3/+4
| | | | | | | | | | | | | | | Fix ioex_is_valid_interrupt_signal() and IOEX_INT() to account for IOEX_SIGNAL_START correctly. BUG=none BRANCH=none TEST=ioex_enable_interrupt() returns success Change-Id: I8f13fa8f2d645aae565ac1062eab4a4d0968c4bc Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031649 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* flash_ec: no stderr redirection in flashrom runNamyoon Woo2020-01-301-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes stderr redirection in running flashrom to flash-size, so that flash_ec log would contain more information on error cases. It could be verbose even for success case, but flash_ec script would take the last output in number as SPI_SIZE. BUG=none BRANCH=none TEST=manually ran flash_ec with Suzy-Q and Servo_Micro on reef. - success case $ ./util/flash_ec --chip=npcx_spi --image ${IMG} --verbose INFO: EC build system didn't recognize . Assuming no baseboard. INFO: Using ccd_cr50. ... INFO: Running flashrom: sudo /usr/sbin/flashrom -p raiden_debug_spi:target=EC, serial=0580300D-91984377 --flash-size flashrom v0.9.9 : : on Linux 5.2.17-1rodete3-amd64 (x86_64) flashrom v0.9.9 : : on Linux 5.2.17-1rodete3-amd64 (x86_64) bus=0x01,address=0x43 | Cr50 INFO: Programming EC firmware image. INFO: Running flashrom: ... - failure case: servo_micro was not connected to the dut. $ ./util/flash_ec --chip=npcx_spi --image ${IMG} --verbose INFO: EC build system didn't recognize . Assuming no baseboard. INFO: Using servo_v4_with_servo_micro. ... INFO: Running flashrom: sudo /usr/sbin/flashrom -p raiden_debug_spi:serial=SNCQ03109 --flash-size flashrom v0.9.9 : : on Linux 5.2.17-1rodete3-amd64 (x86_64) flashrom v0.9.9 : : on Linux 5.2.17-1rodete3-amd64 (x86_64) bus=0x01,address=0x17 | Servo Micro No EEPROM/flash device found. ERROR: Failed to determine chip size! INFO: Restoring servo settings... dut-control --port=9999 cold_reset:off dut-control --port=9999 spi1_vref:off dut-control --port=9999 spi1_buf_en:off dut-control --port=9999 cold_reset:on dut-control --port=9999 cold_reset:off Change-Id: I642f62081e92bec68d01dcf4e2a4bb71a0131163 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031644 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* USB PD: set last rx'd msg ID as invalid before executing soft resetTim Wawrzynczak2020-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | If the last message ID received was a 0, then executing "pd N soft" on the EC shell would incorrectly mark the next message received as a repeat message. This change resets the last received message ID to the invalid value before executing the soft reset. BUG=b:146811519 BRANCH=firmware-hatch-12672.B TEST=Executing "pd 0 swap power pd 0 soft" while connected as a SNK to a servo V4 no longer results in a loop because the message was not marked as a repeat any more. Change-Id: I754d1d3ed9f7a4a5163b0f3cd4bb844f47e0ccc7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2028359 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* hatch: Use GPIO and host event when generating MKBP eventsTim Wawrzynczak2020-01-301-1/+1
| | | | | | | | | | | | | | | | | For waking the system from suspend, the plan is to use the host event (SCI) to perform the wakeup, and use the GPIO for IRQ signalling, following nocturne's example. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=with corresponding coreboot change, verify that the AP will wake on connection of a DisplayPort monitor. Change-Id: Ifcd144777b7e40941327958ccfb931c8a7137887 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031264 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* c2d2: initial c2d2 addJett Rink2020-01-309-4/+1098
| | | | | | | | | | | | | | | | | C2D2 is a debug board bring that uses an 8-pin debug header that is pin compatible with the em100 flash emulator. BRANCH=none BUG=b:145314772 TEST=UART communication for EC and H1 TEST=UART flashing of EC TEST=SPI reading and writing TEST=Automatic Vref detection for UART upon connect and disconnect Change-Id: I023994ed78942f2307e4adb802b5cc96afdf7e24 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991849 Reviewed-by: Diana Z <dzigterman@chromium.org>
* npcx: Add driver support for PS/2 interfaceCHLin2020-01-3010-6/+506
| | | | | | | | | | | | | | | | | | | | | | Morphius connects the trackpoint device to EC via the PS/2 interface. To support it, we implemented the chip level PS/2 driver in this CL. The PS/2 driver can be used on all series of NPCX EC chips (NPCX5/7). BUG=b:145575366 BRANCH=none TEST=No error for "make buildall" TEST=Apply this and related CLs, connect npcx5/npcx7 EVBs to standard PS/2 keyboards and PS/2 device emulator with different channels. Verify that the PS/2 write/read transaction can keep working for several hours without issue. Change-Id: I5bae313db2d697999c2da5cf33478be2da754b8c Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982302 Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Edward Hill <ecgh@chromium.org> Auto-Submit: CH Lin <chlin56@nuvoton.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* ps8818: allow access to all of the register pagesDenis Brockus2020-01-302-12/+93
| | | | | | | | | | | | | | | | Added possible registers that we may need to adjust and many of them are not on page0. So changed the base code to handle different pages BUG=none BRANCH=none TEST=verify different pages can be accessed Change-Id: If6a7a2e141d9c052dfa8da612b9e5268d21630a7 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2022915 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb: differentiate DTS polarity and normal device polarityDenis Brockus2020-01-306-14/+67
| | | | | | | | | | | | | | | | | When we have SNK_DTS polarity, we still want to drive both CC lines with the appropriate pull. SRC_DTS should not show as having a polarity. Non-DTS should show the correct polarity. We were only handling the last sentence of that. BUG=b:147754772 BRANCH=none TEST=verify SuzyQ works on zork Change-Id: I013f9d881427d6d97b655f88cfb3a94e3ed10c61 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2022914 Tested-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: enable the host interface mouse channelCHLin2020-01-301-2/+20
| | | | | | | | | | | | | | | | | | | | | | In Morphius, the trackpoint data is passed through EC to the host by the legacy ports (60h/64h). In this CL, we enable the host interface mouse channel (LDN = 05h). Mouse interrupt (IRQ 12) will be asserted when the trackpoint data is written to the HIMDO register. It will be de-asserted once the host reads the data via IO port 60h. BUG=b:145575366 BRANCH=none TEST=No error for "make buildall" TEST=Apply this and related CL, connect npcx EVB to host emulator. Execute console command "kbcmouse data". Make sure the host can see IRQ12 and read correct data from IO port 60h. Change-Id: I4a4e9fb6c079c164b6a5e617587dd2f2cdf55164 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003002 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* TCPMv1/v2: Move EC_CMD_USB_PD_CONTROL host command to common fileVijay Hiremath2020-01-306-287/+399
| | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: Iadb75b9b187a0444c445c2641ec71d592cf4ac92 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013228 Reviewed-by: Keith Short <keithshort@chromium.org>
* volteer: enable link time optimizationKeith Short2020-01-301-0/+1
| | | | | | | | | | | | | | | Enable LTO to save code space. BUG=none BRANCH=none TEST=make buildall TEST=verify Volteer boots and verify PD charging and type C device detection. Change-Id: Icc1684a05675f3c5b3d0fc3f75aadea63d16d3a8 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2029191 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* intelrvp: Enable PD 3.0 supportVijay Hiremath2020-01-301-0/+4
| | | | | | | | | | | BUG=b:148528594 BRANCH=none TEST=tglrvp can negotiate with TBT3 docks Change-Id: I180ebb26ad8bb4fbbb0685c16b677ce4cc2608ba Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2027754 Reviewed-by: Keith Short <keithshort@chromium.org>
* oak: enable link time optimizationKeith Short2020-01-302-2/+4
| | | | | | | | | | | | | | | | Oak board exceeds RO code size limit after changes in the TCPM stack. Enable LTO to save over 6 KiB of RO flash space. This also fixes the vbus_task() prototype which was caught by the -Wlto-type-mismatch warning. BUG=b:140819518 BRANCH=none TEST=make buildall Change-Id: I45ac0dc5e6e349281c49223453e9f6760cca6523 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2029027 Reviewed-by: Diana Z <dzigterman@chromium.org>
* waddledoo: Add chg_chips tableAseda Aboagye2020-01-292-0/+17
| | | | | | | | | | | | | | | | | | Waddledoo was boot looping due to the fact that its charger init was missing. This commit adds the chg_chips table containing the charger ICs in the system. BUG=b:147672225 BRANCH=None TEST=Build and flash waddledoo, verify that the EC no longer boot loops. Change-Id: I649cf3a4e1869eaeca69e69e96084cc17871194f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2027078 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* volteer: enable PD 3.0 supportKeith Short2020-01-291-0/+6
| | | | | | | | | | | | | | | | Enable PD revision 3.0 messages on Volteer in the TCPMv1 stack. BUG=b:148416212 BRANCH=none TEST=make buildall TEST=Volteer - verify charging on both USB-C ports. Verify superspeed devices detected by kernel. Change-Id: I143d12c61506d6933bf041b76c45357f0863da82 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2025074 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* PD 3.0: Send Reject messages for refusing swapsDiana Z2020-01-291-11/+13
| | | | | | | | | | | | | | | | | | | When refusing a PR_Swap, DR_Swap, or VCONN_Swap the Reject control message needs to be used rather than Not_supported. BRANCH=None BUG=b:64411727 TEST=tested with a PD 3.0 hub which always requests a DR_swap upon connection. Previously, it would leave its cc line at NG upon receiving the unexpected Not_supported response and it now leaves the line at OK. Change-Id: Ifafbadece5c45e51f4100be5e3590c07fcb27346 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1250023 Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* PD 3.0: Add AMS start detection to collision avoidanceDiana Z2020-01-292-110/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an explicit contract is in place for PD 3.0, the source shall control the Rp value in order to facilitate collision avoidance. When the value is set to 1.5 A, the sink can only respond to an existing AMS, and not start a new one. An Atomic Message Sequence (AMS) is defined as "a Message sequence that starts and/or ends in either the PE_SRC_Ready, PE_SNK_Ready or PE_CBL_Ready states." This means any given PD message may be starting an AMS (requiring the source to set Rp, and sink to check the CC level) or it may be a response within an AMS (in which case, sink may send regardless of CC levels). This change adjusts the pd_transmit() calls to indicate whether any given PD message is the beginning of an AMS. There are many AMS's defined, which may be found in section 8.3.2 of the PD 3.0 spec. Anytime the source returns to its ready state, it will reset Rp to reflect that the sink may start an AMS. Additionally, this removes the buffer for sending PD messages. If an AMS cannot be started, then it's better to fail the send so the pd_task state machine can handle the unsent message. BRANCH=None BUG=b:64411727, b:147476471 TEST=Tested with bip board with PD 3.0 config using 2 different PD 3.0 hubs. Monitored Twinkie output with hubs acting as source, sink, and power swapping to source. Also turned off PD 3.0 to ensure PD 2.0 behavior with the hubs was unaffected. TEST=Tested on volteer board with PD 3.0 config using Thunderbolt capable dock. Change-Id: Ib02670add1a125217a981a846e6e2c31681de169 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1246273 Tested-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* TCPMv1: Cleanup sending TBT control flags to hostVijay Hiremath2020-01-298-59/+52
| | | | | | | | | | | BUG=b:148114593 BRANCH=none TEST=tested on Volteer, able to get correct TBT control flags Change-Id: If673d4a194d3cc6b9579f0f32511c6363f2614f3 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013825 Reviewed-by: Keith Short <keithshort@chromium.org>
* spi: keep HW SPI module enabled longerJett Rink2020-01-293-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the HW SPI module is disabled (i.e. SPE bit is cleared), then the stm stops actively driving the SPI CLK signal and lets it float. This can cause spurious communication issues or guaranteed issues if there is a pullup on the CLK signal. Ensure that the CLK signal is being driven (low) for the duration of a USB SPI transaction at minimum. Driving the CLK signal low for the duration of the SPI transaction also seems to help with sporadic reliability issues on servo_micro Also add a flag that enables the SPI module to be enabled for the entire time the firmware wants to enable the SPI module opposed to needing both the firmware and the USB host to enabled the SPI module. BRANCH=servo BUG=b:145314772,b:144846350 TEST=with scope verify that SPI CLK line is help low as soon at the `enable_spi 1800` command is enter on C2D2 console and continues to stay low in between all USB SPI traffic from host. Change-Id: I9dbd6b3ebca8db6470d9ec70bae02ac8366d6c9e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995604 Reviewed-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* spi: add flags to spi configurationJett Rink2020-01-296-6/+17
| | | | | | | | | | | | | | | | Add flags field to stm and g chip usb spi configuration. This is unused for g chip, but added for consistency. BRANCH=none BUG=b:147353903 TEST=builds Change-Id: Ie2aa88ae09e8f6f4049ba13fe4565901c604b92c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995603 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Brian Nemec <bnemec@chromium.org>
* kohaku : set CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA to 6144YongBeum.Ha2020-01-291-1/+1
| | | | | | | | | | | | | | | | | Some systems fail to boot or shutdown abnormally because of discharging current. So set CONFIG_CHARGER_BQ25710_IDCHG_LIMIT_MA to 6144. BUG=b:148189096 BRANCH=firmware-hatch-12672.B TEST=On Kohaku, Update and check if failed systems work. Change-Id: I9f199d627587f7e8f3088f8f56fa1d6775bc1708 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2026330 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* waddledoo: Enable USB Type-C redriverAseda Aboagye2020-01-292-0/+11
| | | | | | | | | | | | | | | | Waddledoo is using the ON Semi NB7V904M USB Type-C redriver on its sub board; this commit enables that redriver. BUG=b:147782066, b:147257992 BRANCH=None TEST=`make -j BOARD=waddledoo` Change-Id: I976066b02f1fda8ee6228fbaa8dd4c7374dcd1ab Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018708 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* driver/retimer: Add support for ON Semi NB7V904MAseda Aboagye2020-01-294-0/+186
| | | | | | | | | | | | | | | | | This commit adds support for the ON Semiconductor NB7V904M USB Type-C Alt Mode Linear Redriver. BUG=b:147782066 BRANCH=None TEST=Enable on waddledoo, `make -j BOARD=waddledoo` Change-Id: Ia6fe76d0ad99bf7a8129e5d453ff12183990a50a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018707 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* USB-C: Move EC_CMD_GET_PD_PORT_CAPS host command to host command fileVijay Hiremath2020-01-282-43/+43
| | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: I70625ee9ffe9a3d5c6de73bd80eb5530db39bca7 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2025769 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPMv1/v2: Move EC_CMD_USB_PD_GET_AMODE host command to common fileVijay Hiremath2020-01-284-82/+119
| | | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: I0b9cb76adbc5e385cb20256f693bd2b0687b30de Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2024428 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPMv1/v2: Move EC_CMD_USB_PD_DISCOVERY host command to common fileVijay Hiremath2020-01-284-43/+39
| | | | | | | | | | | | BUG=b:142911453 BRANCH=none TEST=make buildall -j Change-Id: Ia2ad22669a908e9b9c23c4b73e97872399049e75 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2024427 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* hatch: Add board specific override for board_get_pd_port_location()Tim Wawrzynczak2020-01-281-0/+13
| | | | | | | | | | | | | Returns LEFT_BACK for port 0, and RIGHT_BACK for port 1. BUG=b:146506369 BRANCH=firmware-hatch-12672.B TEST=Verified in SSDT that the port-location property is correct Change-Id: Ib21119d8416b36dde242449bb4433e3250dfb130 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2016918 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* spi: respond to USB endpoint when SPI disabledJett Rink2020-01-281-3/+0
| | | | | | | | | | | | | | | | | If the stm has its SPI bus disabled locally, then the host request to enable or disable SPI would go unacknowledged which would ultimately crash the stm32. BRANCH=none BUG=b:147353903 TEST=execute flash rom when C2D2 is not in SPI mode and watch that C2D2 no longer crashes. Change-Id: I05d6c1519b90932a9c883c013059446c2751c892 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995602 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Brian Nemec <bnemec@chromium.org>
* puff: Change default VCCST_PG_OD to low.Sam McNally2020-01-281-1/+1
| | | | | | | | | | | | | | | | | | The EDS expects VCCST_PWRGD to remain low until VCCST and VDDQ are stable and within specification. From a fresh EC boot, this seems unlikely so default to low. BRANCH=none BUG=b:148042540 TEST=make buildall; puff cold boot succeeds consistently on a dut where it previously failed consistently Change-Id: I827714f5c4d563a205941ee2d3b2d5c781439cdb Signed-off-by: Sam McNally <sammc@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2024252 Commit-Queue: Peter Marheine <pmarheine@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org> Tested-by: Peter Marheine <pmarheine@chromium.org>
* deltaur: initial addJett Rink2020-01-285-0/+136
| | | | | | | | | | | | | | Add a bare-bones Deltaur EC image to build on BRANCH=none BUG=b:148160415 TEST=builds Change-Id: Ia8145e978c2e1d561768d3344e0b89e1c4ef2f6c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015352 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common: vec3: Add init/sub/add functionsYuval Peress2020-01-282-0/+78
| | | | | | | | | | | | | | | | Add convinience functions for initializing, adding, and subtracting vec3. BUG=None BRANCH=None TEST=buildall Change-Id: I594db350863a8199eade15a38deb6c223e2ae1ac Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869729 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* common: mag_cal: update magnetometer to leverage kasaYuval Peress2020-01-287-141/+161
| | | | | | | | | | | | | | | Update magnetometer calibration algorithm to leverage the new kasa standalone code. BUG=b:138303429,chromium:1023858 TEST=added unit test BRANCH=None Change-Id: I5c0403b66d9fe7c2925b2ec6244cf9e32ad5ea5f Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931464 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Charger: change get_vbus_voltage to return EC errorDiana Z2020-01-2815-31/+82
| | | | | | | | | | | | | | | The other driver structure members return an ec_error_list value and fill in parameters to return data. This commit changes the get_vbus_voltage call to follow that model. BRANCH=None BUG=b:147672225 TEST=builds Change-Id: I7308502a9734274dd308b830762493c4d70d147a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015340 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Charger: Remove unused charger driversDiana Z2020-01-2816-2289/+0
| | | | | | | | | | | | | | | | The driver/charger directory contains a number of charger drivers which are currently unused. As a part of the refactor of the charger drivers into a structure, remove these dead files which are no longer built. BRANCH=None BUG=b:147672225 TEST='make -j buildall' Change-Id: I89629c0cef3593954b5b6431bc29be5cc5ee6e45 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008346 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Charger: Create charger driver structureDiana Z2020-01-2822-833/+1738
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With upcoming boards which use multiple charger chips, the EC codebase needs to be changed to assume chargers may have different I2C ports. This commit creates the driver structure and wrapper functions, which for now are hard-coded to chip 0 for equivalent behavior with previous code. A general charger config is created for all boards in charger.c for now, which uses the build information to fill in the structure. All boards will default to defining CONFIG_CHARGER_SINGLE_CHIP, which in turn defines a CHARGER_SOLO which can be used by drivers which have code that needs to determine charger numbers. For boards which have multiple chips, they may undefine this config and should generate build errors if their driver is still using the hardcoded charger reference of CHARGER_SOLO. Older drivers may continue using CHARGER_SOLO in non-static functions until they're needed in a multiple charger board. For boards which may be supporting different I2C configurations for the charger over board versions, they may define CONFIG_CHARGER_RUNTIME_CONFIG to fill in these fields after boot. BRANCH=none BUG=b:147672225 TEST=builds, chargers on hatch and octopus work Change-Id: I390ede494226252e512595c48099fa1288ffe93e Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2008451 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Ensure Rd is set in Debug Accessory.SNKDiana Z2020-01-281-0/+2
| | | | | | | | | | | | | | | | | | | When tcpm_init() runs (ex. during a phy layer reset), it will cache an Open state for the CC pull. This can cause Open to be presented on the CC lines during the next call to set polarity. The Attached.SNK state already ensures Rd is set by calling set_cc explicitly, and this change adds an explicit set to Rd for Debug Accessory.SNK as well. BRANCH=None BUG=b:147316570 TEST=loaded on waddledoo, ensured CC lines weren't set to Open when suzy-q was plugged in Change-Id: I17ea735632e10c666691c04d56057c57688dcbd6 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023240 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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