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* file_lock: Add fallback directoryrelease-R51-8172.BDavid Hendricks2016-07-061-16/+27
| | | | | | | | | | | | | | | | | | | | | | | This adds a fallback directory in case SYSTEM_LOCKFILE_DIR is unavailable. Since this is a band-aid meant to help older systems auto-update, the fallback path is hardcoded to "/tmp" as to avoid polluting the overall lockfile API. BUG=chromium:616620 BRANCH=none TEST=Tested on veyron_jaq by removing /run/lock and seeing mosys, flashrom, and ectool run successfully with firmware_utility_lock in /tmp. Change-Id: Idbe63a574474ec35a5c3b6fe2b0fb3b672941492 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/348850 Reviewed-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit 4b680119cc1de2dda7c0b625c4fea1d1e964189a) Reviewed-on: https://chromium-review.googlesource.com/354780 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* Support RW_B in sysjump command when applicablestabilize-8172.47.BBill Richardson2016-04-082-2/+23
| | | | | | | | | | | | | | | | | | | | If we #define CONFIG_RW_B, the firmware image can have two RW components. This CL expands the "sysinfo" command so that we can see which image we're running from when RW_B is also a possibility. BUG=chrome-os-partner:50701 BRANCH=none TEST=make buildall; test RW update on Cr50 Using test/tpm_test/tpmtest.py, update the RW firmware and reboot several times to switch between RW_A and RW_B. Note that the "sysjump" command reports the correct image each time. Change-Id: Iba3778579587f6df198728d3783cb848b4fd199d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337664 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Add console command "usb" for testingBill Richardson2016-04-072-13/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a command to connect or disconnect, and to switch the PHY between A or B. BUG=chrome-os-partner:52055 BRANCH=none TEST=make buildall; test on Cr50 Using a test board with both PHYs plugged in, try the various commands: usb off usb on usb a usb b The on/off option connects and disconnects, the a/b option switches between PHYs. You can see the state change on the console, or by running dmesg on the host. Change-Id: I4c77e9c586ce197dc99b0b50af7396c253a1a377 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337706 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: forward console through USBMary Ruthven2016-04-072-93/+188
| | | | | | | | | | | | | | | | This change adds support for forwarding the EC console through USB. BUG=chrome-os-partner:49960 BRANCH=none TEST=load the google-serial udev rules in extra/usb_serial/, build the raiden.ko module, and then check that the console can be accessed from /dev/google/Cr50/serial/Shell Change-Id: I35e0bb39fdc8f9485a14c03eb3a4d2f024884e17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334132 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: enable AP and EC UART forwardingMary Ruthven2016-04-072-4/+11
| | | | | | | | | | | | | | | | | Cr50 will be used to debug the EC and AP through USB. This change enables exporting the EC and AP UART through USB by adding the endpoints and enabling the UART and USB streams. BUG=chrome-os-partner:50702 BRANCH=none TEST=Load the serial driver in ec/extras and verify that the EC and AP UARTs can be accessed through /dev/google/Cr50*/serial/AP and EC. Change-Id: I3249b250d0ecc41a206c45c5ca66b5a6a5622e62 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337294 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: export AP and EC UART through USBMary Ruthven2016-04-077-5/+212
| | | | | | | | | | | | | | Add support for exporting the EC and AP UARTs to USB. BUG=chrome-os-partner:50702 BRANCH=none TEST=Verify the EC and AP UARTs are forwarded to the EC and AP endpoints Change-Id: Icaeb7929dbaaf71a40f0752aa6cb5a2319373651 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336317 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add support for creating multiple serial endpointsMary Ruthven2016-04-0710-360/+461
| | | | | | | | | | | | | | | | | CR50 will need three serial endpoints for the streaming AP and EC UART and exporting its own console through USB. This change adds a macro to create endpoints that can be recognized by the usb_serial driver. BUG=chrome-os-partner:50702 BRANCH=none TEST=Verify "/dev/google/Cr50*/serial/Blob" prints capital letters when lower case letters are input. Change-Id: Iddf2c957a00dc3cd5448a6a00de2cf61ef5dd84c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336441 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Driver: BD99955: Set minimum charge current & charge voltage valuesVijay Hiremath2016-04-072-14/+8
| | | | | | | | | | | | | | | | | | | | If the charge current or charge voltage registers are set to zero then the charger cuts the power to board. BD99955 does not support 0mA charge current & 0mV charge voltage values hence set the charge current & charge voltage to charger's minimum values. BUG=chrome-os-partner:52050 BRANCH=none TEST=Manually tested on Amenia. Board can boot without the battery. Battery does not discharge when the charger current or charger voltage is sent to 0 from the charger manager. Change-Id: I8049525594d107d7ad1ff2f17e8df757ee86458c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/337404 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* chell: increase HOSTCMD task stack sizeVincent Palatin2016-04-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | Some host commands might trigger a stack overflow on HOSTCMD, let's increase the stack size for this task. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=glados BUG=chrome-os-partner:51633 TEST=run 'ectool usbpd 0 sink' and verify stack canary with 'taskinfo' Change-Id: Ida6d1656bd14c6a728a4d6624b4fe10fe4b02423 Reviewed-on: https://chromium-review.googlesource.com/334892 Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 952b20a8d7894e1c72c67ada2d25298157f51b79) Reviewed-on: https://chromium-review.googlesource.com/337306 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* Cr50: SPI tests need to poke the target to wake it upBill Richardson2016-04-061-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the Cr50 is in deep sleep, it does a full warm boot when it sees the SPS_CS_L assert. The master doesn't wait for it to boot (because it doesn't know it has to) and starts clocking in data bits right away. The Cr50 can't set up the SPS controller quickly enough to capture those bits, so the first N bits/bytes are lost and the master keeps clocking, waiting for the SPI response which it will never get. To be certain that the Cr50 is awake, this CL causes the test (master) to assert SPS_CS_L briefly, then wait a little bit for the Cr50 to wake up from deep sleep (50ms should be plenty), and THEN it can send the rest of the SPI traffic. The Cr50 won't enter deep sleep until it's been at least a second since the last SPI activity, so we don't have to worry about it going to sleep between SPI commands as long as they're not terribly far apart. The kernel driver will have to implement this same hack too, since the SPI bus doesn't have a suspend/resume protocol like the USB does. We've known this for some time. It would be nice if this weren't needed, but it's a hardware constraint. BUG=chrome-os-partner:49955, chrome-os-partner:52019, b:28018682 BRANCH=none TEST=make buildall; test on Cr50 Ensure that the Cr50 invokes sleep or deep sleep when idle (refer to previous commit messages for the setup required), then cd test/tpm_test make ./tpmtest.py Before this CL, the test hung or failed because it couldn't get a quick response from the Cr50. With this CL, the Cr50 wakes up and the test passes. Change-Id: I581475726313981a780beaaa37638e9c3b9ebec5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336837 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Makefiles should check path assumptionsBill Richardson2016-04-051-6/+11
| | | | | | | | | | | | | | | | | | | | When compiling the EC firmware outside of the chroot, some optional packages may not be installed. Let's be sure the tools exist before we try to use them. BUG=none BRANCH=none TEST=make buildall, both inside and outside of the chroot Note that to build outside the chroot, we need to 1. Use GNU make verion 4.1 or later 2. Install the gcc-arm-none-eabi package Change-Id: I78c75cb4ad658c003ded71b244b0458ae5532e0b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337341 Reviewed-by: Shawn N <shawnn@chromium.org>
* charger: bd99955: Disable BC1.2 detectionShawn Nematbakhsh2016-04-052-18/+51
| | | | | | | | | | | | | | | | | | | bd99955 enables BC1.2 detection by default and auto-sets current limit based upon the detection results. This is undesirable because it races against our external current limit settings (eg. USB-C / PD detection). BUG=chrome-os-partner:51766 BRANCH=None TEST=Manual on kevin. Plug zinger 10 times, verify that battery charges at ~1500mA on each plug, except for cases where Zinger falls into reset / OC loop (a separate issue). Change-Id: I787b2434c30b89fe78bbe50666075c694bf64503 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336970 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: Specify pinmux wake sources in gpio.incBill Richardson2016-04-056-29/+51
| | | | | | | | | | | | | | | | | | | This adds (and uses) some additional flags for gpio.inc's PINMUX() macro, to configure specific pads as wake sources when the SoC is sleeping. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 The sleep/deep sleep behavior is unchanged. This just replaces hard-coded wake sources with pads configured in gpio.inc and the chip/g/sps.c module. Tests from previous CLs still pass. Change-Id: I6608dc959524f42fd589feb804fa06f29cfd9b9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336838 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Enable normal sleep, tooBill Richardson2016-04-051-34/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the "sleep" low-power mode. It consumes less power than simply waiting, but doesn't require a full warm boot to resume. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Configure the Cr50 to sleep when idle (refer to previous commit messages for the setup required). On the console, use the "idle" command to test the three different modes: idle w - wfi, wakes instantly idle s - sleep, wakes slowly but without rebooting idle d - deep sleep, wakes via warm boot You can tell the difference between wfi and sleep by observing that the first character is lost when typing on the serial console while in sleep (remember that it will wait at least 10 seconds after the last console input before sleeping). Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Ib2584aa44ab885f0c8369ec938ee17b935aa0898 Reviewed-on: https://chromium-review.googlesource.com/336836 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Delay sleeping for longer after console inputBill Richardson2016-04-041-18/+8
| | | | | | | | | | | | | | | | | | | | | | Wait at least 10 seconds after the last console input before invoking sleep or deep sleep. BUG=chrome-os-partner:49955, chrome-os-partner:50721 BRANCH=none TEST=make buildall; test on Cr50 Use the "idle d" console command to put the Cr50 into deep sleep when idle (refer to previous commit messages for the setup required). Wake it up, then let it sleep again. It should go back to sleep quickly when woken via USB, but should take much longer when awakened by typing on the serial console. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7a2b840565f5d82e0dbdf8a3e75061a69cb9e405 Reviewed-on: https://chromium-review.googlesource.com/336835 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Preserve the idle action across soft rebootsBill Richardson2016-04-041-5/+7
| | | | | | | | | | | | | | | | | | | | | | This preserves the selected idle action (wfi, sleep, deep sleep) across soft reboots, which includes deep sleep. Hard reboots will restore the default which is to not sleep at all. BUG=chrome-os-partner:49955, chrome-os-partner:50721 BRANCH=none TEST=make buildall; test on Cr50 Use the "idle d" console command to put the Cr50 into deep sleep when idle (refer to previous commit messages for the setup required). Wake it up, then let it sleep again. It should go back to the deep sleep state. Change-Id: Iaad82b725d2b32a19205fa403dbaab9a31c35630 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336834 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* temp sensor: add support for G782Kevin K Wong2016-04-037-292/+383
| | | | | | | | | | | | | | modify g781.c/.h to g78x.c/.h to suppor both G781/G782 temp sensor based on CONFIG_TEMP_SENSOR_G781 or CONFIG_TEMP_SENSOR_G782 BUG=none BRANCH=none TEST=make buildall; able to get temperature data on board with G782 Change-Id: Ia32c85e9964bfd7c0c5263f04368bc001a27fe10 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334228 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Sleep only when SPS has been quiet for a whileBill Richardson2016-04-033-6/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the SPI slave bus and TPM task to the things that can prevent deep sleep. Even when things are quiet, we wait at least a second With this CL, it will wait at least one second after the last SPS transaction before sleeping. Since most TPM-protocol commands are built up of a number of back-to-back SPS messages, if we don't wait we'll keep trying to sleep in the middle of active commands. Even if everything is quiet, we wait 0.2 seconds anyway to give the UART buffers time to drain. BUG=chrome-os-partner:49955, chrome-os-partner:50721 BRANCH=none TEST=make buildall; extensive tests on Cr50 Testing is a pain. In addition to ALL the steps listed in commit d917d3f1867e96369ff25bf6906043a5f488a6fb, loading the firmware with the spiflash tool leaves SPS_CS_L low, so you have to drive it high manually. The easiest way is to build and run test/tpm_test/tpmtest.py for a few seconds then interrupt it with Ctrl-C. Note that because the system wakes from deep sleep when it sees SPS_CS_L go low but it can't get ready fast enough to capture the incoming bits, that first SPI transaction will be garbled or lost. You'll have to either retry it, or wake the system another way first. Change-Id: Iae2fe5ef33869c48e98a3afecd6b98991a51a488 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336690 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Charger: BD99955: Implement charger interfacesVijay Hiremath2016-04-032-14/+196
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=Manually tested on Amenia prototype. Used 'charger' console command to get the details. Change-Id: I131c8501a4e1cedc2b7073eb43f4735a27c1a55f Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336286 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* charge_manager: Report UNKNOWN USB charger for 2 seconds after changeShawn Nematbakhsh2016-04-0312-22/+45
| | | | | | | | | | | | | | | | | | | After a charger is attached, we may set a charge limit based upon BC1.2 or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds for all negotiation to complete. Previously this behavior was implicit when using SW charge ramp. BUG=chrome-os-partner:51280 BRANCH=glados TEST=Manual on chell. Insert stock charger, verify that it is detected as TYPE_UNKNOWN until timeout. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028 Reviewed-on: https://chromium-review.googlesource.com/334312 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus_pd: Use less flash spaceShawn Nematbakhsh2016-04-033-2/+4
| | | | | | | | | | | | | | | | - Reduce the size of some board-level strings - Undef two rarely-used console commands BUG=chrome-os-partner:34489 BRANCH=None TEST=`make buildall -j` Change-Id: I34d599adccce97a62e28e7444854081f068029c3 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336814 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* console: Put additional console commands behind CONFIGsShawn Nematbakhsh2016-04-033-1/+6
| | | | | | | | | | | | | | | | Allow boards to save flash space by undef'ing CONFIGs which gate 'hcdebug' and 'md' console commands. BUG=chrome-os-partner:34489 BRANCH=None TEST=`make buildall -j` Change-Id: I583b98ff1e4d9d6a26958c6895fb0c0305dddceb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336813 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ectool: Support keyboard factory scanningDevn Lu2016-04-018-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | This is keyboard test mechanism request for "multiple key press test", we can thru the testing to scan out kso ksi pins shortting or keyboard has multiple key pressing, below was the testing steps: 1. Turn off internal keyboard scan function. 2. Set all scan & sense pins to input and internal push up. 3. Set start one pin to output low. 4. check other pins status if any sense low level. 5. repeat step 3~4 for all keyboard KSO/KSI pins. 6. Turn on internal keyboard scan function. BUG=chrome-os-partner:49235 BRANCH=ToT TEST=manual Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed. if no pins short together, it shows passed. Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/332322 Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: initial chipset codeKevin K Wong2016-03-313-0/+462
| | | | | | | | | | | | | | used chipset skylake as the initial code base for apollolake BUG=none BRANCH=none TEST=make buildall Change-Id: If82f9bcd53ff44714f4b277637ff9f3c115ccc4d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331651 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* sensor: update sensor driver to use I2C port from motion_sensor_tKevin K Wong2016-03-3117-197/+251
| | | | | | | | | | | | | this allow motion sensor devices to be locate on different I2C port BUG=none BRANCH=none TEST=make buildall Change-Id: Ia7ba2f5729ebb19561768ec87fdb267e79aafb6a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334269 Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: enable use of multiple UARTsMary Ruthven2016-03-316-62/+244
| | | | | | | | | | | | | | | | cr50 has three UARTs that it will be using. This change modifies the uart api to specify which uart to use. BUG=chrome-os-partner:50702 BRANCH=none TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the different UARTs can be used. Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333402 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: First attempt at USB suspend with deep sleepBill Richardson2016-03-313-57/+151
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is still in testing mode, so you have to take special steps to enable it (keep reading). But if you do the right dance, it does go into deep sleep for USB suspend, and resumes correctly. However, it doesn't yet wake for any other reason. That's coming next. Normal sleep is not yet supported, either. BUG=chrome-os-partner:49955, chrome-os-partner:50721 BRANCH=none TEST=make buildall; extensive tests on Cr50 Testing is a pain. First, you can't print anything in the idle task, because that just makes it stop being idle, so the only way to detect when it's triggered is by wiring up a GPIO and instrumenting things. Second, you have to manually reenable USB suspend on the host every time the Cr50 boots with echo auto > /sys/bus/usb/devices/<BLEH>/power/control where <BLEH> is the correct device. Third, for reasons probably related to the mysteries of HID devices combined with crbug.com/431886, you have to build the firmware without CONFIG_USB_HID (and the related items in board.h) Finally, because it's still a work in progress, you have to type idle d at the serial console after every boot (or resume) to reenable deep sleep in the idle task. If you do all that, then you'll see that it does go into deep sleep. Ping it again with "lsusb -v -d 18d1:5014" or ./test/usb_test/device_configuration, and it wakes up and responds! If you disconnect the USB while it's in deep sleep, it stays asleep. When you plug it in again, it wakes up, but it correctly recognizes that it shouldn't resume and does a normal reset instead. Change-Id: I3cc66e48ce671142a4d12edbe0eb9fdacecea0d9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336279 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* kevin: Add battery and charger supportShawn Nematbakhsh2016-03-317-14/+168
| | | | | | | | | | | | | | | | Add support for bd99955 charger and battery. BUG=chrome-os-partner:51722 TEST=Verify kevin charges at 3A input current when zinger is inserted, and verify battery actually charges. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iccd8185585fe39440681f5830cf58acafe6291b8 Reviewed-on: https://chromium-review.googlesource.com/335538 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* charger: bd99955: Add support for extended featuresShawn Nematbakhsh2016-03-312-13/+157
| | | | | | | | | | | | | | | | | | | | | | Add support for charge port switching and extpower detection, which are not part of the standard charger API. In addition, add a console command for dumping all regs, which is helpful for debug. BUG=chrome-os-partner:51722 TEST=Manual with subsequent commit. Verify kevin charges at 3A input current when zinger is inserted, and verify battery actually charges. BRANCH=None Change-Id: I98a0c0142d26facc0e0b9ef7f1dcd003ebffd9c1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335537 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* CR50: add NULL padding support for RSA encrypt/decryptnagendra modadugu2016-03-314-5/+42
| | | | | | | | | | | | | | | | | NULL padding (aka vanilla RSA) support is required by the TPM2 test suite (referred to as TPM_ALG_NULL in the tpm2 source). BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328830 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Include low-power exit triggers in reset causesBill Richardson2016-03-303-3/+18
| | | | | | | | | | | | | | | | | | | | | | | Some of the reset causes are found in another register when resuming from a low-power state. We know we'll need to distinguish among them eventually, so we might as well decode them now. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 I forced the system into deep sleep and observed that the reset cause is accurately recorded on resume. Doing that requires a fair amount of hacks and manual effort, and can't happen by accident. Future CLs will make use of this. The current, normal behavior is completely unaffected. Change-Id: I5a7b19dee8bff1ff1703fbbcc84cff4e374cf872 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336314 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Handle possible resume from deep sleepBill Richardson2016-03-302-2/+26
| | | | | | | | | | | | | | | | | | | | | | | A resume from deep sleep looks a lot like a cold boot, but there are some registers that need updating quickly. We need to disable the settings that triggered deep sleep so that it isn't accidentally invoked again, and we need to unfreeze any modules or pins that were frozen during the deep sleep. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Since we aren't yet triggering deep sleep, this doesn't do anything noticeable, which is the point. It shouldn't have any effect unless we are entering deep sleep and DON'T do this when it resumes. FWIW, I have tested that too, but it's coming in a later CL. Change-Id: I4b32fd2e24fe089d3f659154df26d275b41b4c1b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336450 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Add stubs to support low-power idleBill Richardson2016-03-303-0/+81
| | | | | | | | | | | | | | | | | | | This just adds the framework to use for implementing sleep and deep-sleep. This provides a custom idle task, and a new "idle" console command to control what that task should do (nothing, yet). BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Other than the new idle command which does nothing, there is no visible change. This is just a stub. Change-Id: I8a9b82ca68dd6d1e3e7275f4f6753a23a7448f1d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336420 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add support for RSA PKCS1-PSS paddingnagendra modadugu2016-03-304-6/+124
| | | | | | | | | | | | | | | Add support for PSS padding as per RFC 3447. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under tpm2 pass Change-Id: I14c58394f742daa5de4ec2fbeb7e7f14e54c9fcc Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/328778 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* Cr50: Support USB SETCFG/GETCFG control transfersBill Richardson2016-03-304-6/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds USB support to Set and Get the Device Configuration. These control transfers are standard device requests that need to be added in order to behave properly for USB suspend/resume (and in general). Before this CL, the Get command always failed and the Set command had no effect internally. With this CL it works. Note that this particular change only supports ONE configuration for the Cr50. If/when we add additional configuration descriptors, we'll need to update it again. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; manual tests on Cr50 This CL includes a test program. Connect the Cr50 to the build host, and use that program to read and change the configuration. cd test/usb_test make ./device_configuration ./device_configuration 0 ./device_configuration 1 ./device_configuration 2 You may need to use sudo if your device permissions aren't sufficient. Change-Id: Id65e70265f0760b1b374005dfcddc88e66a933f6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335878 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* spi_flash: print spi flash size in proper unitNaresh G Solanki2016-03-301-1/+1
| | | | | | | | | | | | | Spi flash size is calculated in the units of kB but is printed as MB. correcting it to kB unit. Change-Id: If71681fc868a5974b44d135055c01f9184c71602 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332732 Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Tested-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* Fan: enable fan after system resumeKeith Tzeng2016-03-301-1/+1
| | | | | | | | | | | | | | | | | | Fan will disable when S3 and S5 by pwm_fan_s3_s5, which call set_enabled(fan, 0) to disable it. But the pwn_fan_resume called fan_set_enabled() which not setting GPIO_FAN_PWR_DIF_L to 1, we should use set_enabled() instead. BUG=chrome-os-partner:50372 BRANCH=master TEST=check fan enable after system resume Signed-off-by: Keith Tzeng <Keith.Tzeng@quantatw.com> Change-Id: Id0bd4dd0afc7e02bcfa6e20401d6e9dfe8a81423 Reviewed-on: https://chromium-review.googlesource.com/335693 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* cr50: update GPIOsMary Ruthven2016-03-291-8/+8
| | | | | | | | | | | | | | Update the GPIO mapping based on the Kevin P0 schematic and drive the EC and AP select signals low. BUG=chrome-os-partner:50728 BRANCH=none TEST=test that DIOB2 and B3 default to low, but can be set high or low. Change-Id: If574436913ad0271540bcce2939fe1f4574dae97 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335381 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: gpio: Configure pin attributes before setting as outputShawn Nematbakhsh2016-03-291-8/+10
| | | | | | | | | | | | | | | | | | | | When a pin power-on default is input, it is necessary to configure output level, pull up, etc. before setting the pin to output. Otherwise, the pin may be set to an undesired logic level for a short time. BUG=chrome-os-partner:51722 TEST=Power-up kevin, verify that CR50_RESET_L (default input, configured as high + open drain output by default) does not go low for a short period at boot. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ieaa08e14e6ea15a908f3ff4ee9188e14b17583cf Reviewed-on: https://chromium-review.googlesource.com/335344 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kevin: Change battery i2c frequency to 100 KHzShawn Nematbakhsh2016-03-291-1/+1
| | | | | | | | | | | | | | | Battery does not support frequency higher than 100 KHz. BUG=chrome-os-partner:51722 TEST=Verify `battery` on kevin shows battery stats. BRANCH=None Change-Id: Ia75e0ffec9344dfc432205acce0ad31ca6d3fb3e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335374 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* power: rk3399: Add power down sequencingShawn Nematbakhsh2016-03-292-10/+35
| | | | | | | | | | | | | | | | Add simple power down control for rk3399. BUG=chrome-os-partner:51722 TEST=Verify power button powers up SOC. Verify next power button press powers down SOC. BRANCH=None Change-Id: Ibf4c9c3cb155b59ca7f2b6feb4f51ff173f407c7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335531 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* flash_ec: Add support for kevinShawn Nematbakhsh2016-03-281-2/+14
| | | | | | | | | | | | | | | | Add support for kevin, which uses external 1.8V SPI. BUG=chrome-os-partner:51722 TEST=Verify kevin EC is flashable. Verify wheatley still uses pp3300 SPI voltage. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13e45e829cdc7b2298715812f5714d5dd806df06 Reviewed-on: https://chromium-review.googlesource.com/335396 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: pwm: Fix PWM moduleShawn Nematbakhsh2016-03-282-5/+8
| | | | | | | | | | | | | | | | | - Fix incorrect use of pwm functions which take a channel number. - Set power-down register according to PWMs that are actually enabled. BUG=chrome-os-partner:51722 TEST=Run 'pwm 1 50` on kevin and verify that LED lights up. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If7bcc812b55d3b72f215cf41c264d34827db7e29 Reviewed-on: https://chromium-review.googlesource.com/335372 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* spi_flash: Reload watchdog before writing a flash pageShamile Khan2016-03-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When EC receives many flash write requests from host and PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the HOOK task may not get scheduled in time to pet the watchdog resulting in an EC reset. BUG=chrome-os-partner:51438 BRANCH=None TEST=Manual on lars, determine two EC versions that have enough differences so that replacing one image with the other will require all or most of the flash pages to be updated. Alternate between flashing the two images with flashrom using a script. Atleast 1000 iterations should pass. Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334457 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52) Reviewed-on: https://chromium-review.googlesource.com/334903 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: Fix subtle USB error in clearing global NAKsBill Richardson2016-03-251-2/+2
| | | | | | | | | | | | | | | | | | | | | We clear global NAKs by writing bits in the USB_DCTL register. However, prior to this CL we were overwriting the entire register, not just touching individual bits. Since we've never actually set any global NAKs, this mistake didn't have any noticeable effects. But we should still do the right thing in case we need it later. BUG=chrome-os-partner:50721 BRANCH=none TEST=make buildall; test on Cr50 No visible change; everything continues to work. Change-Id: Ia25d95dc6211e5460132622ac005723f43b00e24 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335190 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Fix console message on unexpected USB eventBill Richardson2016-03-251-6/+6
| | | | | | | | | | | | | | | | We were referring to unhandled USB control messages as errors, but they aren't necessarily. Sometimes they're optional things that aren't fatal. We should still address them, but we don't have to freak out. BUG=none BRANCH=none TEST=make buildall; test on Cr50 Change-Id: I892acec2d89b8ec95353cdc09f3e49aa78b1704d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/335200 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Cleanup check_reset_cause() codeBill Richardson2016-03-251-10/+18
| | | | | | | | | | | | | | There were some unnecessary shifts and conditionals. This just makes the code a little more readable. BUG=none BRANCH=none TEST=make buildall; test on Cr50 hw Change-Id: I084f191675d1b51101e9dc55c2e5a12b0b345d33 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334870 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: cleanup: Clarify a few commentsBill Richardson2016-03-242-7/+18
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall; try on Cr50 No code changes, just comments. Change-Id: I3eccccb024b4a319920a8252cd7d5d3829bf21da Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334820 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Cr50: Remove CONFIG_HOSTCMD_SPS supportBill Richardson2016-03-243-311/+1
| | | | | | | | | | | | | | | | This config option allowed us to disable the TPM protocol on the SPI slave bus and replace it with our EC-style host command protocol. We only used this for early testing and don't need it anymore, so we can get rid of it completely for this SoC. BUG=none BRANCH=none TEST=make buildall; test on cr50 Change-Id: I2126537e8bcc78e583cf426a3a83962c9ff1a121 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334762 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* it8380dev: util: Enable Host Global ResetDonald Huang2016-03-241-1/+1
| | | | | | | | | | | | | | BRANCH=none BUG=none TEST=Test OK on ITE8390CX. You can run "make -j BOARD=it8380dev" to build ec.bin and flash the ec.bin via "sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin" Change-Id: I2077012114bdbd5a8cc8f7dc29e43cdcb77d65b6 Signed-off-by: Donald Huang <donald.huang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/334176 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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