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* cleanup: remove board function callback on charge override timeoutrelease-R45-7262.BAlec Berg2015-07-1310-54/+17
| | | | | | | | | | | | | | | | | Remove board function callback on charge override timeout, since the implementation should be common to all boards: send host event. This function is called when a power swap fails during an issued charge override and notifies the host so that it is aware that the power swap did not succeed. BUG=none BRANCH=smaug TEST=make -j buildall Change-Id: Ia2a078a17aef6b302fd2b9fd21a5a92c628fd7db Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: define one set of USB charger voltage and min currentAlec Berg2015-07-1310-53/+39
| | | | | | | | | | | | | | | Remove duplicate definitions of USB charger min current across boards and make one set of defines for standard USB charger voltage and minimum USB charger current. BUG=none BRANCH=smaug TEST=make -j buildall Change-Id: Ib842fafb317417c8de9a67d314fdde4c1e47ad9d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284956 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: for one PD port, allow task to be named PD or PD_C0Alec Berg2015-07-111-0/+2
| | | | | | | | | | | BUG=none BRANCH=none TEST=make -j buildall Change-Id: If8442a0a2d0a26c4e2cd4e23cbb93f689258bf21 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284913 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: Clear the TX FIFO when the SPS CS deassertsBill Richardson2015-07-112-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SPI slave chip select is deasserted, it means that the SPI master doesn't want to hear any more from the EC. We need to clear any bytes left in the TX FIFO, so that the next SPI transaction doesn't send those leftover bytes out. Since the EC's SPI protocol for host commands uses software flow control, those leftover bytes could screw up the messages. I expanded a comment explaining how that works. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall And, with the EC connected to the build host via an FTDI USB-to-SPI adapater, I used the extra/sps_errs/ test program to see the original problem and that this CL fixed it: cd extra/sps_errs make ./prog -v ./prog -v -c 22 ./prog -v This sends a complete EC_CMD_HELLO message, then a truncated message, then sends the whole message. Before this change to sps.c, the third message response begins with the leftover bytes from the aborted second message. Bad third message: Transfer(12) => 03 64 01 00 00 00 04 00 a5 a5 a5 a5 Transfer(12) <= a9 a8 a7 a6 f8 f8 f8 f8 f8 f8 f9 f9 ^^ ^^ ^^ ^^ Good third message: Transfer(12) => 03 64 01 00 00 00 04 00 a5 a5 a5 a5 Transfer(12) <= f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f9 f9 ^^ ^^ ^^ ^^ Change-Id: Id6e431f91be0204921edee2f774b6c487966ddff Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284746 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* Cr50: Add extra/sps_errs/ test programBill Richardson2015-07-114-0/+513
| | | | | | | | | | | | | | | | | | | | | | | | | This adds another test program to use with the EC connected to the build host via an FTDI USB-to-SPI adapater, This program sends an EC_CMD_HELLO host command to the EC. Options exist to display the bytes transferred over the SPI interface, and to truncate the message before its complete, to see how the EC reacts. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall To try out the new test program: cd extra/sps_errs make ./prog ./prog -v ./prog -v -c 22 Change-Id: I1d370ecdbae047d9504bc6e5f73949d4e3aed9d9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284865 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* Update .gitignore for new private repoBill Richardson2015-07-101-0/+1
| | | | | | | | | | | | | | | | | A new private repo has been added, so prevent git from complaining about it. BUG=chromium:507445 BRANCH=none TEST=make build all; git status Nothing breaks, "git status" stops pointing out the new subdirectory. Change-Id: Ibf1fbc7504fb6bbb9df7d6ddf0efda9a632e39b6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284874 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* glados: scrub gpio config to save powerAlec Berg2015-07-101-13/+12
| | | | | | | | | | | | BUG=chrome-os-partner:42104 BRANCH=none TEST=load on glados, boot, test keyboard and lid switch. Change-Id: I1c308e4372f5eb23549ca2c7101373ef16cb1a62 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283558 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* ectool: Fix compilation warningGwendal Grignou2015-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | Was comparting a int16_t with 0x8000 leading to: error: comparison of constant 32768 with expression of ec-utils-0.0.1-r2377: type 'int16_t' (aka 'short') is always false (Builder: Chromium OS (x86) Asan (stats) 7005) BRANCH=smaug TEST=On Smaug check that ectool does report invalid temperature when EC returns 0x8000. Check the temperature is correct when the EC returns a valid temperature. BUG=chromium:508674 Change-Id: I2a1414cf7bf018ecaa7ff8dd37c76804de4bce52 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284673 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Achuith Bhandarkar <achuith@chromium.org>
* Cr50: Handle 11-bit SPS FIFO pointers correctlyBill Richardson2015-07-101-30/+52
| | | | | | | | | | | | | | | | | The SPS module uses mirroring for the buffer management (see https://en.wikipedia.org/wiki/Circular_buffer#Mirroring). This just tweaks the logic to handle that correctly. BUG=b:20894690 BRANCH=none TEST=make buildall Also tested with extra/ftdi_hostcmd Change-Id: Icb9593b71fd3c745bd333c7ee1a9492fab022e1f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283902 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* ryu: sensor hub: Add FIFO and interrupt supportGwendal Grignou2015-07-104-2/+16
| | | | | | | | | | | | | Enable code to use BMI150 FIFO and interrupt support on Smaug BUG=chrome-os-partner:39900 BRANCH=smaug TEST=Check fifo is working, interrupts are enabled. Change-Id: Ifc07da793d3ece4806895db4aff5d880c0f3d9b0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274228 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: bmi160: Add FIFO and interrupt supportGwendal Grignou2015-07-109-120/+731
| | | | | | | | | | | | | | | | | | | Add FIFO support, where bmi160 hardware FIFO is copied in local fifo. Add rudimentary support for single/double tap and lift detection. BUG=chrome-os-partner:39900 BRANCH=smaug TEST=Check on F411 that FIFO data is retrieved and correct. Check on Smaug as well, with proper kernel the collect the FIFO: - check that increasing sampling_frequency we are collecting the FIFO less often - check no frames are lost. - check tap/lift interrupts are working - if latency is less than 100ms, check we are collecting much faster. Change-Id: Ic2317c27fad0ef31dacd6e18cd5f71ccd2cec807 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274227
* Reserve host command range for experimentsBill Richardson2015-07-101-0/+17
| | | | | | | | | | | | | | | | | This adds a range of (proto v3) host commands to use for experimental/one-off feature development without constantly updating include/ec_commands.h BUG=none BRANCH=none TEST=make buildall This doesn't implement any new commands. It just adds some new constants. Change-Id: I1d7b829dec9fa847e16f92d35c78446cc5f34cc5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284408 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* driver: bm160: fix ODR_TO_REG macrosGwendal Grignou2015-07-101-3/+7
| | | | | | | | | | | | | Were not working when ODR > 100Hz. BRANCH=smaug TEST=Check by setting iio:deviceX/frequency from user space. BUG=chrome-os-partner:39900 Change-Id: I1795e4faf85039133da6bb38ae3b415e5fde236e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284612 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Add verbose & range options to extra/ftdi_hostcmd/Bill Richardson2015-07-101-13/+61
| | | | | | | | | | | | | This just helps debug the SPI traffic. BUG=none BRANCH=none TEST=make buildall Change-Id: I09c2f0e0fed9a9f7d0b4cbcea6719c73cdf61068 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284409 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Enable host commands over SPI busBill Richardson2015-07-096-1/+624
| | | | | | | | | | | | | | | | | | | | | | This enables the feature that lets the Cr50 receive host commands via the SPI (slave) interface. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall CQ-DEPEND=CL:283998 This CL also adds a test example in the extra/ftdi_hostcmd/ directory. To use it, you need the Cr50 attached to the build host via an FTDI USB-to-SPI adapter. cd extra/ftdi_hostcmd make ./test_cmds Change-Id: Ia719b1c898afc45b3105a9cd573a8492178d9be2 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284001
* samus: small change to support sensor offsets in ECGwendal Grignou2015-07-091-1/+1
| | | | | | | | | | | | BRANCH=smaug BUG=chromium:506101 TEST=On samus, check we can set the offset and are taken into account. Check the bias added is correct in the measurements. Change-Id: I6cf06271ac080a47a008a342d9d108fd302241cc Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283164 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: lsm6ds0: Add bias offset codeGwendal Grignou2015-07-092-32/+47
| | | | | | | | | | | | | | | | Add code to store bias from AP at boot and correct raw data from accelerometer on the fly. Also return the raw data on 16 bits, as recommned by sysfs. BRANCH=smaug BUG=chromium:506101 TEST=check set and get offset works fine. Check value from accelerometer are sane (on Samus). Change-Id: Ia62f02aadb9e11988edf0049a0cfee817641db88 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283163 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: kxcj9: Add bias offset codeGwendal Grignou2015-07-092-31/+46
| | | | | | | | | | | | | | | Add code to store bias from AP at boot and correct raw data from accelerometer on the fly. Also return the raw data on 16 bits, as recommned by sysfs. BRANCH=smaug BUG=chromium:506101 TEST=check set and get offset works fine. Check value from accelerometer are sane (on Samus). Change-Id: I2ad4ce601665b497527dc8c6acb6e7d398366afe Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283162
* motion: Add commands for calibrationGwendal Grignou2015-07-094-4/+133
| | | | | | | | | | | | | | | Move calibration in the EC to returns raw value with offset already applied, as recommended by iio interface. BRANCH=smaug TEST=On Samus, with kernel change CL:283103 Check raw value are returned properly. BUG=chromium:506101 Change-Id: I3dcb4f2fcfff35639e3bfdcc6c1468bdb5e53c45 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283161 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* flash_ec: remove redundant code from lm4x_cmds.tclMyles Watson2015-07-091-32/+16
| | | | | | | | | | | | | | All boards in ToT have the same RO configuration. Boards which define CONFIG_FLASH_PSTATE_BANK have pstate following RO. BRANCH=none BUG=chrome-os-partner:22990 TEST="git grep" to see that none of the affected functions are called. Change-Id: Ie1eb9a726e1fa157852b0c55d474c9b4587c41f0 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273908 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: split interface config from chip configsMyles Watson2015-07-094-25/+23
| | | | | | | | | | | | | | | | | rename setup_openocd -> flash_openocd refactor so that flash_npcx and flash_lm4 set OCD_CMDS and call flash_openocd BRANCH=none BUG=chrome-os-partner:22990 TEST=run flash_ec before and after and compare the sequence of calls to dut-control and the command-line args to openocd tested with ryu (non-lm4), samus, link, npcx_evb, and peppy Change-Id: I7a05e3219d4b324bcf19a20f86b149f8e3377465 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273907 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: move openocd configs from chip/ to util/Myles Watson2015-07-097-26/+0
| | | | | | | | | | | | | | Avoid duplicating servo configurations for every chip. BRANCH=none BUG=chrome-os-partner:22990 TEST=None. This is an intermediate step to make it clear what's happening. CQ-DEPEND=CL:273950 Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273906 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Implement host commands over SPI busBill Richardson2015-07-083-0/+302
| | | | | | | | | | | | | | | | | This adds a module that attaches to the SPS driver to process host commands delivered over the SPI slave interface. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall This feature is not yet enabled, so there's nothing new to test. That will come next. Change-Id: If57a6fce698a7eb050e2a68b7f4d18d8b0e2956f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284010 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Add Try.SRC functionality to the pd_protocol state machineScott2015-07-084-17/+122
| | | | | | | | | | | | | | | | | 1. Added new config option CONFIG_USB_PD_TRY_SRC 2. Added pd_try_source_enable global flag with console command 3. Added bit to pd.flags to indicate Try.SRC states are active BUG=chrome-os-partner:39724 TEST=Manual samus to samus with the Try.SRC enabled on both and just one samus. Tested Samus to Honeybuns and Samus to Zinger connections. BRANCH=TOT Change-Id: Ifa5d5d82e443f376e546aaf852ff24d92ef04d72 Signed-off-by: Scott Collyer <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282052 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* Fix stack overflow exception in host-command task.Chiranjeevi Rapolu2015-07-082-1/+2
| | | | | | | | | | | | | | | | Increase host-command task stack size by 128 to avoid stack overflow exception. BRANCH=None BUG=chrome-os-partner:42071 TEST=Test for general functionality and confirm that no stack overflow happens. Change-Id: I5513dbca84cf556357c25cddbcde00e0db6d271b Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282810 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* it8380dev: add flash module and fix system jumpDino Li2015-07-0812-25/+875
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add flash control module for emulation board. 2. Fix system jump for Andes core. 3. Change the physical size of the flash on the chip to 256KB. note: 1. Only IT839x series supports flash write protect by registers. 2. Static DMA method of flash code only for IT839x series and IT838x Dx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command flashwp and flashinfo 1-a. flashwp enable 1-b. WP asserted and reboot 1-c. flashinfo RO protected now 1-d. WP deasserted and reboot 1-e. No protected 1-f. flashwp disable 1-g. WP asserted and reboot 1-h. No protected 2. console sysjump and sysinfo 2-a. sysjump rw 2-b. jumping to image RW 2-c. sysinfo, Copy : RW, Jumped : yes 2-d. sysjump ro 2-e. jumping to image RO 2-f. sysinfo, Copy : RO, Jumped : yes 3. RO/RW firmware image test 3-a. sysjump rw 3-b. use console command "eflash" to erase RO region, erase OK and system still work. 3-c. reflash firmware 3-d. sysjump rw, sysjump ro 3-e. use console command "eflash" to erase RW region, erase OK and system still work. Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8 Reviewed-on: https://chromium-review.googlesource.com/271390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* Add jerry to the list of BOARDS_STM32 as a short-term fixDan Shi2015-07-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Board jerry was removed from the list in CL 276524. The board share the same overlay as pinky. So ideally user can call flash_ec with board set to pinky. This applies to other veyron boards in BUG 505003 as well. However, servo in the lab runs on ToT, and it only updates firmware of the dut by calling flash_ec with board name retrieved from the overlay file. Also, lab has a tool to check the servod's board and the dut's board. That is, if we change servod to return board name pinky for servo connected to a jerry dut, the lab script will raise a warning that the servod is running with a wrong board. Before we have a good design to really address the issue, I'd like to add jerry back to flash_ec so the board can run FAFT in the lab. BUG=chromium:505003 BRANCH=None TEST=None Change-Id: I155e79710f2731701af0acdfeab6089701cf52a8 Reviewed-on: https://chromium-review.googlesource.com/283494 Tested-by: Dan Shi <dshi@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dan Shi <dshi@chromium.org>
* Cr50: Simplify the API for the SPS driverBill Richardson2015-07-076-370/+159
| | | | | | | | | | | | | | | | | | | | | | The SPS (SPI Slave) driver handles incoming traffic from the SPI master. This abstracts the basic hardware functions into a clean API so that the response to the SPI bytes can be put into separate files. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall If CONFIG_SPI is not defined, incoming SPI traffic is completely ignored. Even when it's enabled, nothing is reacting to the traffic so incoming SPI bytes return 0xFF bytes to the master (SPI traffic is always bidirectional). Change-Id: I9bbcebc9c5223b942362200fe43a11ac57dfff40 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283581 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* Add EC_CMD_BLOB host command to pass opaque data aroundBill Richardson2015-07-061-0/+8
| | | | | | | | | | | | | | | | | | | | This provides a way to experiment with or support random functionality not specifically related to the normal EC operation. With this, we can use a standard host command to pass opaque data blobs between the AP and EC without specifying a particular meaning to them. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall Nothing in the normal EC usage sends these messages. I have a test/example program coming soon. Change-Id: I77fe434cbd9151e4c2c22bc36d1ed6063d3bf940 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283070 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lucid: add support for lucid battery pack boardAlec Berg2015-07-069-0/+804
| | | | | | | | | | | | | Add support for lucid battery pack board. BUG=chrome-os-partner:42111 BRANCH=none TEST=make -j buildall Change-Id: I145a1a362503bcd35ee92e6c013af4facd95f443 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283170 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: cleanup a few strings & messagesBill Richardson2015-07-014-3/+6
| | | | | | | | | | | | | | Add a description for the USB HID interface, neaten a bit of console output. No new functionality. BUG=none BRANCH=none TEST=make buildall Change-Id: Ie85a0192bc4ab9fa87afb4be41d496545a3b548a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283051 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: protect spi_transcation() with mutexAndrey Petrov2015-07-012-2/+17
| | | | | | | | | | | | | | | | | | Concurrent SPI transactions are not possible, however in case of external SPI and flashrom update scenario both host command and vhash trigger transactions. This adds mutex for the SPI transcation BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read, erase or write errors Change-Id: If346ebe635387d477dcea5f406a5c31579142e2d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282113 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: correct reset cause state in lfwDivya Jyothi2015-07-011-5/+12
| | | | | | | | | | | | | | | | | | Reset cause was recorded / corrected only in RO/RW images. lfw still has old implementation.This caused sysjump RO/RW to not jump appropriately. BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan,sysjump RO and sysjump RW console commands nd make sure it jumps to the right image. Change-Id: I37138f552fdd385c98d770d242d896ffc014697c Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282210 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* nds32: remove macro "RO"Dino Li2015-07-014-25/+4
| | | | | | | | | | | | | | | | | | | "RO" is a workaround for GP base instructions. And now we have added "-mno-gp-direct" option in the NDS32 toolchain. So the compiler would not generate GP base instructions directly, and we can remove this "RO". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:24378 TEST=console "version" and "gpioget" Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/281862 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: Change which DP pin config DP source uses for sink capabilities.Todd Broch2015-07-012-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DP Alternate mode specification defines two bytes in the DP capabilities payload with respect to pin configs. One that governs the DFP and the other the UFP. The one that the DP source needs to examine depends upon whether the UFP is a receptacle or a plug. Previously we just examined the DFP pin config which was correct for all UFP plugs but not UFP receptacles. This change fixes that by examining bit <6> of capability message to determe plug vs receptacle and in case of receptacle choosing the UFP ping config instead. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chromium:505652 TEST=manual, hoho & apple (UFP_D plugs) still work. While I don't have a test for UFP_D receptacle partner device reports following for its DP caps which should now decode correctly. <31:24> 00 Reserved/SBZ <23:16> 1C UFP pin config == C, D, E <15:08> 00 DFP pin config zero <07:00> C5 <6> == 1 == receptacle Change-Id: Ib9e3a808828ff6b8c062baf0fc3c23b3da33c2c3 Reviewed-on: https://chromium-review.googlesource.com/282621 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org>
* mec1322: reload watchdog on LFW entryAndrey Petrov2015-07-011-0/+9
| | | | | | | | | | | | | | | | | | When RO/RW sysjump is made watchdog is not disabled. Since LFW needs to load firmware image into SRAM over SPI, there is a certain chance watchdog counter will fire in the middle of it. BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles and make sure there is no watchdog reset Change-Id: Idafcc6a1c9fb35f04be398a68e3ec05bb2b1425d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282112 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* vboot_hash: Abort hash calculation on flash writeDivya Jyothi2015-07-013-3/+36
| | | | | | | | | | | | | | | | | If flash is being written, any pending hash calculation is likely to be invalid. BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read, erase or write errors Change-Id: I915f8db7998c56fc12e7d85173232882fb7ed80d Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282211 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: fix flash_physical_read()Andrey Petrov2015-07-013-18/+6
| | | | | | | | | | | | | | | | | | | | | | | flashrom on target issues a salvo of flash read commands with small buffer size (128 bytes). Since there is no yield this starves other tasks/events including hooks and as result watchdog is never reloaded. This change makes read function yield to other tasks. In addition, spi_enable()/disable chaining leads to situations where a SPI can be disabled in the middle of transcation. This is addressed by keeping SPI permanently enabled in LFW entry function, as well as in RW/RO early init functions. BRANCH=None BUG=chrome-os-partner:38103 TEST=manual on Cyan, run flashrom -p ec -w xx in cycles, swaping xx so that flashrom does flash. Make sure there is no watchdog triggered Change-Id: Id5c50239a1d5c64054d7c660dd03b2be4678221c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282111 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* pi3usb9281: fix BC1.2 re-detection when using USB device modeVincent Palatin2015-07-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | When the USB2.0 port is used in device mode, having the D+/D- lines connected just before resetting the PI3USB9281 (for the 2nd detection used a BC1.2 debouncing) triggers a misdetection where DCP chargers are seen as Apple 2.4A chargers. To avoid this, disconnect the D+/D- lines and let them relax before triggering the PI3USB9281 reset. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:42048 TEST=connect and disconnect a DCP charger to the Smaug type-C port with the AP running, see it constantly detected as DCP and no Pericom interrupt storm. Change-Id: I8f6043439c2c6b52f2689b4947baffe51f62eba8 Reviewed-on: https://chromium-review.googlesource.com/282594 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* bq2598x: ryu: take into account hardware input current optimizerVincent Palatin2015-07-016-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | Take profit of the hardware input current ramping/back-off integrated in the BQ2589x charger by setting the current limits higher for BC1.2 USB modes and letting the hardware adjust to the actual charger limitation depending on the VBUS voltage droop. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:42045 TEST=Connect a Nexus 9 DCP charger to Smaug and see the input current adjusted to 1650mA without brown-out, read back the value properly from the AP: $ ectool usbpdpower Port 0: SNK Charger DCP 4958mV / 1650mA, max 5000mV / 1650mA / 8250mW Change-Id: I348e5ee4980a5652f72f279ab4e3a7126583b093 Reviewed-on: https://chromium-review.googlesource.com/282584 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* tcpc: use initialization complete alert bit to signal readinessAlec Berg2015-06-302-10/+19
| | | | | | | | | | | | | | | Use the new TCPC initialization complete bit in alert register to signal TCPC readiness instead of checking for USB VID to be set. BUG=none BRANCH=none TEST=load on glados, make sure we can boot without battery. Change-Id: I4b25c973ece0de6dd3f419c5901cff1d8d05ed95 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282593 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32 PWM: Add error case in conditional compilationAnton Staaf2015-06-301-1/+3
| | | | | | | | | | | | | | | | | | | Ensure that a new chip doesn't default to one of the possible alternate function selection schemes, requiring it to pick one or implement something new. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I3650fa0c99bbf541039a778f4d6398f0a549f1b2 Reviewed-on: https://chromium-review.googlesource.com/282601 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* STM32F: Remove support for this familyAnton Staaf2015-06-3021-2035/+478
| | | | | | | | | | | | | | | | | | There are no boards left that use this family of STM32 parts. If we add one later we can resurect support. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: If985a9e9f93c935e98c93f33c075ce00cb9a91ac Reviewed-on: https://chromium-review.googlesource.com/282532 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* it8380dev: add pin 3.3v/1.8v selectionDino Li2015-06-304-2/+101
| | | | | | | | | | | | | | | | | | | add GPIO_SEL_1P8V flag for 1.8v/3.3v selection. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To configure 1.8V/3.3V pin to 1.8V, set GPIO_SEL_1P8V flag in gpio.inc. 2. The corresponding bit will be set as default value if the pin is not listed in gpio.inc. Change-Id: Ica02aabe40b83fcb4d33bd28d717a0633bdef5f3 Reviewed-on: https://chromium-review.googlesource.com/281842 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* glados: Add support for USB-C muxesShawn Nematbakhsh2015-06-303-3/+23
| | | | | | | | | | | | | | Add support for pericom mux (port 0) and parade mux (port 1). BUG=chrome-os-partner:41696 TEST=Verify set() and get() functions set and return consistent values. Verify that DP and USB are only activated when proper modes are set. BRANCH=None Change-Id: I9d42108688a9070b982ae77f77633654bc6505ed Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282281 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* presubmit: Add hook to check for config options.Aseda Aboagye2015-06-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | This enables a presubmit hook to check for missing configuration options. All CONFIG_* options should be defined in include/config.h along with a brief description of what the config option does. BUG=chrome-os-partner:26304 BRANCH=none CQ-DEPEND=CL:281626 TEST=Create a commit modifying a source file with a new CONFIG_* option and watched the preupload process fail illustrating the error with the CONFIG_* option. TEST=make -j buildall tests Change-Id: I7240b386b4981dcab66811a4829d7d6ebfbf7cb1 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/281826 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* usb_mux: Add support for Parade PS8740 chipShawn Nematbakhsh2015-06-305-0/+154
| | | | | | | | | | | | | | | Initial support for Parade PS8740 Type-C redriving switch. BUG=chrome-os-partner:41696 TEST=Manual on Glados in subsequent commit. Verify set() and get() functions set and return consistent values. Verify that USB SS device functions when muxes are set to dock or USB. BRANCH=None Change-Id: Iedbe53cc76f30ecd969c2ca99a7377ed3b193729 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282280 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* usb_mux: Add driver interface for USB-C muxesShawn Nematbakhsh2015-06-3032-644/+853
| | | | | | | | | | | | | | | | | | | | In preparation for adding support for additional USB-C mux chips, add a new high-level USB-C mux interface usb_mux.c. usb_mux functions are now called from pd code instead of board-level functions. usb_mux calls down into a mux chip-specific driver (currently pi3usb30532) or board-specific drivers which toggle GPIOs (for legacy boards). BUG=chrome-os-partner:41696 TEST=Manual on Glados in subsequent commit. Verify set() and get() functions set and return consistent values. Verify that USB SS device functions when muxes are set to dock or USB. Also, verify that DP dongle and USB SS device are functional on both PD ports on samus_pd. BRANCH=None Change-Id: Ib6477f489310f3be1430585ea09fea26f57e3752 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/281435 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* tcpc: update tcpci registers to latest specAlec Berg2015-06-306-74/+70
| | | | | | | | | | | | | | | Update TCPCI registers to version 0.62 of PD Interface specification. BUG=none BRANCH=none TEST=test on glados and samus Change-Id: I57338b385123371e90f3b79b84e652af15be1bf1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282067 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: refactor tcpm and move alert function to tcpm driverAlec Berg2015-06-308-192/+265
| | | | | | | | | | | | | | | Refactor the tcpm/tcpc split such that the tcpm driver implements the alert functionality since it may be unique for different tcpc chips. BUG=chrome-os-partner:41842 BRANCH=none TEST=make -j buildall. run on samus and glados. Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/281631 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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