summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Clear OWNERS for factory/firmware branchfirmware-servo-11011.BBrian Norris2021-09-102-10/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155241 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-171-1/+3
| | | | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit c2c2c083fef813e3e3c70f8c13a1418717ba682d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107664
* servo_v4: fix in displaying CCD polarityNamyoon Woo2019-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From crrev.com/c/1529724, servo-v4 console displays the ccd polarity in opposite manner. 2019-05-15 11:53:59 [583.849805 CCD: connected noflip] 2019-05-15 11:54:01 adC 2019-05-15 11:54:01 CHG_CC1_PD = 1708 2019-05-15 11:54:01 CHG_CC2_PD = 33 2019-05-15 11:54:01 DUT_CC1_PD = 1637 2019-05-15 11:54:01 DUT_CC2_PD = 1625 2019-05-15 11:54:01 SBU1_DET = 3092 2019-05-15 11:54:01 SBU2_DET = 24 2019-05-15 11:54:01 SUB_C_REF = 569 2019-05-15 11:54:20 C1 st3 2019-05-15 11:54:20 C1 st5 2019-05-15 11:54:20 [604.585404 CCD: connected flip] 2019-05-15 11:54:23 adc 2019-05-15 11:54:24 CHG_CC1_PD = 1712 2019-05-15 11:54:24 CHG_CC2_PD = 32 2019-05-15 11:54:24 DUT_CC1_PD = 1616 2019-05-15 11:54:24 DUT_CC2_PD = 1644 2019-05-15 11:54:24 SBU1_DET = 20 2019-05-15 11:54:24 SBU2_DET = 2955 2019-05-15 11:54:24 SUB_C_REF = 611 BUG=None BRANCH=None TEST=manually build fw and checked. 2019-05-15 12:07:46 [27.057955 CCD: connected noflip] 2019-05-15 12:07:47 adc 2019-05-15 12:07:48 CHG_CC1_PD = 1705 2019-05-15 12:07:48 CHG_CC2_PD = 4 2019-05-15 12:07:48 DUT_CC1_PD = 1617 2019-05-15 12:07:48 DUT_CC2_PD = 1645 2019-05-15 12:07:48 SBU1_DET = 20 2019-05-15 12:07:48 SBU2_DET = 3102 2019-05-15 12:07:48 SUB_C_REF = 592 2019-05-15 12:08:05 [45.191161 CCD: connected flip] 2019-05-15 12:08:06 adc 2019-05-15 12:08:08 CHG_CC1_PD = 1704 2019-05-15 12:08:08 CHG_CC2_PD = 4 2019-05-15 12:08:08 DUT_CC1_PD = 1638 2019-05-15 12:08:08 DUT_CC2_PD = 1625 2019-05-15 12:08:08 SBU1_DET = 2970 2019-05-15 12:08:08 SBU2_DET = 23 2019-05-15 12:08:08 SUB_C_REF = 563 Change-Id: I0e8540fb30460827772fefd63a3426d67fa85092 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1613650 Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit 83ea11a4fa470c1de5130d8fd5bfbacf9805278e) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1939776 Commit-Queue: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org>
* servo_micro: shutdown HW module at sysjumpJett Rink2019-11-192-2/+28
| | | | | | | | | | | | | | | | | | | | Some servo micros will fail to jump to RW if we leave the USART hardware modules active during the RW jump and the RW jump tries to change the gpio flags to anything other than alternate in gpio.inc. We would like the state transition from RO to RW to be as clean as possible, so shutdown the hardware modules that RW will reinitialize in board_init right after the jump BRANCH=servo BUG=b:144356961 TEST=flash this image on a bad servo micro, the remove then change GPIO_ALTERNATE to GPIO_INPUT and reflash and see that it sauce's fully flashes from then on Change-Id: I81fcbbcda9f63761a719f6e0cb6bb4cf6962f18f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924498
* servo_micro: add usart cmd to hold pins lowJett Rink2019-11-113-4/+105
| | | | | | | | | | | | | | | | | | | | | | | | To enabled UART (UUT) programming mode for some ECs, we need to drive the EC_TX_SERVO_RX line low while the EC is rebooting. Add a console command that is controllable by dut-control that will drive the UART pins low while the UART is disabled, until the command to re-enable the UART is sent on the console. Also, remove unnecessary alternate mode initialization for USART4 (UART3). BRANCH=firmware-servo-11011.B BUG=b:143163043 TEST=flashed phaser with reworked servo_micro Change-Id: I1af1af7b48bf446936211740e16008a80ab2a39f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884190 Reviewed-by: Keith Short <keithshort@chromium.org> (cherry picked from commit b3cb8a6f818f425bfe11b817d7b873dd36d239a8) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906246 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* servo_v4: The polarity is based on the flags in SRC DTS modeWai-Hong Tam2019-11-063-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port in SRC DTS mode, it should not perform the polarity detection. The polarity is predetermined, as a board-specific setting. In the servo case, the polarity is based on the flags. This CL changes the protocol layer to check the port in SRC DTS mode and call the board-specific function board_get_src_dts_polarity() for the polarity. BRANCH=servo BUG=b:140876537 TEST=Configed servo as srcdts and unflipped direction: > cc srcdts cc2 Verified the power negotiation good and detected the correct polarity: > pd 1 state Port C1 CC2, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e Without this patch, it detected the wrong polarity and the power negotiation failed: > pd 1 state Port C1 CC1, Ena - Role: SRC-DFP State: SRC_DISCOVERY, Flags: 0x10608 Change-Id: I32c5dfffeaeb20a21db1417f3a1c98566b7f5e38 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891255 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org> (cherry picked from commit 3c1eff2e293adeca40c0c919e63db4c62b89de41) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902098
* common: Define markers for weak symbolsDaisuke Nojiri2019-11-061-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces macros to mark weak symbols. These macros are used to annotate weak definitions, declarations, and overriding definitions. __override_proto: declarations __override: definitions which take precedence __overridable: default (weak) definitions Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium.org/964060 BRANCH=none TEST=buildall Change-Id: I44cec41e0523e285db19a890d084b52337f64a9c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1633911 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> (cherry picked from commit a5c17b44c506979a56cf7ebcaf03ef86f406a3c4) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902097 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com>
* servo_v4: Use the correct voltage threshold on the flipped CC directionWai-Hong Tam2019-11-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the DTS mode, servo pulls up CC lines with different Rp values. When detecting DUT Rd value, servo senses the CC voltage values, and checks it using some table of voltage thresholds. The tables assume CC1 is the primary CC and CC2 is the alternative CC. When servo emulates the flipped CC scenario, should use the correct colume to check the voltage thresholds. BRANCH=servo BUG=b:136014621, b:140876537 TEST=Configed servo to emulate the flipped scenario in dts mode: > cc srcdts cc2 Verified it detect the correct Rd values in DUT (CC0 and CC1 are 2, i.e. TYPEC_CC_VOLT_RD): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:2 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Without this patch, it detected wrong Rd values in DUT (CC0 is 2, i.e. TYPEC_CC_VOLT_RD, but CC1 is 0, i.e. TYPEC_CC_VOLT_OPEN): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:0 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Change-Id: Iaf089356230f24f871636956780cb5652fec5c42 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1876800 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 8418697eb78692882b05da42059226e3dbfce159) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902090
* servo_v4: Disable CCD (monitoring SBU) when DTS-mode disabled by a userWai-Hong Tam2019-09-302-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | The SBU monitoring logic is used for muxing the correct polarity for CCD. If the DTS-mode is disabled by a user, meaning that CCD is supposed not being used, the SBU monitoring logic can be disabled. For DP alt-mode, the SBU lines are used for AUX channel. This SBU monitoring logic affects the AUX channel, due to the strong pull-up on the USB D+ line. It should be disabled. Remove the original calls of ccd_enable(), which is called when supplying power and detecting DUT Rd/Rd or Rp/Rp. This requires PD comm. We don't want CCD depends on PD comm. BRANCH=servo BUG=b:137219603 TEST=The default role "cc srcdts", CCD works on both phyical polarity. TEST=Called "cc src", checked GPIO SBU_MUX_EN 0. Change-Id: I8f2f7bda88426e6097f0f4efd811114b7a1135c3 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1815557 Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit 19b8749c0915278171acfd83495d5a73bb359385) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1817020
* servo_v4: Disable some features to save spaceWai-Hong Tam2019-09-181-0/+2
| | | | | | | | | | | | | | | | No room left in the flash for the ToT firmware. Remove some features to save space. BRANCH=servo BUG=b:1002121 TEST=Built the servo v4 firmware, 560 bytes in flash available. Change-Id: I26aeea9cad155085bac7a349b6242d1f2958112f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1795926 Reviewed-by: Denis Brockus <dbrockus@chromium.org> (cherry picked from commit b8aa16feae8b4d66ff78ce899cbda13f7cf74316) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1811467
* servo_v4: Be a sink without PD comm when power charge-through detachedWai-Hong Tam2019-09-181-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL changes the behavior of no charge-through happens but a user explicitly sets servo v4 as a source. It is changed from "sink with PD comm" to "sink without PD comm". BRANCH=servo BUG=b:138585164, b:135035317 TEST=Manual as the following console interaction: (Plug the power cable back to servo v4) > cc src > pd 1 state Port C1 CC1, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e > cc snk > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608 > cc pdsnk > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: SNK_READY, Flags: 0x414e > cc src > pd 1 state Port C1 CC1, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e (Unplug the power cable from servo v4) > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608 (Plug the power cable back to servo v4) > pd 1 state Port C1 CC1, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e > cc pdsnk > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: SNK_READY, Flags: 0x414e (Unplug the power cable from servo v4) > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: SNK_READY, Flags: 0x414e (Plug the power cable back to servo v4) > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: SNK_READY, Flags: 0x414e > cc snk > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608 (Unplug the power cable from servo v4) > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608 (Plug the power cable back to servo v4) > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x0608 Change-Id: Ia4b6f858a4b0e22d81efbff02df4d02f3dc04bc9 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1724933 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 66bb7ba71db2a8c1233bd51d06e0ece93d89ce91) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1811460
* servo_v4: Support changing CC polarityWai-Hong Tam2019-07-232-37/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support an argument pol0/pol1 to the console command to change the CC polarity. When CC polarity change, apply the Rd/Rp to the proper CC line and fake the proper CC voltage. BRANCH=servo BUG=b:136014621 TEST=Tried the console commands: * Typed "cc src pol0" on servo v4 and checked DUT detected CC1: Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946 * Typed "cc src pol1" on servo v4 and checked DUT detected CC2: Port C0 CC2, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x4946 * Typed "cc snk pol0" on servo v4 and checked DUT detected CC1: Port C0 CC1, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608 * Typed "cc snk pol1" on servo v4 and checked DUT detected CC2: Port C0 CC2, Ena - Role: SRC-DFP-VC State: SRC_DISCOVERY, Flags: 0x1608 * Typed "cc srcdts pol0" on servo v4 and checked DUT detected CC1: Port C0 CC1, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x14946 * Typed "cc srcdts pol1" on servo v4 but resulted some hard reset issue during PD negotiation; need further investigation. Port C0 CC2, Ena - Role: SNK-UFP State: SNK_DISCOVERY, Flags: 0x10608 TEST=Ran the entire PD FAFT suite passed on both CC polarities. Change-Id: I7f983179b13e87a219bd26fe3665446df36de86e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693843 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 2340951cd98db31e971e270319f52991b62ca77d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715624
* Reland: servo_v4: Support command to limit the max_voltageWai-Hong Tam2019-07-231-3/+25
| | | | | | | | | | | | | | | | | | | | | | | firmware_PDVbusRequest forces servo v4 to different max_voltage limits to verify the PD negotiation. Add the firmware support for it. The console command usbc_action is the same as Plankton. So the test side doesn't need any change. BRANCH=servo BUG=b:134700685 TEST=Tried usbc_action command and ran firmware_PDVbusRequest passed. Old-Change-Id: I5f05d73d9a2f92fe26514285e7c251e9fa27aba8 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686221 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 167648267e5307b497ca64948f3bd79ac0327eb0) Change-Id: Ice26680c2f61ff35ea93b99226e2aa1acec856dd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715390 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com>
* servo_v4: Support sink roles with PD comm enabledWai-Hong Tam2019-07-232-2/+25
| | | | | | | | | | | | | | | | | | | For the normal lab use, emulating a sink has no PD comm, like a passive hub. For the PD FAFT use, we need to validate some PD behavior, should support sink roles with PD comm enabled. Two new roles "pdsnk" and "pdsnkdts" are introduced. BRANCH=servo BUG=b:134700685 TEST=Typed "cc pdsnk" or "cc pdsnkdts" can transit the DUT port to the PD state "SNK_READY", instead "SNK_DISCOVERY". Change-Id: If6a7c39cd296986b8b28de1c1fbe66ee8438c709 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682920 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 7d29ac01ea9c3a6ac3aba2dcace88ca43e2d8201) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686280
* servo_v4: Support dual-role portWai-Hong Tam2019-07-232-79/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support a new flag to enable DRP. The do_cc() function becomes having 4 arguments. So change to merge them into a single cc_config with different bit masks. For the force_source or force_sink role, we explicitly set the the Rp or Rd resistors on CC lines. But for DRP role, the Rp/Rd toggling is controlled by the PD state machine. So don't set any CC pull resistor for DRP. Support an "on" option in "cc" command to restore the previous role before emulating detach. Add "usbc_action drp" to toggle the DRP state, which is compatible with Plankton. BRANCH=servo BUG=b:135691171 TEST=Ran the firmware_PDTrySrc test passed, and not break all the existing PD FAFT tests. Change-Id: I3b90611c9840f502e496c42f80354e7ee002f96e Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682919 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit b1d81401eebb4444123cacac08e88ef6e38ee58d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686279
* Revert "servo_v4: Support command to limit the max_voltage"Wai-Hong Tam2019-07-231-47/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 978add22f0c63984644653ab98630ae2931214e3. Reason for revert: This conflict hasn't resolved. Original change's description: > servo_v4: Support command to limit the max_voltage > > firmware_PDVbusRequest forces servo v4 to different max_voltage > limits to verify the PD negotiation. Add the firmware support for it. > The console command usbc_action is the same as Plankton. So the test > side doesn't need any change. > > BRANCH=servo > BUG=b:134700685 > TEST=Tried usbc_action command and ran firmware_PDVbusRequest passed. > > Change-Id: I5f05d73d9a2f92fe26514285e7c251e9fa27aba8 > Signed-off-by: Wai-Hong Tam <waihong@google.com> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686221 > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > (cherry picked from commit 167648267e5307b497ca64948f3bd79ac0327eb0) > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686281 Bug: b:134700685 Change-Id: Id11f616e4e6de5f71d70a64d89bd58fe05811e15 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715389 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com>
* servo_v4: Support command to limit the max_voltageWai-Hong Tam2019-07-231-1/+47
| | | | | | | | | | | | | | | | | | firmware_PDVbusRequest forces servo v4 to different max_voltage limits to verify the PD negotiation. Add the firmware support for it. The console command usbc_action is the same as Plankton. So the test side doesn't need any change. BRANCH=servo BUG=b:134700685 TEST=Tried usbc_action command and ran firmware_PDVbusRequest passed. Change-Id: I5f05d73d9a2f92fe26514285e7c251e9fa27aba8 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686221 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 167648267e5307b497ca64948f3bd79ac0327eb0) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686281
* servo_v4: Minor update the PD policy and commentsWai-Hong Tam2019-07-231-9/+17
| | | | | | | | | | | | | | | | | | | | Update the PD policy and comments: * Only allow data role swap on DUT port; * Remove the dts mode condition to initiate a data role swap (not necessary to limit it to dts mode). BRANCH=servo BUG=b:135691171 TEST=Checked the CHG port is always UFP. TEST=Checked the DUT port is SRC/UFP, a data role swap happened (but it was initiated by DUT). Change-Id: I668703209301a9542e94768f31f6ce8e2d9eb0f4 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682918 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 598c2c11d4024ed84fa1b185ef447c8a732c8535) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686278
* servo_v4: Remove unnecessary init for GPIO MODULE_USB_PDWai-Hong Tam2019-07-232-7/+7
| | | | | | | | | | | | | | | | | | | | | | | The pd_config_init() does two things: * pd_tx_init() to init the GPIO MODULE_USB_PD; * pd_set_host_mode() to set CC pull resistors. The pd_config_init() is called on PD phy init hook. For setting CC pull resistors, calling pd_set_host_mode() is enough. Don't need to reinit GPIO MODULE_USB_PD. BRANCH=servo BUG=b:135691171 TEST=Set "cc" role to "src", "snk", "srcdts", "snkdts", and "off". TEST=Unplugged and replugged the CHG port cable. Change-Id: I1e783dfa5da4f8e8f1d9d591818eb1128b7a8caa Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682917 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a551572c396ba2e3c90f1e0581f256d6f207be2a) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686277
* servo_v4: Fake CC2 voltage when servo v4 as snkWai-Hong Tam2019-07-231-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In servo v4 hardware logic, both CC lines are wired directly to DUT. When servo v4 as a snk, DUT may source Vconn to CC2 and make the voltage high as vRd-3.0, which makes the PD state mess up. As the PD state machine doesn't handle this case. It assumes that CC2 is separated by a Type-C cable, resulting a voltage lower than the max of vRa. It fakes the voltage within vRa so the PD state machine checks the value as expected. This is an issue only happening on servo v4 as it wires both CC lines to DUT. BUG=b:134700685 BRANCH=servo TEST=Servo v4 as snk, verified the CC2 is sensed vRa, i.e. the output "CC1:0" (TYPEC_CC_VOLT_OPEN), instead of "CC1:7" (TYPEC_CC_VOLT_SNK_3_0). 2019-06-18 15:05:47 > cc snk 2019-06-18 15:05:50 cc: on 2019-06-18 15:05:50 dts mode: off 2019-06-18 15:05:50 chg mode: off 2019-06-18 15:05:50 chg allowed: off 2019-06-18 15:05:50 > C1 st2 SNK_DISCONNECTED 2019-06-18 15:05:50 C1 st3 SNK_DISCONNECTED_DEBOUNCE 2019-06-18 15:05:50 C1 st5 SNK_DISCOVERY 2019-06-18 15:05:51 > tcpc 1 state 2019-06-18 15:05:53 Port C1, Dis - CC:2, CC0:6, CC1:0 2019-06-18 15:05:53 Alert: 0x00 Mask: 0x007d 2019-06-18 15:05:53 Power Status: 0x48 Mask: 0x00 TEST=Ran the PD FAFT test firmware_PDConnect passed. Change-Id: I10f1ffe80768100ee3ed4c374598df7c2f9a8d05 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666468 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 1f14229fa7e499dfcee07d17add187598ff0a46c) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686276
* servo_v4: Remove the dts console commandWai-Hong Tam2019-06-221-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Servod now uses the "cc" console command to change the dts mode. So no one uses the "dts" command. Remove it to save the flash space (128 bytes). BUG=b:131840808 BRANCH=servo TEST=Flashed the servo v4 firmware and started servod. Tried: $ dut-control servo_v4_dts_mode servo_v4_dts_mode:on $ dut-control servo_v4_dts_mode:off servo_v4_dts_mode servo_v4_dts_mode:off $ dut-control servo_v4_dts_mode:on servo_v4_dts_mode servo_v4_dts_mode:on Change-Id: I35778ff8975af35e623a9c9c70926264161cff3d Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1669742 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Jason Clinton <jclinton@chromium.org> (cherry picked from commit 11c362df1a73980344da7aa0d62da72945f84c89) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672558
* servo_v4: Enable VBUS detection interrupts to wake PD tasks fast enoughWai-Hong Tam2019-06-182-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It fixes a hard reset issue. After a hard reset, the PD state goes to SNK_HARD_RESET_RECOVER state and waits for the VBUS "off" and then back "on" again. When the VBUS goes back to "on", it then transits to SNK_DISCOVERY state that replies the Source_Cap message. In order to make the VBUS detection fast enough, these interrupts are needed to wake the PD tasks up; otherwise, it missed the Source_Cap message BUG=b:134701032 BRANCH=servo TEST=Made servo v4 as sink and issued Hard_Reset on either DUT or servo. 2019-06-14 13:55:04 > cc snk 2019-06-14 13:55:06 cc: on 2019-06-14 13:55:06 dts mode: off 2019-06-14 13:55:06 chg mode: off 2019-06-14 13:55:06 chg allowed: off 2019-06-14 13:55:06 > C1 st3 SNK_DISCONNECTED_DEBOUNCE 2019-06-14 13:55:06 C1 st5 SNK_DISCOVERY 2019-06-14 13:55:06 C1 Req [1] 5000mV 3000mA 2019-06-14 13:55:06 C1 st6 SNK_REQUESTED 2019-06-14 13:55:06 C1 st7 SNK_TRANSITION 2019-06-14 13:55:06 C1 st8 SNK_READY 2019-06-14 13:55:07 2019-06-14 13:55:07 > pd 1 hard 2019-06-14 13:55:16 C1 st34 HARD_RESET_SEND 2019-06-14 13:55:16 > C1 st35 HARD_RESET_EXECUTE 2019-06-14 13:55:16 C1 HARD RST TX 2019-06-14 13:55:16 C1 st4 SNK_HARD_RESET_RECOVER 2019-06-14 13:55:16 Repeat msg_id[0] port[1] 2019-06-14 13:55:16 Repeat msg_id[0] port[1] 2019-06-14 13:55:16 Repeat msg_id[0] port[1] 2019-06-14 13:55:16 C1 st5 SNK_DISCOVERY 2019-06-14 13:55:16 Repeat msg_id[0] port[1] 2019-06-14 13:55:16 C1 HARD RST RX 2019-06-14 13:55:16 C1 st4 SNK_HARD_RESET_RECOVER 2019-06-14 13:55:17 C1 st5 SNK_DISCOVERY 2019-06-14 13:55:17 C1 Req [1] 5000mV 3000mA 2019-06-14 13:55:17 C1 st6 SNK_REQUESTED 2019-06-14 13:55:17 C1 st7 SNK_TRANSITION 2019-06-14 13:55:18 C1 st8 SNK_READY 2019-06-14 13:55:18 C1 Req [1] 5000mV 3000mA 2019-06-14 13:55:18 C1 st6 SNK_REQUESTED 2019-06-14 13:55:18 C1 st7 SNK_TRANSITION 2019-06-14 13:55:18 C1 st8 SNK_READY Issued "pd 0 hard" on DUT: 2019-06-14 13:56:07 > C1 HARD RST RX 2019-06-14 13:56:11 C1 st4 SNK_HARD_RESET_RECOVER 2019-06-14 13:56:12 C1 st5 SNK_DISCOVERY 2019-06-14 13:56:12 C1 Req [1] 5000mV 3000mA 2019-06-14 13:56:12 C1 st6 SNK_REQUESTED 2019-06-14 13:56:12 C1 st7 SNK_TRANSITION 2019-06-14 13:56:12 C1 st8 SNK_READY Change-Id: I0cc80515df8044ec07fa6795d3723aca2a3dc0ef Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660125 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 67c7d647103ea88fa0957a0e9538316901828c64) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666352
* servo_v4: Implement CC detach and fakedisconnect on servo v4Wai-Hong Tam2019-06-182-38/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DUT may have multiple USB Type-C ports. In order to identify a pair of PD port partners, the PD FAFT tests asks one partner to emulate a detach and then checks the other partner if it sees a proper status. This requires to implement a CC detach on servo v4. A console command 'fakedisconnect' (similar to plankton) is introduced to disconnect for a given period and then connect back. BUG=b:131840808 BRANCH=servo TEST=Manuall tested the commands on servo v4 console to emulate detach. . > cc . cc: on . dts mode: on . chg mode: on . chg allowed: on . > pd 1 state . Port C1 CC1, Ena - Role: SRC-UFP State: 23(SRC_READY), Flags: 0x1415e . > cc off . cc: off . dts mode: on . chg mode: on . chg allowed: off . > pd 1 state . Port C1 CC1, Dis - Role: SNK-UFP State: 2(SNK_DISCONNECTED), . Flags: 0x0000 Checked the DUT EC console to verify the port status as detached. . > pd 0 state . Port C0 CC2, Ena - Role: SNK-DFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 Made the servo v4 connect back. . > cc srcdts . cc: on . dts mode: on . chg mode: on . chg allowed: on . > pd 1 state . Port C1 CC1, Ena - Role: SRC-UFP State: 23(SRC_READY), Flags: 0x1415e Checked the DUT EC console to verify the port status as connected. . > pd 0 state . Port C0 CC2, Ena - Role: SNK-DFP State: SNK_READY, Flags: 0x14946 Typed 'fakedisconnect' command to disconnect for a period. . > fakedisconnect 1000 2000 . Fake disconnect for 2000 ms starting in 1000 ms. Verified DUT got disconnected and then connected back. Change-Id: Ie29cfd4f55ac48b593f71d580762ff5e77ee9602 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1603469 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit bf5323de2d1a4d184532b9f4af708f314c5d3047) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666348
* servo_v4: Disable syslock and flash commandsWai-Hong Tam2019-06-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Servo_v4 is used as a testing equipment, not like a normal Chromebook. So we don't syslock the system and WP the flash. Disable these commands to save space. Before: 1136 bytes in flash and 2336 bytes in RAM available on RO After: 1712 bytes in flash and 2344 bytes in RAM available on RO BUG=b:131840808 BRANCH=servo TEST=Built and flashed the servo v4 firmware. Started servod and verified some functions. Change-Id: Ic84d48d984ae9abb1cbbb7b90aaece1f99d9d729 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1613804 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit faff726eaf8bb86b195a19996f8d43e23014450f) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1642352
* servo_v4: Disable unused features to reduce spaceWai-Hong Tam2019-06-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The servo_v4 is almost out-of-space. Disable some unused features and console commands to reclaim some space. Before: 176 bytes in flash and 4392 bytes in RAM available on RO After: 1264 bytes in flash and 4400 bytes in RAM available on RO BUG=b:131840808 BRANCH=servo TEST=Built and flashed the servo v4 firmware. Started servod and verified some functions. Change-Id: Ic0e76794d0603fccc2f733cad388f54650d2cd45 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1597959 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> (cherry picked from commit a6bfa5e7a8c013ffb9b48d437d5758f46c38ebb8) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1642351
* servo_v4: Remove console commands to save flash spaceDaisuke Nojiri2019-06-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the following commands: CONFIG_CMD_ACCELSPOOF CONFIG_CMD_FASTCHARGE CONFIG_CMD_GETTIME CONFIG_CMD_MEM Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ic6e0bd4441f17636d77468874646e3aabe0d250b Reviewed-on: https://chromium-review.googlesource.com/1475770 Commit-Ready: Tony Zou <zoutao@huaqin.corp-partner.google.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit d9a3b7c58a441cfcfb32b05fe3bd112c9caf78d6) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1626037 Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* stm32: Decouple printf logic from directly calling USB console driverWai-Hong Tam2019-05-132-56/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling printf functions, it was to call the USB console driver directly, i.e. copying all the bytes to USB package buffer and enabling the transmission. If the next printf is called immediately before the USB transmission is done, it will wait (polling the EP_TX_VALID status). This implementation limited each printf function can only transmit 64 bytes, i.e. the USB max package size. The remaining bytes will be dropped silently. To fix this issue, this CL puts a queue between the printf logic and the driver. The size of the queue is 2048-byte (no overflow happened on a normal boot and console commands). The printf logic now fills the queue and schedules a deferred hook to handle the transmission. When the transmission is done, an interrupt will be triggered that schedules the deferred hook again to check any remaining bytes need to be transmitted. For the incoming bytes, replace the circular buffer to a queue structure for better reusability. No major logic changes. BRANCH=servo BUG=b:129423678 TEST=Manually added a printf call to show >64 bytes and verified it. TEST=Manually added a printf call to show >2048 bytes and the bytes after the 2048-th dropped silently. Change-Id: Icb2310421d7bcbbff8d7cd753c732390acc43ab8 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1597960 Commit-Ready: Todd Broch <tbroch@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit e02b08ceca36300a602c50b2b3cc81f3a5385978) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1609602 Commit-Queue: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* servo_v4: disable PD entirely when in SNK.Nick Sanders2019-04-091-4/+9
| | | | | | | | | | | | | | This prevents the system from negotiating power or reenabling dualrole after it's turned off in board.c. BUG=b:129882930 BRANCH=servo TEST=cc snkdts stays snk. Change-Id: I0a05eb9e8073cec7da884e071e023bcddadb130f Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1555024 Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* servo_micro: Increase maximum I2C-over-USB write and read sizes.Matthew Blecker2019-04-021-0/+35
| | | | | | | | | | | | | | | | | BRANCH=none BUG=b:79684405 TEST=This makes block_write_size up to 254B in iteflash work, and makes 256B verification reads work. Change-Id: I887f0eaacc87428a4646007520f27bdf5aaa231a Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1351517 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit c1b0bf4bd57ec87a55ffbae4d08ae7422d1a6e44) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1539425 Commit-Queue: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* usb_i2c: provide a way to communicate non-i2c commandsVadim Bendebury2019-04-022-1/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | On some occasions there might be a need to request an action from the DUT which is related to i2c operations but can not be performed through an i2c transaction. For instance when one need to generate the sync sequence on the EC i2c interface before the EC can be programmed. This patch introduces a facility which allows to register a handler for commands sent on this special address which is picked at 0x78, which becomes 0xf0 during write transaction address cycle. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=tested along with the rest of the patches to trigger generating of the ITE EC debugger sync sequence. Change-Id: I269d4b8073b0d02f96ca526f221c02c38a036f3d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1214542 Reviewed-by: Randall Spangler <rspangler@chromium.org> (cherry picked from commit 4170abd620557cddef031546ba0a249b834f7b38) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1549605 Commit-Queue: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* usb_i2c: extend protocol to allow longer writesVadim Bendebury2019-04-022-29/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | It is necessary to be able to send longer than 255 byte packets over the USB I2C bridge. This patch introduces a backwards compatible protocol extension to the to allow that. Namely, the top 4 bits of the byte previously used as the port number are now used as the top 4 bits of the 12 bit write counter field. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=tested along with patches modifying Cr50 and iteflash for operating over CCD. Verified that the ITE EC programming requiring 256 byte write transactions succeeds. Change-Id: I21475c8d87a6a858ff9ad96dae87388604bbbf2d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1256059 Reviewed-by: Matthew Blecker <matthewb@chromium.org> (cherry picked from commit 83af9ed091c8a10bae1fca0434d30ab66a3a07ab) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1549604 Commit-Queue: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Tested-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* servo_v4: detect SBU more reliablyNick Sanders2019-04-021-104/+93
| | | | | | | | | | | | | | | | | | | | | | | SBU orientation was detected in a one-shot check, that didn't ensure that the line was idle. Change to detect SBU orientation independently of PD state, and only while it's disconnected from the host. Delete keepalive and ccd_enable as they aren't meaningful for the new mechanism. BUG=b:128646723, chromium:942130 BRANCH=servo TEST=unplug a lot of times, orientation always correct. Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I16c770b9d8d7a0c2d90aa214cb8cdec4c36a7303 Reviewed-on: https://chromium-review.googlesource.com/1529724 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Todd Broch <tbroch@chromium.org> (cherry picked from commit 0490e8afde1b90cb600e68630a1ebe08a88cb681) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1545083
* servo_v4: update board_select_rp_valueNick Sanders2018-09-291-2/+24
| | | | | | | | | | | | | | | | | This function sets the default Rp value, but should not enable Rp if it's not already enabled. BRANCH=servo BUG=b:116630203 TEST=check CC lines after booting with/without charge through. Change-Id: Ie9709796940cf908b9af3701d2123f16596f04e0 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1244381 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit a2c0c599f3e2f458735c17e42843086cf1eff989) Reviewed-on: https://chromium-review.googlesource.com/1252446
* servo_micro: Allow setting the baud rate for usartv2.3.0Nicolas Boichat2018-09-078-13/+74
| | | | | | | | | | | | | | | | | | | | | | | | | We set the baud rate in increments of 100 baud, to avoid overflowing the 16-bit wValue integer (921600 is the highest we are likely to use). Also, increment the buffer size for USART3 to 1024 bytes. That helps a bit to avoid losing characters, but we still can't keep up if the host is printing at maximum speed. BRANCH=servo BUG=chromium:876651 TEST=baud usart2/3/4 115200 in servo_micro console TEST=dut-control cpu_uart_baudrate:921600 seq 1 1000 shows numbers 1 to 226 before buffer overflows Change-Id: Ifca266189f93def493f207dd29d2cceca4d8d68f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1189782 Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit 7eb9ff3cfcf4b96356050da66bd957225bef6044) Reviewed-on: https://chromium-review.googlesource.com/1213552 Commit-Queue: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org>
* servo_micro: Increase USB stream TX size to 64 bytesNicolas Boichat2018-09-041-1/+1
| | | | | | | | | | | | | | | | | Bigger packets help increase the bandwidth a little bit. BRANCH=servo BUG=chromium:876651 TEST=With the servod patch to increase read sizes to 256 bytes (CL:1202090), usart_test usart3 shows an improved time to transfer 64kb from 0.671 seconds to 0.611. Change-Id: I849c9cea70b25b5b2d6cd7ab15f56b81cdb297d9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1202545 Reviewed-by: Nick Sanders <nsanders@chromium.org> (cherry picked from commit c2154182985c384f8484f03a8d1d2079ba8858c9) Reviewed-on: https://chromium-review.googlesource.com/1203837
* Revert "ec3po: quit console & interpreter loop when parent process changes."Nick Sanders2018-08-272-10/+6
| | | | | | | | | | | | | | | | | | This reverts commit 3b39bc56d38511e10871447392b709b3b8e65637. Reason: wedges consoles on servod. BRANCH=None BUG=b:113246887 TEST=reverting unbreaks servod Change-Id: I2f4dd65727347ce4757c4863664e3b2e46c826fc Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1191383 Tested-by: Raul E Rangel <rrangel@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* servo_micro: Fix DMA mappingsNick Sanders2018-08-272-15/+35
| | | | | | | | | | | | | | UART3 and 4 had DMA collisions. Remove DMA from UART4. BRANCH=servo-9040 BUG=b:112701646,chromium:865478 TEST=reboot EC, no crashy Change-Id: Ic44b363dafe938d6420b350eb1c5ab796da81f3c Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1188514 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: don't clear DEVCNT_F_SPI_TRIS bit for chips that use intenal flashCHLin2018-08-261-1/+1
| | | | | | | | | | | | | | | | | | As documented in the datasheet, NPCX_DEVCNT_F_SPI_TRIS must be 1 for ECs that use internal flash (e.g., NPCX79nF and NPCX797W). BRANCH=none BUG=b:112906111 TEST=No build errors for make buildall. Flash image on npcx7_evb; check this bit is not cleared. Flash image on yorp; check the platform boots up to OS screen. Change-Id: I533553ad91ce0ecc79fc55b86aa83bbbcf514d89 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1188180 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cr50: enable ccd open from the consoleMary Ruthven2018-08-251-0/+2
| | | | | | | | | | | | | | | | | | | Enable running ccd open from the console. Do not require dev mode to run the command. PREPVT ONLY. DO NOT MERGE INTO MP. BUG=b:112861587 BRANCH=cr50-prePVT TEST='ccd open' can be run on the console, and it doesn't require dev mode. Change-Id: Ie666d3bdf56a525deb7764bbcd03676174745cd3 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1188928 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ccd_config: add flag restricting ccd openMary Ruthven2018-08-252-0/+4
| | | | | | | | | | | | | | | | | On prePVT images we wan't to allow ccd open from the console without dev mode enabled. This change adds a config option limiting ccd open. BUG=b:112861587 BRANCH=cr50 TEST=ccd open is still disabled from the console unless the password is set. Change-Id: I2adbf9b0e900a693ab513a6bf6650b320b7320d4 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1188927 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nocturne: Remove CONFIG_SYSTEM_UNLOCKED.stabilize-11005.BAseda Aboagye2018-08-251-3/+0
| | | | | | | | | | | | | | BUG=b:113127952 BRANCH=firmware-nocturne-10984.B TEST=Enable HW/SW WP, plug in a PD charger, verify no PD communication is done in RO. Change-Id: Idc9219c70662b1b51e228863e2bd51a72cecb2b1 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1188929 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* servo_v4: clear bbram PD state on rebootNick Sanders2018-08-251-0/+6
| | | | | | | | | | | | | | | Preserved bbram state causes failure to reinit on reboot. Clear on board init. BRANCH=None BUG=b:111573811 TEST=PD reinits on reboot. Change-Id: Ifdf98b5793cb99e2900ac5dc53263a86317b6b07 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187883 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Fleex: Modify shipping mode register and FETelthanhuang2018-08-251-10/+9
| | | | | | | | | | | | | | | | | | | | | | | status register and data Modify LGC/BYD board_battery_info of shipping mode reg_addr and LGC/BYD/Simplo FET status of reg_addr/reg_mask BUG=b:112322236,b:112237278 BRANCH=none TEST=Use "ectool batterycutoff", system can shutdown. Plugin AC can power on system and battery return BATTERY_NOT_DISCONNECTED. Change-Id: I0d7a2b2c9d27a058b67f7b48970aaaab2ebee9b8 Signed-off-by: elthanhuang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1170669 Commit-Ready: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* bd99992: add some more register definitionsCaveh Jalali2018-08-242-6/+18
| | | | | | | | | | | | | | | | | this adds definitions for some additional PMIC registers we're using in our codebase. BUG=b:112732855 BRANCH=none TEST=flashed atlas with new EC build Change-Id: Ibad7b11b3770f00c925c2d8fc3b24109147aa643 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187899 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* cheza: Use BC1.2 to detect VBUS presentWai-Hong Tam2018-08-241-1/+1
| | | | | | | | | | | | | | | | | | | There are several ways to detect VBUS present. Using the BC1.2 to detect is through a GPIO. It is more effective than talking to the TCPC chip over I2C comm. Change the config from CONFIG_USB_PD_VBUS_DETECT_TCPC to CONFIG_USB_PD_VBUS_DETECT_CHARGER. BRANCH=none BUG=b:112179392 TEST=Plugged and unplugged charger to port-0 and port-1. Verified the charging state correct. Change-Id: I9dd69cd17099b5794988efca9d8c7a82af3614a5 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1170126 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* chip/npcx: Make check_reset_cause() staticSimon Glass2018-08-241-3/+2
| | | | | | | | | | | | | | | This function is not called from outside this file so make it static. Also drop a pointless comment, and rename the function since the 'system' prefix suggests it is defined in system.h (which it is not). BUG=chromium:876737 BRANCH=none TEST=make -j50 BOARD=grunt Change-Id: Ic429fb1da2e56e1888e008f4739c90e8ed2c1947 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1184975 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec3po: quit console & interpreter loop when parent process changes.Ruben Rodriguez Buchillon2018-08-242-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Right now, when the parent process dies ungracefully - say kill -9 - then the interpreter, and console processes remain active. This leads to bugs in the servod implementation from holding on to sockets, to reinitialization issues of a new instance on the same servod device. This change quits the loops inside console & interpreter as soon as the parent pid changes (i.e. the parent dies). BRANCH=None BUG=chromium:841121 TEST=sudo servod -b soraka ps aux | grep servod >xxxxx servod >xxxxy servod >xxxyx servod >xxxaa grep servod sudo kill -9 xxxxx ps aux | grep servod >xxxab grep servod Before this, just kill -9 on the main thread did not take the children with it. Change-Id: I547bd92bf8732bff8aef2b72840417c809ba27d6 Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1186299 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* power/mt8183: Power sequence from S5, not G3Nicolas Boichat2018-08-241-19/+22
| | | | | | | | | | | | | | | | | | | The previous code was switching on the AP on G3 to S5 transition, this causes problems as there is a 10s timeout in the S5 to G3 transition, so we would not be able to boot the AP from S5. The only difference now between S5 and G3, is the case where the PMIC fails to shut down properly: we only enter G3 if the PMIC shuts down as expected. BRANCH=none BUG=b:109850749 TEST=make BOARD=kukui -j Change-Id: I260146e6d4622a76ad3a53d67fdde43a8669697c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1181008 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cheza: Configure ANX3429 interrupt as open-drainWai-Hong Tam2018-08-234-1/+16
| | | | | | | | | | | | | | | | | This interrupt pin by default is a push-pull. It causes leak to EC VSPI power during EC watchdog reset. As in our design, we use this interrupt pin as open-drain. Should configure the register to make it open-drain. BRANCH=none BUG=b:112906111 TEST=Flashed the EC image to Cheza rev-2 board. Typed "reboot" command and then EC reset properly. Change-Id: Iee5db3cb5b5291778d97dee4fc70369d34344ce7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1185871 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* octopus: update bip for lower power hibernateJett Rink2018-08-233-24/+52
| | | | | | | | | | | | | | | | | | | | Pulled hibernate_wake_pins into each EC variant because the 4/5 item array was getting pretty fractured. Bip EC now wakes up based on PPC interrupts instead of AC_PRESENT. This allows the PPCs to disable the SNK FET (and all OVP circuitry). The power won't get from the USB-C connector to the battery charger until the EC wakes up, but that isn't an issue. BRANCH=none BUG=b:111006203,b:111520593 TEST=bip PD_A rail is 3.97mW during hiberate with this CL stack Change-Id: I2d08ca5bb2b0b7181c7a0f0c5894b8f59ccbd85f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1166184 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
View Lorry Controller Status