summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* common: motion: fix races at shutdownfirmware-rammus-11275.BGwendal Grignou2022-10-211-7/+16
| | | | | | | | | | | | | | | | | | | | | | Do not use collection_rate blindly after a function may have slept: the HOOK task could have run suspend() or suspend() call and set it to 0. Fixes 104f5257 ("motion: Control on which task sensor setting functions are running on") [CL:2553347] BUG=b:218982018, b:176918310, b:170703322 BRANCH=kukui TEST=unit test. Change-Id: I9ef13ceca195db4b48866f1e53f9408fb2bbf595 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2616137 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> (cherry picked from commit ea99e40f31445e67659c09b32cab6857cad8b83e) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508418 Reviewed-by: Ricardo Quesada <ricardoq@chromium.org>
* motionsense: prevent loop after missing eventsJett Rink2022-05-171-8/+10
| | | | | | | | | | | | | | | | | | | | | | We don't need to loop to figure out when to schedule the next sensor collection event, just schedule it as soon as possible. This eliminates a watchdog reset when we miss scheduling the sensor task and get really far behind. BRANCH=none BUG=b:133190570 TEST=normal operation is fine, based on longs of failing results in bug, this should prevent the watch reset. Change-Id: I3001028ba393b51d1958f0136ba040eaee5e52d1 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1658521 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> (cherry picked from commit 8374923a60c8b63b7bb2c1823e4f5b6078544e44) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508416 Reviewed-by: Yuval Peress <peress@google.com>
* Panic: Save LR and code location in HFSRDaisuke Nojiri2022-03-284-9/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Nami's PMIC reset clears panic data, we currently report only a few fault registers (HFSR, MMSR, etc.), IPSR, r4, and r5. These are included in a feedback report but not very useful. To debug a crash happening remotely, this patch makes the assert handler, the watchdog handler, and the panic handler store PC, LR, and some additional info. | regs[1] | regs[3] | regs[4] | HFSR | (IPSR) | (r4) | (r5) | [29:2] -------+---------+----------+----------+-------------------- Assert | n/a | __func__ | __FILE__ | [29:26] Flags (=3) | | | | [25:10] Line# | | | | [ 9: 2] Task# -------+---------+----------+----------+-------------------- WDT | LR | Reason | PC | [29:26] Flags (=4) | | | | [ 9: 2] Task# -------+---------+----------+----------+-------------------- Panic | IPSR | LR | PC | n/a -------+---------+----------+----------+-------------------- Note that this patch is created under several constraints imposed by the released RO. Some of the constraints are as follows: - It's the RO not RW who saves the panic data into BBRAM. This is for avoiding executing extra code in a restricted environment (= panic). - If RO sees a watchdog reset without reason == PANIC_SW_WATCHDOG, it stores PANIC_SW_WATCHDOG in r4 and clears r5 and IPSR. - BBRAM is already used up to the max (64 bytes). Obviously, a patch for ToT would be very different (and much cleaner) since it's free from these constraints. Most importantly, there is no PMIC reset which erases panic data. > crash assert ASSERTION FAILURE '0' in command_crash() at common/panic_output.c:165 Rebooting... --- UART initialized after reboot --- [Reset cause: soft] [Image: RO, nami_v1.1.8956+f067821734 2021-11-09 12:31:41 some@host] [0.003853 init buttons] [0.004072 Inits done] Restarting system with PMIC. > panicinfo ASSERTION FAILURE in command_crash() at common/panic_output.c:165 r0 : r1 : r2 : r3 : r4 :100a9f82 r5 :100a89e0 r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = c029428, dfsr = 0, ipsr = 100995ad > crash divzero === PROCESS EXCEPTION: 06 ====== xPSR: 41000000 === r0 :00000000 r1 :100a8f09 r2 :400c4000 r3 :00000000 r4 :1009956f r5 :1009956e r6 :200c07c4 r7 :100a4fe3 r8 :100a4fde r9 :100a3a54 r10:00000000 r11:200c07d2 r12:00000000 sp :200c4508 lr :1009956f pc :1009956e Undefined instructions mmfs = 10000, shcsr = 70008, hfsr = 0, dfsr = 0, ipsr = 00000006 =========== Process Stack Contents =========== 200c4528: 00000002 200c4548 200c07c4 200c0400 200c4538: 00000002 1008d2c7 00000000 200c07c4 200c4548: 200c07c4 200c07ca 00000000 00000000 200c4558: 00000000 00000000 00000000 00000000 Rebooting... > crashinfo === PROCESS EXCEPTION: 06 ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :1009956f r5 :1009956e r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : Undefined instructions mmfs = 10000, shcsr = 0, hfsr = 0, dfsr = 0, ipsr = 00000006 > crash watchdog >### WATCHDOG PC=100995ae / LR=100995ad / pSP=200c4508 (task 10) ### Time: 0x0000000009dd5f1d us, 165.502749 s Deadline: 0x0000000009de2ab3 -> 0.052118 s from now Active timers: Tsk 14 0x0000000009de2ab3 -> 0.052118 Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000001 134.736448 80/672 1 R HOOKS 80000000 0.935280 648/800 2 USB_CHG_P0 00000000 0.001806 312/672 3 USB_CHG_P1 00000000 0.004606 320/672 4 R CHARGER 80000000 1.657817 424/800 5 R MOTIONSENSE 80000004 1.789985 560/928 6 CHIPSET 00000000 0.000396 296/800 7 KEYPROTO 00000000 0.002983 312/672 8 PDCMD 00000000 0.000065 112/672 9 R HOSTCMD 00000001 0.517519 568/800 10 R CONSOLE 00000000 2.074095 332/800 ... > panicinfo > ### WATCHDOG PC=100995ae / LR=100995ad / task=10 r0 : r1 : r2 : r3 : r4 :dead6664 r5 :100995ae r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : mmfs = 0, shcsr = 0, hfsr = 10000028, dfsr = 0, ipsr = 100995ad BUG=b:200593658 BRANCH=Nami TEST=Sona. Run crash assert. Verify function name, file name, line number, task id are stored in r4, r5, ipsr by panicinfo after PMIC reset. Change-Id: I55b142ac4de14c05a8184a66ed127c9cbcd29745 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271351 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457946 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Tested-by: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* watchdog: Save LR in panic data when watchdog triggersDaisuke Nojiri2022-03-281-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | We currently save a panic reason (e.g. PANIC_SW_WATCHDOG), PC, task index but not LR. LR often points to the actual code causing the crash because PC points to a generic API (e.g. udelay). This patch makes the watchdog handler store LR to cm.hfsr. It is for HardFault status register but it is probably the least informative register used by chip_panic_data_backup/restore of the existing RO. BUG=b:200593658 BRANCH=Nami TEST=Sona. Run crash watchdog. Verify panic_data_print prints LR. Change-Id: Icf9fffe1a8eed0d3b7e8d36f9c6234fe56133ea4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3218118 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457945 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Tested-by: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* mec1322/timer: Unroll udelayDaisuke Nojiri2022-03-281-0/+11
| | | | | | | | | | | | | | | | This patch flattens udelay by unrolling __hw_clock_source_read. This increases the chance that we record LR of the instruction near which an infinite loop happened. BUG=b:218982018,b:200593658 BRANCH= TEST=buildall Change-Id: I8127e9a3308c161fd064e78048d82972bb57e464 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit f0a9a2701fee604ec721b6a23173cec12cd8f4f0) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508423
* npcx/timer: Unroll udelayDaisuke Nojiri2022-03-281-0/+21
| | | | | | | | | | | | | | | | | This patch flattens udelay by unrolling __hw_clock_source_read. This increases the chance that we record LR of the instruction near which an infinite loop happened. BUG=b:218982018,b:200593658 BRANCH= TEST=Sona. Run crash assert. Hack battery command to trigger WD reset. Verify LR points to the root causes. Change-Id: Ibd6cbcf18ab6d58c06ddfd19021058268289bf00 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit cc1d30dd2bd3b92d29f5ffb942d016bc207e2ad0) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508422
* timer: Make udelay overridableDaisuke Nojiri2022-03-283-7/+2
| | | | | | | | | | | | | | | | | This patch defines udelay as overridable so that individual projects can implement customized versions. CONFIG_HW_SPECIFIC_UDELAY is no longer needed. BUG=b:218982018,b:200593658 BRANCH=None TEST=buildall; zmake testall (cherry picked from commit 5b4d9332d123f1c7dfca81b1ccaa5a4a39d72572) Change-Id: I291151755c3d714db6863749d66579007eb73ecd Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508421
* ectool/panicinfo: Print extra cortex-m fault registersDaisuke Nojiri2022-03-281-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes ectool panicinfo print extra cortex-m fault registers, including CFSR, HFSR, and IPSR. Saved panic data: === PROCESS EXCEPTION: ad ====== xPSR: ffffffff === r0 : r1 : r2 : r3 : r4 :dead6664 r5 :100995ae r6 :00000000 r7 :00000000 r8 :00000000 r9 :00000000 r10:00000000 r11:00000000 r12: sp :00000000 lr : pc : cfsr=00000000, shcsr=000000000, hfsr=10000028, dfsr=00000000, ipsr=100995ad BUG=b:218982018,b:200593658 BRANCH=None TEST=Run on Nami. See a sample output above. Change-Id: I56ecbefa2414553ab2204f113bedcad67b5ccad6 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3271886 Reviewed-by: caveh jalali <caveh@chromium.org> (cherry picked from commit 0819d1e49b3dbc2416610e005af090249860673c) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3456703
* common: Define markers for weak symbolsDaisuke Nojiri2022-03-281-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces macros to mark weak symbols. These macros are used to annotate weak definitions, declarations, and overriding definitions. __override_proto: declarations __override: definitions which take precedence __overridable: default (weak) definitions Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:218982018,chromium.org/964060 BRANCH=none TEST=buildall Change-Id: I44cec41e0523e285db19a890d084b52337f64a9c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1633911 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> (cherry picked from commit a5c17b44c506979a56cf7ebcaf03ef86f406a3c4) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508420
* Rename Cortex-M MMFS to CFSRPeter Marheine2022-03-285-58/+42
| | | | | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=b:218982018 BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org> (cherry picked from commit 124b2a8654b1bca281277b581fb79daeb1bdadde) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457944
* cortex-m/panic: Introduce CONFIG_PANIC_STRIP_GPR optionPatryk Duda2022-03-283-6/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | If set, this option will prevent saving General Purpose Registers during panic. When software panic occurs, R4 and R5 will be saved, because they contain additional information about panic. This should be enabled on boards which are processing sensitive data and panic could cause the leak. BUG=b:218982018,b:193408648 BRANCH=none TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo' to check what was saved. When CPU exception occurred registers R0-R12 should be set to 0. In case of software panic, R4 and R5 can contain panic reason and additional information. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> (cherry picked from commit 0bb062c8cd7c201571da60edd828c007dcbc436c) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508419 Reviewed-by: Patryk Duda <patrykd@google.com>
* bmi160: exit IRQ loop if error during reg readJett Rink2022-03-101-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | The IRQ handler for bmi160 continues to loop until all of the interrupt reasons are handled; however, if the read fails the interrupt variable will be in an unknown state. We can either return early if there was an error or we can set the interrupt variable to 0 before the read call. Either way the loop exits. BRANCH=none BUG=b:119093572 TEST=On Bobba360 with a solid repro case of the watchdog reset, this change avoids the watchdog reset. Change-Id: I482f074b6e9e7c183def8ce17157ed28ca96b1c9 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1378908 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> (cherry picked from commit 4d15f8668fbadac39604c6e015a86c1634162584) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3515353 Reviewed-by: Ricardo Quesada <ricardoq@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org>
* rammus: Disable HC debug by defaultGwendal Grignou2022-02-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | Similar to commit 27e8d040b368 ("nocturne: Disable HC debug by default"). When sensors are in use, host queries EC often. BUG=b:205354460 TEST=compile. Apply change in rammus branch, check on DUT that host command messages are gone. BRANCH=rammus Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Ia828428ab940a0c7faa627fa3655b4f7ce5cd9b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3456704 Reviewed-by: Ricardo Quesada <ricardoq@chromium.org> (cherry picked from commit d059ea64ba23dff66392677367cf70c26e20cf6a) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3466430 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Tested-by: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* rammus: gryo sensor add 2nd source ICM40608Michael5 Chen12021-09-285-2/+97
| | | | | | | | | | | | | | | | | | | gryo sensor add 2nd source icm40608 BUG=b:192817920 BRANCH=rammus TEST=make BOARD=rammus Set CBI SSFC 0x10 and using command "watch ectool motionsense lid_angle" for icm-40608. Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: If64ee373c0c63e074b11b8a37c9d67c70d409f40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180700 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit 9fc70659ae9cc8350e8734471bcffb55b2580f74) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3189456 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* board: nucleo-f411re: create icm426xx development platformJean-Baptiste Maneyrol2021-09-274-18/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use icm426xx chip instead of bmi. Add SPI slave + interrupt to interface with AP (SPI1 + PA1). Add SPI master interface using SPI2 for the sensor (optional). Fix board init hook priority to be run after motionsense init. Increase task stack sizes. Conflicts: board/nucleo-f411re/board.c: Just change i2c address, SPI and frequency support not in this branch. board/nucleo-f411re/board.h: CONFIG_ACCEL_FIFO_SIZE does not exist. BUG=chromium:1117541, b:192817920 BRANCH=rammus TEST=ectool && tast run hardware.SensorRing Cq-Depend: chromium:3099546, chromium:3121867 Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I860b669fd3d2ee196a66e5c80cdc0835b4e5bc73 (cherry picked from commit a4b8af57d15111440893759acd5d90bfc21d8c58) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3121866 Reviewed-by: JuHyun Kim <jkim@invensense.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: JuHyun Kim <jkim@invensense.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Auto-Submit: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* driver: icm426xx: discard first data instead of sleepingJean-Baptiste Maneyrol2021-09-273-22/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | Sleeping when turning a sensor on/off is problematic when the other sensor is running. Replace sleeping by discarding first events until sensor is stabilized. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn sensor on/off when the other is running using cros-ec iio devices Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I61801970b12f9fbdcc2cd96cb4df1edae5ed521f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682715 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit 71d6b16eff18aab1f7c592a75e5489a4f14b8790) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128756 Reviewed-by: JuHyun Kim <jkim@invensense.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* driver: icm426xx: change accel oscillator to RC clockJean-Baptiste Maneyrol2021-09-272-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | When using accel low-power with WakeUp oscillator, turning gyro on switch directly to PLL mode and provokes glitch on ODR. Use RC clock oscillator for accel low-power to avoid this glitch. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn gyro on when accel is running using cros-ec iio devices and check that odr stays consistent. Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I51435eb9533a1fa16bf695e468854156c16d3296 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2679700 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit ae50227d0d5b9c135e474bbfd3bb8cce6efef71f) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128755 Reviewed-by: JuHyun Kim <jkim@invensense.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: JuHyun Kim <jkim@invensense.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* driver: icm426xx: update odr before turning sensor onJean-Baptiste Maneyrol2021-09-271-9/+9
| | | | | | | | | | | | | | | | | | | | | | | Prevent to have the first event in 1 ODR and the second in another. Conflicts: driver/accelgyro_icm426xx.c: IS_ENABLED is not in this branch. BUG=chromium:1175757 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer TEST=turn sensor on/off and change odr using cros-ec iio devices Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I501bf14e70fd7180c7e68385ef4afb5934d7d37a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2679699 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit ba264bb932fcfa46378e68c4276d1db01c577ebf) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128754 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* driver: icm426xx: Use calibration unit to set/get offsetGwendal Grignou2021-09-271-17/+15
| | | | | | | | | | | | | | | | | | | | | | | EC interface use constant (not range dependent) units to get/set offsets. Use them in icm426xx driver. Conflicts: driver/accelgyro_icm426xx.c: default range is not in rammus branch, change original driver. BUG=b:177292639 BRANCH=hatch,nami,kukui,dedede,grunt,zork,octopus,volteer,rammus TEST=compile Change-Id: I6e6b1551464ea389db34646ba5b2bb553d683d7a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657955 Reviewed-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> (cherry picked from commit 0438e061c30640f4d72213fd09f2f8ba334c22ae) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128753 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* icm426xx: reset data rate when initDavid Huang2021-09-271-0/+3
| | | | | | | | | | | | | | | | | | | | | When icm426xx init, reset data rate to enable sensor. Conflicts: driver/accelgyro_icm426xx.c: readd saved_data variable. BUG=chromium:1160266 BRANCH=main TEST=Check ectool motionsense get data after shutdown and power on. Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I0a1042eaf6dbdb132c4bb50975eae3c6f0cfad00 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597131 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> (cherry picked from commit 65bc9015e5e2c7f73ed93ad652498a3cf67ed9fd) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128752 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* driver: add ICM-426xx driver supportJean-Baptiste Maneyrol2021-09-277-0/+1552
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add ICM-426xx accel/gyro driver code. Conflicts: - SPI connection not supported. Remove i2c_spi_addr_flags and associated code. - Remove set/get_scale, not supported in branch. BUG=chromium:1117541, b:192817920 BRANCH=rammus TEST=ectool motionsense fifo_read && tast run hardware.SensorRing Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Change-Id: I83fe48abc6aa9cde86576a777ac4272d90fac597 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317888 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3099546 Reviewed-by: JuHyun Kim <jkim@invensense.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Tested-by: JuHyun Kim <jkim@invensense.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* driver: add icm426xx chip type defineJean-Baptiste Maneyrol2021-09-272-0/+4
| | | | | | | | | | | | | | | | | | | | | Add new enum motionsensor_chip and update ectool motionsense. BUG=chromium:1117541 BRANCH=None TEST=ectool motionsense info Cq-Depend: chromium:3099546 Signed-off-by: JuHyun Kim <jkim@invensense.com> Change-Id: I07736d61bdb7332bfdc44c8f7294233e43a6e00d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2374647 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> (cherry picked from commit deed6c7cd265fe0cbfd2d64e3082cd8d8b9a2f38) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3121867 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* i2c: add generic read/modify/write operationsDenis Brockus2021-09-272-0/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | i2c_update is used to set or clear a mask i2c_field_update is used to clear out a field before the set Conflicts: common/i2c_master.c: i2c_read_offset16 not yet introduced. include/i2c.h : i2c_info_t not yet introduced. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7f8f93f4894fb9635092931a93961d328eacfeb9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956437 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> (cherry picked from commit d3129132f6e05cbce0141b5549272731bafb034f) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128751 Reviewed-by: JuHyun Kim <jkim@invensense.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: JuHyun Kim <jkim@invensense.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* motion sense: Calculate loop time based on sensor needsMathew King2021-09-255-85/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the motion sense loop bases its sleep time based on the fastest active sensor. This method has several flaws: 1. It does not take into account any task switching overhead 2. With a mix of interrupt driven and forced sensors the sleep time gets recalculated every time there is an interrupt causing the loop to oversleep 3. If multiple sensors do not have rates that are in sync the timing of the slower sensor will be off. For example if there was a sensor running at 50 Hz and one running at 20 Hz the slower sensor would end up being sampled at about 16 Hz instead of 20 Hz This change calculates an ideal read time for every forced mode sensor and calculates the sleep time based on the nearest read time. Every time a sensor is read the next read time is calculated based on the ideal read time not the actual read time so that reading does not drift because of system load or other overhead. Conflitcs: - remove code in test section added with lid angle calculation - common/motion_sense.c: use older code for processing flush. BUG=b:129159505 TEST=Ran sensor CTS tests on arcada, without this change the magnetometer was failing 50 Hz tests at about 38 Hz with 30% jitter with this change in place 50 Hz was spot on with about 10% jitter BRANCH=none Change-Id: Ia4fccb083713b490518d45e7398eb3be3b957eae Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1574786 Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 0c71c4748699f5f2cb1423ffc07d4c852d04b3fc) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128750 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: I-Fan Wang <ifanw@google.com>
* touchpad_gt7288: Basic driver for Goodix GT7288Gwendal Grignou2021-09-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | A simple driver which allows touch reports and firmware version information to be read. If the appropriate config flag is set, console commands are included for testing. Unlike the other two touchpad drivers already implemented, which simply receive I2C HID events and send them straight out again over USB HID, we want to do some processing on the touchpad data in the board directory. For that reason, this driver leaves handling the touch interrupts up to the user. Conflict: Just add UINT16_FROM_BYTE_ARRAY_LE macro. BRANCH=rammus BUG=none TEST=With https://crrev.com/c/1716928 patched, run the various host commands and check the output. Change-Id: Ia38e516473b78fb052ae18ca89acc5d815b53bd6 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799290 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128749 Reviewed-by: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* compile_time_macros: Add GENMASK and GENMASK_ULLCraig Hesling2021-09-174-0/+74
| | | | | | | | | | | | | | | | | | | | | BRANCH=all BUG=none TEST=make buildall TEST=make run-compile_time_macros Change-Id: I586e009dac20e33701ded9a05c51ee806e466cae Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1974356 Tested-by: Craig Hesling <hesling@chromium.org> Auto-Submit: Craig Hesling <hesling@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> (cherry picked from commit f776a287369e4ac46b17eb9001f3b78621f87325) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128748 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* common: Add BIT macroGwendal Grignou2021-09-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | As requested for integration in kernel mfd subsystem, use BIT(...) instead of (1 << ... ). Add the macros, apply just to ec_commands.h for now. Conflict: only add the BIT macro in compile_time_macros.h. BUG=None BRANCH=rammus TEST=Compile Change-Id: I8509f1e8dc966799c3c4f0269b15f1ccc4138c07 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518658 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128747 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* util/ecst: Make sure that copying back arguments doesn't exceed MAX_ARGSPatrick Georgi2021-09-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer gcc than we have in CrOS shows a non-helpful error message: util/ecst.c: In function 'main': util/ecst.c:398:7: error: 'strncpy' output may be truncated copying 100 bytes from a string of length 9999 [-Werror=stringop-truncation] 398 | strncpy(hdr_args[arg_ind++], | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 399 | tmp_hdr_args[tmp_ind], | ~~~~~~~~~~~~~~~~~~~~~~ 400 | ARG_SIZE); | ~~~~~~~~~ In the end it's about gcc not being able to ensure that hdr_args[] doesn't overflow. BUG=none BRANCH=none TEST=gcc 9.3 as shipped with debian sid compiles ecst without error Change-Id: I2c30cdfaac0305ea4e4c19477469bcf497469caa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2273240 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> (cherry picked from commit 3a838d11ae131526b1524a03789f11300f095c9b) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128746 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* rammus: Add accelerometer 2nd source KX022.Michael5 Chen12021-09-135-2/+116
| | | | | | | | | | | | | | | | | | Add accelerometer 2nd source KX022. BUG=b:197005105 BRANCH=rammus TEST=make BOARD=rammus Using command "watch ectool motionsense lid_angle". Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: Iea7fee7766730a8c054217877abb76facb55976a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3102685 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> (cherry picked from commit e7de2313be106dc09fdc2c67eda7c190be5fa3e4) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3156305
* Clear OWNERS for factory/firmware branchBrian Norris2021-09-102-9/+0
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155231 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* BACKPORT: mkbp: handle multiple writes of interruptJett Rink2021-09-102-74/+274
| | | | | | | | | | | | | | | | | | | | | | | | | | We need to handle the case of multiple tasks trying to set the mkbp interrupt while the host command task is trying to clear it. The setting of the interrupt may also take a while and we need to ensure that we synchronize correct after a longer delay. BRANCH=ramus BUG=b:129159505,b:139001152 TEST=passing CTS sensor run (except test 133 nullptr) with this change TEST=pass CTS sensor run on eSPI-based system TEST=pass CTS sensor run on GPIO-based system cheets_CTS_P.9.0_r9.x86.CtsSensorTestCases passes on shyvana. Conflicts: common/mkbp_event.c : do not add HECI code. Change-Id: I056b72c1210d7525c29a8555f97e6f09d773d12f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1560229 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1776839 Tested-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* BACKPORT: mkbp: non-gpio-based mkbp events, leave interruptsJett Rink2021-09-102-33/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For non-gpio-based mkbp event delivery, we do not want to temporarily disable interrupts as the code to send the mkbp events may use mutexes or task scheduling to perform the more complicated mkbp event delivery. For simple GPIO-based implementations, pausing interrupts gives the mkbp_last_event_time marker the best chance at matching the actual time the gpio was toggled on the EC. For other implementation, we are already at the mercy of bus delays and timing for delivery so it wasn't as reliable in that case to beginning with. BRANCH=none BUG=b:128862307,b:139001152 TEST=Ran AIDA64 sensor tab for a long time without seeing ISH communication issue. cheets_CTS_P.9.0_r9.x86.CtsSensorTestCases passes on Rammus. Conflicts: common/mkbp_event.c : do not add HECI code. Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1531773 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mathew King <mathewk@chromium.org> (cherry picked from commit 7c91b658c6c0c1ef9a08f2409190bbda0c2a0140) Change-Id: Id6e63a7f7b494559bd38b4659a580fa57666ecf1 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1776838
* BACKPORT: mkbp_event,include/config.h: Clarify MKBP delivery method.Yilun Lin2021-09-1017-25/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we have two MKBP delivery methods: 1. define CONFIG_MKBP_USE_HOST_EVENT to notify via host event 2. undef CONFIG_MKBP_USE_HOST_EVENT to notify via GPIO interrupt It may become more complicated if new notification methods introduced. e.g.: mt_scp uses IPI, rather than host event and GPIO interrupt. This CL does: 1. add CONFIG_MKBP_USE_GPIO to explicilty declare that MKBP event are sent via GPIO interrupt. 2. CONFIG_MKBP_USE_CUSTOM for boards which have custmized methods. 3. Remove weak attribute in mkbp_set_host_active (which can be done with CONFIG_MKBP_USE_CUSTOM now. 4. Removes mkbp_set_host_active function in board Nocturne. It only deliver MKBP events through GPIO interrupt now. BRANCH=rammus BUG=b:120808999,b:139001152 TEST=grep -rn "CONFIG_MKBP_USE_GPIO\|EC_INT_L" board/ baseboard/ and see the result is reasonable: 1. EC_INT_L must be 1-to-1 mapped to define CONFIG_MKBP_USE_GPIO in every board, except that meep, yorp, ampton which are defined in baseboard octopus. 2. undef CONFIG_MKBP_USE_GPIO in bip and casta, which use host event, but also have baseboard octopus. Conflicts: octupus boards not updated. Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1490794 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit 8b1b74c10a87c8477bc65b7be1f6943676bd56bb) Change-Id: I4af6110e4fd3c009968075c3623ef2d91cbd770b Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1776337
* mkbp: Enable the EC to report whether it has more events on mkbp_get_next_eventEnrico Granata2021-09-102-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On all platforms where there is a GPIO interrupt line between EC and AP for MKBP events, the EC will keep the interrupt pin set as long as there are events to be served, but the AP will need to re-enter its IRQ handler once per event in order to serve all the events in the FIFO. This commit adds a version 2 of EC_CMD_GET_NEXT_EVENT, such that the EC will use the most-significant bit of the event type to record the fact that the EC has more events available. This, in turn, enables the AP to keep its interrupt handler thread awake and loop until all events are served. Since it uses a new command version, this change is forward and backward compatible: - new EC, old kernel: the old kernel will use the V1 command and never see the flag - new kernel, old EC: the old EC will not accept the V2 command and never send the flag BUG=b:119570064,b:139001152 TEST=patched Linux kernel can see and use the flag on nocturne BRANCH=nocturne,rammus Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1341159 Commit-Ready: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit fd6412f0ec89fd5570279d6081ae425107b3c9ea) Change-Id: I5bae7fdc85efcd26f7bdebcd31a7f27ecf570d88 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1776336 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* Makefile: Ignore -Waddress-of-packed-member for GCCJacob Garber2021-09-081-7/+4
| | | | | | | | | | | | | | | | | | | | | | | GCC 9 enabled the -Waddress-of-packed-member warning by default, which causes the build to fail. This is already ignored for Clang, so do the same for GCC. Tidy up the organization of the flags while we're at it. Conflicts: Makefile.toolchain: Just modify COMMON_WARN. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I8796b268503c9fef2be9336ee01beaf5309024f6 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1826289 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 344f19b1c150d0a3fc5f88b45735ab5910c16783) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128745 Reviewed-by: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* ectool_keyscan: add missing null terminator to kbd_plain_xlateFabio Baltieri2021-09-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | strchr relies on the source string to be null terminated. This fixes a compiler warning when building outside of the chroot: util/ectool_keyscan.c: In function ‘cmd_keyscan’: util/ectool_keyscan.c:208:9: error: ‘strchr’ argument missing terminating nul [-Werror=stringop-overflow=] 208 | pos = strchr(kbd_plain_xlate, key); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ BUG=none TEST=build only, warning is gone BRANCH=none Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Change-Id: Iafb8249515ffa1a5f7e04a272e54a048eef9a57c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606228 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> (cherry picked from commit 06a82155ef062adaccf3c2469c59ca850f5800c7) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128744 Reviewed-by: JuHyun Kim <jkim@invensense.com> Tested-by: JuHyun Kim <jkim@invensense.com>
* util: Add explicit castsTom Hughes2021-09-0811-47/+57
| | | | | | | | | | | | | | | | | When compiling with C++, the implicit casting that is performed in C is disallowed. Add casts in preparation for C++ compatibility. BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I5c25440819428db65225c772c1c5115a735db58a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2864519 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit e0a4e5ab99a45faa196b3894ade8c375061a7ab6) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128743
* extra/util: replace deprecated sys_siglist with strsignalAdrian Ratiu2021-09-083-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with Glibc 2.32: * The deprecated arrays sys_siglist, _sys_siglist, and sys_sigabbrev are no longer available to newly linked binaries, and their declarations have been removed from <string.h>. They are exported solely as compatibility symbols to support old binaries. All programs should use strsignal instead. https://sourceware.org/pipermail/libc-announce/2020/000029.html BUG=chromium:1171287 BRANCH=none TEST=Local builds on x86_64 / eve and arm / kevin. Sent SIGINT to iteflash and verified output. Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.corp-partner.google.com> Change-Id: I8b4deaf8743c806a9610863648b345be3b35e1b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Manoj Gupta <manojgupta@chromium.org> Tested-by: Manoj Gupta <manojgupta@chromium.org> (cherry picked from commit 733952136ee500b545fbac222bb1c63a1cf0a229) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128742
* cbi: add Second Source Factory Cache (SSFC) CBI fieldMarco Chen2021-09-086-17/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSFC field will be leveraged to record what second source is used in the DUT by probing components in the factory or RMA. Firmware code should refer to this field to judge what driver should be configured for a specific component. For example, the board code can arrange what sensor driver should be set into motion_sensors array if there are multiple sources of base or lid sensor. As the definition of FW_CONFIG, it describe which "features" the firmware code should enable or disable. For example, whether lid / base sensors should be enabled or not but not care about what second source is in this DUT. BRANCH=none BUG=b:197005105 TEST= make BOARD=rammus TEST= Run command "ectool cbi set 8 0x10 4" TEST= Run command "ectool cbi get 8" Change-Id: Icb4aa00ae47ab025198e7fd5edd6aab96a4bf53e Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2344268 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org> (cherry picked from commit 0212d4a3ce01452ddaba46f076f90e9a5e90e589) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3128387 Reviewed-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Tested-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* doc: add doc for code review rotationJett Rink2021-09-082-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | We will use cros-ec-reviewers@google.com account to trigger the round-robin code reviewer assignment for CLs. If you are the R line of this CL, then you are on the initial list :) BRANCH=none BUG=b:142125160 TEST=builds Change-Id: I121a8acc984b6b99bb9c1f3638ef431822080f0a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1972607 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> (cherry picked from commit c8c2fc0f0790ad8266855f9224aefcc2a447defb) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140773 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Jora Jacobi <jora@google.com> Owners-Override: Jora Jacobi <jora@google.com>
* OWNERS: Allow anyone to approve changes.Aseda Aboagye2021-09-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | In the (near) future, the infra team plans to enforce the OWNERS file. To continue to allow anyone to approve changers, this commit simply adds the special ownerEmail '*' meaning that any user can approve that directory or files. BUG=None BRANCH=None TEST=None Change-Id: I31a9be3b973e3e95a3a696e8195bef44fe4714a9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666753 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit cf62299c34d7fbb19187acef57264c7eec9ac2a2) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140772 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Jora Jacobi <jora@google.com> Owners-Override: Jora Jacobi <jora@google.com>
* ec: Update OWNERSKirtika Ruchandani2021-09-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | Remove folks no longer on the project and add new owners. BRANCH=None BUG=None TEST=None Change-Id: I6572d9685661fc1482b7f568be78649136cc5987 Signed-off-by: Kirtika Ruchandani <kirtika@google.com> Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1630614 Commit-Ready: Kirtika Ruchandani <kirtika@chromium.org> Tested-by: Kirtika Ruchandani <kirtika@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Kirtika Ruchandani <kirtika@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit 832e76b19ddbb4eba6d6c6e71516ebdcf288f673) Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140771 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Bill Richardson <wfrichar@google.com> Commit-Queue: Jora Jacobi <jora@google.com> Owners-Override: Jora Jacobi <jora@google.com>
* chgramp: Don't ramp DTS suppliers above advertisementAseda Aboagye2021-03-191-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We shouldn't ramp above the current limit that the DTS specifies; the USB Type-C spec clearly shows what the limit is. The existing code was allowing us to ramp up to 2.4A when a SuzyQable was connected to a chromebook. This was causing issues on various devices/workstations. If a board needs more power than SuzyQable can provide, they ought to use a ServoV4 with a charger connected instead. BUG=chromium:770296,b:142033952,b:144198315,b:152000267 BRANCH=hatch,nami,octopus TEST=Build and flash kohaku, plug in SuzyQable, verify that DUT draws no more than 1500mA. TEST=Repeat above test with a ServoV4 with 60W adapter plugged in, verify DUT can pull ~60W. Change-Id: Ife9f8d99862d61cf7d18722fdd6e19331a47e301 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2053608 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Eric Herrmann <eherrmann@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2760684 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org>
* charge_ramp: Allow USB-C power to be ramped by hardwareDaisuke Nojiri2021-03-191-7/+22
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, hardware ramping (= voltage regulation) is automatically disabled for USB-C power supplier (HARGE_SUPPLIER_PD & _TYPEC). This patch allows USB-C suppliers to get voltage regulation. It prevents the input voltage of weak suppliers from drooping. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/80163913,b/120238339,b/152000267 BRANCH=none TEST=Verify Vayne get charged by PD and Type-C adapters. TEST=Verify on Vayne input current limit is set to adapters' limit. Change-Id: Ideecac911822ffca33be1755846febfcb822f734 Reviewed-on: https://chromium-review.googlesource.com/1377564 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2760683 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-171-1/+3
| | | | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> (cherry picked from commit c2c2c083fef813e3e3c70f8c13a1418717ba682d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107292
* usbc: fix storm tracker overflow issueJett Rink2019-11-261-7/+10
| | | | | | | | | | | | | | | | | | | | | | | If there is no USB-C interrupt activity for 2^31 microseconds, then there are more than ALERT_STORM_MAX_COUNT events within 2^31 microsecond (instead of ALERT_STORM_INTERVAL), then the interrupt storm would incorrectly detect a storm and disable the port due to incorrect math regarding 32-bit overflow. (Needed to remove tests for cherry-pick to branch) BRANCH=octopus and all branches with original storm detection (CL:1650484) BUG=b:144369187 TEST=unit test in CL Change-Id: I90b888ac092f81d151538d6018771fb32f8e9c39 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925668 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931289 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* rammus: Set input voltage to 9V when batt fullMichael5 Chen2019-09-201-0/+29
| | | | | | | | | | | | | | | | | | To reduce our power consumption in our lowest power state, we should reduce the charger's input voltage down to 9V when the battery is full and we are no longer charging it. This commit will trigger a PD negotiation to select a 9V source cap. BUG=b:139429471 BRANCH=firmware-rammus-11275.B TEST=Manual Power team check power consumption under S5. Change-Id: I88517255b196ca56660441270fe01143f97f4f4d Signed-off-by: Michael5 Chen <michael5_chen@pegatroncorp.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772576 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* USB PD: disable port if TCPC interrupt storm detectedJett Rink2019-08-181-2/+41
| | | | | | | | | | | | | | | | | | | | | If we get too many interrupts too fast, then we will starve the rest of the EC. Disable an overactive port for 5 seconds. BRANCH=none BUG=b:134702480,b:128701054 TEST=7-magic hub no longer watch dog resets phaser port 0, HDMI dongle plugged into port 1 still able to function while port 0 is periodically suspending Change-Id: Ic2d13ecc64990994ffc8e3fb68537aa909657745 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1650484 Tested-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693158 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb/mux: Do not connect MUX when PD disconnectedRuibin Chang2019-08-181-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When chipset power up to S5->S3 state set PD_EVENT_POWER_STATE_CHANGE, pd task set mux usb mode whether c-port is attached or not. If c-port is nothing attached at the setting moment, then mux detects nothing and goes to low power state. Plug-in type-c usb device, after debounce pass, we set mux usb mode and mux responds i2C NAK (due to in low power mode). This CL changes that do not connect MUX when PD disconnected. For example ps8751 is used for mux case. When power up(S5->S3), we should set mux none mode whether c-port is attached or not. Once type-c usb device plug-in, after cc debounce pass, we will set mux usb mode in X_DEBOUNCE_DISCONNECT state. BRANCH=None BUG=b:133196882 TEST=After console cmd reboot and reboot hard, type-c usb device plug-in on ampton and get type-c port status by "ectool usbpdmuxinfo". Change-Id: Ia538af48c450e12af1438a6aa9a6e4e426e2f616 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1609262 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693157 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org>
* USB PD: Only maintain contracts over sysjump when sinkingDiana Z2019-08-181-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, the pd_task will attempt to maintain both source and sink contracts after an unlocked sysjump or unlocked EC reset. However, the pd_task will disable Vbus to any partners it was sourcing, causing the soft reset process to lead to a hard reset and disconnection. Since the port partner will be without Vbus and unable to respond, treat the contract as terminated and the port as the default state. BUG=b:132110509 BRANCH=octopus TEST=unlocked sysjumps with a display port dongle and hoho to ensure they were treated as disconnected, unlocked sysjumps with charger to ensure it was soft reset Change-Id: Ie477f393ea828a4e880c8e8ccbe72539e8be721a Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1639212 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693156 Commit-Queue: Zhuohao Lee <zhuohao@chromium.org> Tested-by: Zhuohao Lee <zhuohao@chromium.org>
View Lorry Controller Status