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* nautilus: Move PMIC init to a deferred functionFurquan Shaikh2018-06-061-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to nautilus board file) BUG=b:77336348 BRANCH=poppy TEST=None Change-Id: Id9eec4333c6f04141e475b61e5aea7b838dcedf7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1033614 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit ec74ffb91f20f271bf28442c22c13c602cf02492) Reviewed-on: https://chromium-review.googlesource.com/1087521 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* nautilus: Enable usb device modeFurquan Shaikh2018-06-061-1/+8
| | | | | | | | | | | | | | | | | | | | | BUG=b:78649985 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: I10addb4936eab169655c1d11f115740da139a14e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1031109 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> (cherry picked from commit a26cdd08128a33a7cd39ce59d89e6e79d88e4260) Reviewed-on: https://chromium-review.googlesource.com/1087520 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* console: Do not flush the console in console_initNicolas Boichat2018-06-011-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, console_init calls cflush() twice, once before "Console is enabled" string is printed, once afterwards. The reason is that firmware_ECBootTime looks for that string, and it may get corrupted/interleaved with others if the EC is busy during initialization. The problem here is that the CONSOLE task may have higher priority than other tasks (for good reasons), but, on boot, there are other more critical tasks that need to run (e.g. RW image verification), rather than busy-looping waiting for the console to be flushed. By fixing firmware_ECBootTime to not look for the string anymore, we do not need those 2 console flush. BRANCH=poppy BUG=b:35647963 BUG=chromium:687228 CQ-DEPEND=CL:1075832 TEST=Flash staff, see that RW verification starts at 0.001037 instead of 0.028087 (=> 27 ms faster). TEST=test_that -b $BOARD $IP firmware_ECBootTime Change-Id: I794e48eb69cc647c4595fd80265adee4a434d566 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1073180 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1081767 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* rsa: Further optimization of multiplications for Cortex-M0Nicolas Boichat2018-06-014-9/+60
| | | | | | | | | | | | | | | | | | | | | In RSA, we often need to actually compute (a*b)+c+d: provide some assembly optimized functions for that. With -O3, 3072-bit exponent, lower verification time from 104 ms to 88 ms on STM32F072 @48Mhz. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=make BOARD=hammer test-utils test-rsa3, test on board Change-Id: I80e8a7258d091e4f6adea11797729ac657dfd85d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071411 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080584
* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-06-017-7/+107
| | | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080583
* console_channel.inc: Add more ifdef to reduce number of channelsNicolas Boichat2018-06-014-6/+17
| | | | | | | | | | | | | | | | | | | There are still more ifdef than can be added: this just takes out the low hanging fruits. BRANCH=poppy BUG=b:35647963 TEST=make buildall -j, see that we gain from 0 to 64 bytes on many boards. Conflicts: board/nocturne/board.c => Does not exist on FW branch Change-Id: Ibe85b8bfa5d5c22c160e4a6656104256067beee9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070948 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080582
* console_output: Clarify help text for CONFIG_CONSOLE_CHANNELNicolas Boichat2018-06-011-2/+5
| | | | | | | | | | | | BRANCH=poppy BUG=b:35647963 TEST=N/A Change-Id: I85dd6553cf3ebace4e19813a308d0a024eba2915 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071412 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080581
* hammer: Remove unnecessary console commandsNicolas Boichat2018-06-011-0/+11
| | | | | | | | | | | | | | | | Saving space in RW, even if we are not critical in terms of size, always helps to reduce verification time. BRANCH=poppy BUG=b:35647963 TEST=make newsize => Hammer shrinks by ~3k, verification time down by ~12 ms. Change-Id: I63741106fdc56c410871fb367c29605bf37f1b77 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070951 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080580
* timer: Allow disabling gettime console commandNicolas Boichat2018-06-012-0/+3
| | | | | | | | | | | | | | hammer does not need that command, let's just remove it. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, saves 112 bytes of flash Change-Id: I24ed979f8a9053128d4eb56fc5af00429f7ba0ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070950 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080579
* console_output: Add option to disable console channelsNicolas Boichat2018-06-012-0/+19
| | | | | | | | | | | | | | | On hammer, we do not need the console channels, so we can just disable them to save flash size. BRANCH=poppy BUG=b:35647963 TEST=make newsizes, staff image size shrinks by 704 bytes Change-Id: I7a493ae57573814b166d45e57f1ad3d885f26086 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070949 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080578
* hammer: Increase PDU size to 4kNicolas Boichat2018-06-012-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Saves another ~1300 bytes of flash size, as the touchpad hashes can now be computed in blocks of 4K, instead of 1K. This costs 3K of SRAM, which we would not otherwise need on hammer. wand can only fit 2k PDU, so let's stick to that. Also, make sure that util/gen_touchpad_fw is regenerated when the configuration option changes (touchpad FW size, PDU size). Sadly, this will still break bisection from commit after this CL, to before this CL. BRANCH=poppy BUG=b:80167548 TEST=make buildall -j TEST=make BOARD=hammer/staff/wand/whiskers all tests -j TEST=Copy new staff image with old touchpad FW to DUT, verify that FW can be updated. Change-Id: Ic1763684da730dc986bbbcb3312088c8208c84b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070953 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080577
* test/build.mk: Allow boards to specify test listsNicolas Boichat2018-06-019-18/+26
| | | | | | | | | | | | | | | | | | Some tests cannot be built on some boards (not enough SRAM, unusual configuration, etc.). Instead of the long list of exceptions in test/build.mk that we currently use, allow each board (or chip) build.mk to set test-list-y, and only use the default list if it is unset. BRANCH=poppy BUG=b:80167548 TEST=make buildalltests -j Change-Id: I803c691f419451aad4396529302a4805cbe3f9b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1074572 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080576
* touchpad_elan: Reload watchdog when programmingNicolas Boichat2018-06-011-0/+2
| | | | | | | | | | | | | | | | | | | When using larger block sizes (e.g. 4096 bytes), the write operations take too long, which often causes a watchdog reset. Fix this by reloading the watchdog after programming every 64 bytes page. BRANCH=poppy BUG=b:80167548 TEST=Copy old touchpad FW to soraka, build staff, make sure FW can be updated. Change-Id: Ic6e7a3e3ef63877a4f2d5011e1fb0d49c04177a6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1070952 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1080575
* nautilus: fix battery communication errorYB.Ha2018-05-091-1/+10
| | | | | | | | | | | | | | Interrupt is generated in battery on every stop condition. So bus free time of battery must be over 5ms after every stop condition. BUG=b:73147310 TEST=Build & flash EC then check if charging is stopped. Change-Id: Ic940f2af1ec11079d3ffe97aa56224d2621723f9 Signed-off-by: YB.Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/1050166 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org>
* hammer: Disable side-band wake using detection pinNicolas Boichat2018-05-071-24/+0
| | | | | | | | | | | | | | | | | | | Side-band wake was only useful when the lid would go in deep-S3, where the USB interface is disabled. Since we are using S0ix on poppy and derivatives, the side band wake is useless, and, in some rare case, may actually cause issues. BRANCH=poppy BUG=b:77828249 TEST=Flash staff, can wake soraka from suspend, or from USB autosuspend. Change-Id: I23398a792157b32a5d79505dcffc92aaffd4fec2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1011523 Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit bbdff9dbb8e9f37ab444f72c48b70fa76a5e18bf) Reviewed-on: https://chromium-review.googlesource.com/1023535
* usb_pd_protocol: Add PD_ROLE_DISCONNECTED for data role swapsDuncan Laurie2018-05-012-2/+8
| | | | | | | | | | | | | | | | | | | | | Add a state to indicate that a data role is actually disconnected and notify the board-level data swap function with this state when a cable is unplugged. This allows the board to clean up and restore any state that may have been set up with a data role swap. BUG=b:78308749 BRANCH=eve,poppy TEST=manual on eve: plug in C-to-C cable, execute data swap on port 0 with 'pd 0 swap data' and ensure the OTG pins are asserted. Then unplug the cable and ensure OTG pins are now deasserted. Change-Id: I7d8fff22dd5836b4b5af54f0ede71ee1b6e40b5c Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/1036904 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* poppy: Enable usb device modeFurquan Shaikh2018-04-263-3/+9
| | | | | | | | | | | | | | | | | | | | | | BUG=b:78577893 BRANCH=poppy TEST=Verified following: 1. ectool usbpd 0 dr_swap 2. ectool usbpd 0 --> Role: SNK UFP Change-Id: Ie1130eba3da4352e2a3e09eaad20886a1bea81a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029539 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 664339e6f20ddedb4e3dc88715b586cc31616e85) Reviewed-on: https://chromium-review.googlesource.com/1031111 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* nautilus: Lower maximal ODR to 100 Hz and disable sensor EC logYounghun Kim2018-04-261-0/+10
| | | | | | | | | | | | | | | | | | | When ARC++ request Accel/Gyro to maximum rate(200Hz) at same time, accel sensor is stopped or fastest_batching test is failed 1) EC Maximum ODR from 200 Hz -> 100 Hz 2) Disable EC sensor log BUG=b:75498983,b:78220297,b:78458301 TEST=Build EC then run cts CtsHardwareTestCases run cts-verifier sensor test Change-Id: I9a41e04853e10bae58b6d1fc57307b550901630d Signed-off-by: Younghun Kim <young-h.kim@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/1023497 Reviewed-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Gwendal Grignou <gwendal@google.com>
* poppy: Move PMIC init to a deferred functionNicolas Boichat2018-04-261-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to poppy board file) BUG=b:77336348 BRANCH=poppy TEST=while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done for 24 hours Change-Id: Ie7ce08f5c4d6ee7052f2c1b36b53099c9e208074 Original-Change-Id: Icd9c2096ca026da6308b74582144886b30ea965f Original-Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/1003436 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029254 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: Touch watchdog during initDuncan Laurie2018-04-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Touch the watchdog during init to prevent it from firing prematurely during HOOK_INIT processing before the tasks are started and watchdog_reload() will be called with HOOK_TICK. BUG=b:77336348 BRANCH=eve,poppy,fizz,reef,kevin TEST=run stress test for several days: while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done Change-Id: Ic468efd0fbc4b2a8681d4eabcd2fddcf79f7d13c Original-Change-Id: I79e744a4678ab1808870d0e7647d2ce273ddeb8f Original-Signed-off-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1001532 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029253 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: watchdog: disable ITIM16 before updating ITCNT registerMulin Chao2018-04-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | During watchdog initialization, the driver doesn't disable ITIM16 module which used for detecting watchdog timeout before updating new preload value. Although the ITEN bit on reset is zero, it caused preload value is not updated to module successfully since ITEN won't be reset (ITIM16 is still enabled) in sysjump case. Despite WDCNT will be reloaded by touching watchdog in HOOK_TICK hook function later, it's better to disable any ITIM16 module before updating ITCNT register. BRANCH=none BUG=b:77336821 TEST=No build errors for npcx5 series. Change-Id: I6444dfdece0e9f286be64b7ccbfa6e80deff28a8 Original-Change-Id: I19baa47bca347b9dca2fc1dcaacca81519facf21 Original-Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Original-Reviewed-on: https://chromium-review.googlesource.com/999458 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029252 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/npcx: Ensure software watchdog has highest priorityNicolas Boichat2018-04-2611-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change uart_ec_interrupt and software watchdog interrupt handler both had priority 0. Since UART IRQ number is 33, and software watchdog is 44, the UART interrupt handler would have higher prority. Fix this by increasing all interrupt handler priorities, leaving the software watchdog handler alone on priority 0. BRANCH=eve,poppy,fizz BUG=b:76391320 TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt handler), check that panicinfo contains a sensible PC in r5 after reset. Change-Id: I8275e0a4c1a5307139fb6be0387eb5787b1209d4 Original-Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e Original-Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/979738 Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029251 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* host_event_commands: Fix lpc_get_next_host_event for 64-bit eventsNicolas Boichat2018-04-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | __builtin_ffs takes an int as argument, and, therefore, does not find bits >= 32. Fix this up when CONFIG_HOST_EVENT64. BUG=b:69329196 BRANCH=fizz,poppy TEST=Patch coreboot to add bit 33 in SCI mask, add EC code to send such events, EC does not watchdog anymore Change-Id: I91a4366c7b0e565fc523246d0abb684ffa50d483 Original-Change-Id: If868095f19fe1940b4f5924cf669a719f9535991 Original-Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/989514 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029250 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: lpc: fixed bug that ec gets stuck in lpc_sib_wait_hostxx routines.Mulin Chao2018-04-263-4/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done() and lpc_sib_wait_host_write_done() routines, in rare case, ec might have a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD bits are high forever. (Normally, CSWR/CSRD bits won't be always high. These bits are high forever also means something wrong on LPC/eSPI bus.) In order to prevent this situation, the CL checks TO_STS bit of ITCTS in these routines. If this bit is set, restoring ITIM32 preload counter value to maximum value and processing overflow will be done by force_time(). BRANCH=eve,fizz,poppy BUG=b:76182199 TEST=No build errors for npcx series. Passed test command of CL 979389 on npcx_evb. No symptom occurred during warm reset stress test on soraka. Change-Id: I04dbe44115599cec79ed240ce4b78c122d9c8631 Original-Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6 Original-Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Original-Reviewed-on: https://chromium-review.googlesource.com/979874 Original-Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1029229 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* poppy: Prevent base detection from falling into reverse detection trapNicolas Boichat2018-04-231-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem here is that both normal detection range (120-300mV) and reverse connection detection range (450-500mV) are on the same side of the interrupt pin TTL level. So if we accidentally sample the ADC at the wrong time (either on connection, or after a side-band wake signal from base), we may fall into a trap where we assume that the base is connected in reverse, while the value may just be a transient. We have seen this case in the field, due to side-band wake pulse from base EC, but this could potentially happen on attach as well. The code debounces the reverse detection signal a little longer (this has no impact as the base is not functional anyway), so that we only consider that the base is connected in reverse if the ADC value is within the range twice in a row. BRANCH=poppy BUG=b:77828249 TEST=With HACK CL to emulate bug: - Press a few keys, hammer gets disconnected - Connect/disconnect hammer a few times, sometimes it does not get disconnected. TEST=Base connection, normal and reverse, still works properly. Change-Id: I2ccb911472dd591146e3b0e68400c8bd55368dba Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1010044 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit cdc9d417612275cdcc3b62f47c0a2cc6155b8c41) Reviewed-on: https://chromium-review.googlesource.com/1013757 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* hammer: Lock RO image whenever write protect screw is onNicolas Boichat2018-04-171-4/+2
| | | | | | | | | | | | | | To be committed only exactly as the same time as we switch the key to MP. CQ-DEPEND=CL:*609303 BRANCH=poppy only (no master) BUG=b:68232822 TEST=Flash staff, flashinfo: RO/RW regions are both locked Change-Id: I5050524e7b27b523416e7deecdf7fc48276e2d5f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1006558
* Revert "i2c: expose port num during unwedge console output."Furquan Shaikh2018-04-111-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 47c0dde1b5e97906b8b4436d45924cce5a814760. Reason for revert: Note from Nicolas "This increases stack size usage and should _not_ have been backported to a stable branch." Original change's description: > i2c: expose port num during unwedge console output. > > Signed-off-by: Todd Broch <tbroch@chromium.org> > > BUG=b:72837836 > TEST=manual, > on Nami, 'echo mem > /sys/power/state' > > From EC console see, > [4823.162371 I2C4 unwedge failed, SCL is held low > > Change-Id: Ic66c7fe00442fdcef90b3a0e4c10bcddc73e04c6 > Reviewed-on: https://chromium-review.googlesource.com/981450 > Commit-Ready: Todd Broch <tbroch@chromium.org> > Tested-by: Todd Broch <tbroch@chromium.org> > Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> > Reviewed-by: Todd Broch <tbroch@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/982350 > Reviewed-by: Furquan Shaikh <furquan@chromium.org> > Commit-Queue: Furquan Shaikh <furquan@chromium.org> > Tested-by: Furquan Shaikh <furquan@chromium.org> > Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Bug: b:72837836 Change-Id: I08cacf8291daf4738a284f325e1300e74a7a006b Reviewed-on: https://chromium-review.googlesource.com/1006316 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nautilus: Shrink accelerometer FIFO to 512 entriesNicolas Boichat2018-04-111-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that the shared memory buffer on Nautilus starts at 200c7720 D __shared_mem_buf That's 29.78 kb into the RAM. Software sync needs 1kb, so we should be fine, expect that the last 2kb of RAM are supposed to be reserved for the "booter" (NPCX_BTRAM_SIZE). We shrink the accelerometer FIFO to 512 entries, freeing up 4kb of RAM, and increase the UART TX buffer to 4kb, to make use of 3kb of that freed up space: 200c7320 D __shared_mem_buf That's 28.78 kb into the RAM. BRANCH=poppy BUG=chromium:739771 TEST=make BOARD=nautilus -j, check that shared_mem_buf offset is < 29 kb. Change-Id: I361a439b847d31d3415f2ee66229bd32f8816e2d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1002712 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 3a9b89116fd0b3e358706f9c5822d4ee944978b6) Reviewed-on: https://chromium-review.googlesource.com/1006315 Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* nautilus: Support tristate board id strapping pinPhilip Chen2018-04-092-0/+29
| | | | | | | | | | | | | | | | | | | | With 3 binary strapping pins, we only have 7 available board ids: 000, 001, 010, 011, 100, 101, 110, 111. Let's make the MSB of board id tristate. So we can have 4 more board ids to use: Z00, Z01, Z10, Z11. BUG=b:77731277 BRANCH=poppy TEST=build nautilus Change-Id: I7aebb89437d2ccb9eea6c477155b25d964983232 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1001493 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* FIXUP: board: Add CONFIG_ACCEL_FORCE_MODE_MASK for ALS when neededGwendal Grignou2018-04-081-1/+1
| | | | | | | | | | | | | | | | Enabled forced mode for BMI160 accelerometer on soraka by mistake. BUG=b:67112751,b:75533383 BRANCH=poppy TEST=Compile Change-Id: I429a1d527a56c371351f8248912c580f8680447f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1000726 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> (cherry picked from commit 7f5299cb7a588d660c8064fd7f3a4855e5706df9) Reviewed-on: https://chromium-review.googlesource.com/1001713
* nautilus: Lower VCCIO from 0.975V to 0.850VFurquan Shaikh2018-04-051-4/+4
| | | | | | | | | | | | | | | | | | | CQ-DEPEND=CL:*602409 BUG=b:77496214 BRANCH=poppy TEST=None Change-Id: If04161615343f573d0de0881667564f7384c2605 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/996804 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bf954bedfc1bb11aee020eeb1729bbc187cb293) Reviewed-on: https://chromium-review.googlesource.com/996733 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* i2c: Use the correct config variable for i2c board callbackFurquan Shaikh2018-04-041-2/+2
| | | | | | | | | | | | | | | | Fix typo in i2c_master.c to use CONFIG_I2C_XFER_BOARD_CALLBACK instead of CONFIG_I2C_XFER_CALLBACK. BUG=b:73147310 BRANCH=None TEST=None Change-Id: I4a8179df48940e6d4347f9d76908a0fc4d3ea692 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/996252 Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* driver/touchpad_st.c: implement touchpad fw updateWei-Han Chen2018-03-271-1/+232
| | | | | | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=make BOARD=whiskers TEST=sudo ./extra/usb_updater/usb_updater2 -d 18d1:5030 -p <file> Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I6e3e73a01571ae4cf31891edca588c44e5f41194 Reviewed-on: https://chromium-review.googlesource.com/958896 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982351 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* i2c: expose port num during unwedge console output.Todd Broch2018-03-271-4/+5
| | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:72837836 TEST=manual, on Nami, 'echo mem > /sys/power/state' From EC console see, [4823.162371 I2C4 unwedge failed, SCL is held low Change-Id: Ic66c7fe00442fdcef90b3a0e4c10bcddc73e04c6 Reviewed-on: https://chromium-review.googlesource.com/981450 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982350 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* whiskers: enable ST touchpadWei-Han Chen2018-03-272-11/+61
| | | | | | | | | | | | | | | | | | BRANCH=whiskers BUG=none TEST=make BOARD=whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I8a5ef6796a60706da539dd80fb03a379f1aa8d38 Reviewed-on: https://chromium-review.googlesource.com/958895 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982349 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* ec: add driver/touchpad_st.cWei-Han Chen2018-03-274-5/+732
| | | | | | | | | | | | | | | | | | | | | | | Initial commit for ST touchpad. This CL will support X/Y mode function. BRANCH=none BUG=none TEST=make BOARD=whiskers TEST=manually test touchpad function on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: I1669286ca764fbbd4a691171193415dd4999673f Reviewed-on: https://chromium-review.googlesource.com/958894 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982348 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* lpc: remove lpc_host_resetJett Rink2018-03-274-64/+0
| | | | | | | | | | | | | | | | | | | | | | No one is using this method and it implies that all chipset should support the RCIN# Virtual Wire if using eSPI. Only large core chips use RCIN#; small core chips don't. This method was introduced for skylake and has since been replaced since CL:575947 was merged. BRANCH=none BUG=none TEST=build all Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/975904 Reviewed-on: https://chromium-review.googlesource.com/982347 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Remove the unnecessary words of "Disable touchpad" in the commentsKaiyen Chang2018-03-274-4/+8
| | | | | | | | | | | | | | | | | | | | The control of trackpad from EC was entirely removed by CL:421275. So remove the unnecessary words of disabling touchpad in the comment of lid_angle_peripheral_enable(). BUG=none BRANCH=poppy TEST=none Change-Id: Ie688d9dc98c5f6f60a9d3908945495f4b6fdb00d Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/979572 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982346 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Nami: initial x,y,z-axis direction of lid and base g-sensorElmo_Lan2018-03-271-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Modify standard reference frame to fit Nami shell design. (base_standard_ref and lid_standard_ref) BUG=b:76392750 BRANCH=none TEST=Use "watch -n 1 ectool motionsense" to check x,y,z-axis. 1. When x-axis face up, get x value of sensor0 and sensor1 more than 10000. 2. When y-axis face up, get y value of sensor0 and sensor1 more than 10000. 3. When z-axis face up, get z value of sensor0 and sensor1 more than 10000. Change-Id: I8df24f6a48d2759938d17f8ec92b7b4536d71aaa Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/980012 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/981712 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* sensor: bmi160/bma2x2: Fix the timeout value of compensation.Marco Chen2018-03-272-2/+2
| | | | | | | | | | | | | | | | | | | | | | | CL:957872 introduced "get_time().val + 400" as the deadline to perform compensation and the comment in bma2x2.c mentioned the deadline should be 400ms. But the unit of val in timestamp_t is microsecond not milisecond so only 400us is defined not 400ms. BRANCH=none BUG=none TEST=test manually on the dut by performing calibrate. Change-Id: I7a834ef6dcb0772569d2c8d6c507803deb5d2fc1 Signed-off-by: Marco Chen <marcochen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/979512 Commit-Ready: Gwendal Grignou <gwendal@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/981713 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* yorp: update virtual wire note for PLT_RST_LJett Rink2018-03-271-1/+2
| | | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I8d1a810a171685f98c6fe476234ec2e29e7c5854 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978369 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982345 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* bip: enable CONFIG_IT83XX_FLASH_CLOCK_48MHZ to support eSPI speed of 50MhzJett Rink2018-03-271-0/+3
| | | | | | | | | | | | | | | | | | | | The FND clock must be greater than half the eSPI clock. Enabling this option bumps the FND clock from 24Mhz to 48Mhz. BRANCH=none BUG=none TEST=none Change-Id: Ifbd82a5049c2cc88700100fda2b7cc0930425b91 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978933 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/982344 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* bip: add UART interrupt to exit deep doze modeJett Rink2018-03-272-3/+5
| | | | | | | | | | | | | | | | | Hook up UART RX pin to wake up ITE device when in deep doze mode. BRANCH=none BUG=none TEST=none Change-Id: Iabfd3ef51f9e63a6cbcca60fb916108528b0b294 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978932 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982343 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* bip: remove GPIO_HIB_WAKE_HIGH option GPIOJett Rink2018-03-271-2/+1
| | | | | | | | | | | | | | | | | | | | GPIO_HIB_WAKE_HIGH is not needed or honored by ITE EC controller. The lower power state on the ITE still honors the GPIO_INT_BOTH option. BRANCH=none BUG=none TEST=none Change-Id: I9aba6713c6e4773dd9473705ae020be9d4bac74c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978871 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/982342 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* stoney: Rename PGOOD GPIOsEdward Hill2018-03-279-28/+28
| | | | | | | | | | | | | | | | | | | | Rename stoney power signals for clarity: SPOK -> S5_PGOOD VGATE -> S0_PGOOD BUG=none BRANCH=none TEST=power grunt on and off Change-Id: Iee8307138600c10868981a22971beace2de1ca91 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978952 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982341 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-277-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=none BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982340 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* keyboard: Add config option for refresh key rowDuncan Laurie2018-03-273-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The keyboards that have an assistant key also move the row that the refresh key is on from 2 to 3. The row is hardcoded and used by the early boot key detection code to determine if boot keys should be honored. The fallout from not having the right refresh row defined was not seen on Eve because that board has a different quirk where it does not distinguish reset-pin vs power-on reset types so the test in check_boot_keys() was not failing. BUG=none BRANCH=none TEST=manual testing on Eve board Change-Id: I5b94b4e32024afa1768bdf371a7eb951753014e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979574 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982339 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* intel_x86: Move chipset reset logic to common codeVijay Hiremath2018-03-274-50/+31
| | | | | | | | | | | | | | | | | | | | | | Chipset reset logic chipset_reset() is same for APL, GLK, SKL, KBL and CNL hence move it to common code. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974471 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982338 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* apollolake: Remove AP cold reset logicVijay Hiremath2018-03-271-29/+8
| | | | | | | | | | | | | | | | | | | | | | | | | In APL & GLK, cold reset code does a AP force shutdown (with board specific AP shutdown code) by power sequencing the SOC all the way to S5 and bring it back to S0. However there is no separate GPIO in APL & GLK for doing AP cold reset hence removed the AP cold reset logic. BUG=none BRANCH=none TEST=make buildall -j Manually verified on GLKRVP, apreset cold & warm behave same Change-Id: I6ee5e4c4df94e685acdabe31b8b5554295883792 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974107 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982337 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
* yorp: Switch on blue LED on boot-upFurquan Shaikh2018-03-273-0/+28
| | | | | | | | | | | | | | | | | | | | | This is helpful during early debugging to identify if the EC is up and running. This will be later cleaned up as part of LED support for yorp. BUG=none BRANCH=None TEST=Verified that blue led glows up on booting up EC. Change-Id: I4670c210045c649a926e7c3f23c5d6097df69e3d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/979270 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982336 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Trybot-Ready: Furquan Shaikh <furquan@chromium.org>
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