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* CBI: Make cbi command dump EEPROM contentsfirmware-kbl-10431.BDaisuke Nojiri2018-02-221-16/+21
| | | | | | | | | | | | | | | | | | | | | | | Currently, cbi console command dumps the buffered contents. This patch will make the command dump the entire EEPROM. BUG=b:70294260 BRANCH=none TEST=Run cbi command on Fizz: CBI_VERSION: 0x0000 TOTAL_SIZE: 18 BOARD_VERSION: 514 (0x202) OEM_ID: 2 (0x2) SKU_ID: 0 (0x0) 43 42 49 5c 00 00 12 00 00 02 02 02 02 01 00 01 01 02 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ... Change-Id: I39f3335a38eb72c95d53264ddc7386dd0910e946 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/930322 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: use single __packed definitionVadim Bendebury2018-02-225-6/+6
| | | | | | | | | | | | | | | | | | | Various parts of Cr50 code and Cr50 related utilities duplicate definition of __packed available in include/common.h. Let's use the same definition everywhere. BRANCH=cr50, cr50-mp BUG=none TEST=make buildall succeeds verified that linker generated map files for Cr50 RW are the same before and after this change. built and used gsctoo and rma_reset Change-Id: Ib91f9bbad1f6822b347f32b393630f592df80d60 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/931929 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: fix Board ID retrieval functionVadim Bendebury2018-02-211-8/+6
| | | | | | | | | | | | | | | | | | The function used to read or write Board ID value, when invoked for reading, reports the value on the console, but does not save the read value in the passed in structure. Let's always save it in the structure so that the caller of this function has access to the retrieved value. BRANCH=none BUG=chromium:812880 TEST=verified that 'gsctool -i' still operates as expected. Change-Id: I9bc713386758ca6701e6b853e042652e2f392871 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/925692 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gsctool: allow multiple source filesVadim Bendebury2018-02-212-3/+14
| | | | | | | | | | | | | | | | | | | | | | | With the upcoming extensions it would be beneficial to be able to keep gsctool functionality spread among multiple source files. The current Makefile is also not generating proper dependencies, which was fine when gsctool utility was first introduced, but is not adequate any more, and would be even more noticeable when more source files are added. In preparation let's just convert the build scheme into separately compiling .c files, generating .d files while at it, and then linking the .o files together in a separate link operation. BRANCH=none BUG=chromium:812880 TEST=verified that gsctool still builds fine and allows to update Cr50 image. Change-Id: I537bbe6bf76ac71e8d30040b276b78513d390bbf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/923418 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: fix AXI memory corruption on STM32H743Vincent Palatin2018-02-212-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15 'Reading from AXI SRAM might lead to data read corruption': """ Read data might be corrupted when the following conditions are met: - Several read transactions are performed to the AXI SRAM, - and a master delays its data acceptance while a new transfer is requested. """ We can actually hit this under a fair interrupt load and two tasks running (e.g polling with the AP with host commands while doing fingerprint image acquisitions). So apply the proposed workaround and limit concurrent read access on AXI master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD register. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor', poll in a tight loop with 'ectool fpmode'. No longer see random panics. Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576 Reviewed-on: https://chromium-review.googlesource.com/926009 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pd: retry DR_SWAP after a WAITVincent Palatin2018-02-211-1/+4
| | | | | | | | | | | | | | | | | | | | | If the other side answers our DR_SWAP request with a WAIT message (as bizarre as it might be), we want to retry later rather than giving up. Set again the PD_FLAGS_CHECK_DR_ROLE flag in order to do so. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=fizz BUG=chromium:814098 TEST=do repeated cold reset on Fizz connected to the 'interesting' USB-C screen and see the DP alternate mode negotiated. Change-Id: Icfb9fa209ce8cbe3c42c1e6946b43464544bdaea Reviewed-on: https://chromium-review.googlesource.com/921141 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* cr50: Allow spihash extension command over USBVadim Bendebury2018-02-201-0/+1
| | | | | | | | | | | | | | | Execution of this command requires physical presence on the DUT, this is why it is save to allow it over USB. BRANCH=cr50, cr50-mp BUG=chromium:812880 TEST=using modified gsctool verified that the command goes through and physical presence indication is requested Change-Id: I0aa371d8aaa5a480cc12d5d16edad8497142f4b4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/927796 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: Set ESPI_MAXFREQ based on FMCLK valueFurquan Shaikh2018-02-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should be decided based on the value of FMCLK. Since we are setting FMCLK to 30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz. This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK. BUG=b:73504527 BRANCH=fizz? TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran some reboot tests to ensure that there is no regression in boot time. Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/925843 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* poppy/soraka: Enable VR decay for runtime and suspend S0ixFurquan Shaikh2018-02-201-48/+1
| | | | | | | | | | | | | | | | We have been using upstart script to force VR decay in runtime S0ix for a while now and haven't seen any issues. This change pushes the fix in EC so that we don't need the upstart script hack any more. BUG=b:70881268 BRANCH=None TEST=Verified by reverting upstart script that PMIC registers are programmed as required to enable VR decay in S0 and S0ix. Change-Id: I19729e907d2ae065758e69933d0b1d3e5b43d5e0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/856856 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: remove set capabilities from powerbtnMary Ruthven2018-02-203-68/+2
| | | | | | | | | | | | | | | | | | | | Cr50 cannot override the state of the power button. It was possible with dev cr50 chips, but the capability was removed in prod chips. Change the console command, so it is only used to get the state of the power button. Remove all of the commands used to override the power button. BUG=b:73557298 BRANCH=none TEST=none Change-Id: I99cb5e8a18dd972fba460c434364702f06a26305 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/926964 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* CBI: Update cbi-util printing formatDaisuke Nojiri2018-02-201-14/+41
| | | | | | | | | | | | | | | | | | | | | | | This patch makes cbi-util print the tag and the size of each field. It also fixes help message and adds indendation for readability. BUG=b:70294260 BRANCH=none TEST=Run the command as follows: $ cbi-util --show /tmp/cbi.bin CBI blob: /tmp/cbi2.bin TOTAL_SIZE: 18 CBI_VERSION: 0 Data Field: name: value (hex, tag, size) BOARD_VERSION: 514 (0x202, 0, 2) OEM_ID: 2 (0x2, 1, 1) SKU_ID: 3 (0x3, 2, 1) Data validated successfully Change-Id: I5f0fde4690c29c0ee58c798e8cc35bac3ed1b6f8 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/926781 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Nami: Read board info from EEPROMraymondchou2018-02-172-8/+10
| | | | | | | | | | | | | | | | | Eanble CONFIG_CROS_BOARD_INFO to read board info from EEPROM. 1. Change the EEPROM address to 0xa0. BUG=none BRANCH=none TEST=Read data from EEPROM. Change-Id: I81fbada6dd64627cc438d6ed405b696e442c3a83 Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/880525 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* meowth_fp: more reliable flashing sequenceVincent Palatin2018-02-171-4/+6
| | | | | | | | | | | | | | | | | | | | Release the reset of the FP MCU later after loading the proper spidev kernel module else the STM DFU bootloader is confused by the SPI state and fails half of the time. Also update the SPI device for the current board configuration. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36125319 TEST=On Meowth, run a lot of 'flash_fp_mcu ec.bin' Change-Id: I634fbc91fc5da52b07c48696594661f88338d986 Reviewed-on: https://chromium-review.googlesource.com/924284 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cr50: fix DEBUG_DRIVE commentBrian Norris2018-02-161-1/+1
| | | | | | | | | | | | | | This is the DEBUG_DRIVE register, not the DEBUG_BLOCK_OUTPUT. Copy/paste error? BRANCH=none BUG=none TEST=none Change-Id: Ic915b8675559d6f43d153f3a309becc621416dbe Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924698 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* host_command: Count suppressed host commands individuallyDaisuke Nojiri2018-02-165-23/+63
| | | | | | | | | | | BUG=chromium:803955 BRANCH=none TEST=Verify counters are printed every hour and before sysjump as follows: [12.540051 HC Suppressed: 0x97=25 0x98=0 0x115=0] Change-Id: I1c1aecf316d233f967f1d2f6ee6c9c16cc59bece Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912150
* CBI: Update cbi-util to support variable data offset & sizeDaisuke Nojiri2018-02-161-23/+72
| | | | | | | | | | | | | | | | | | | | | | | This patch makes cbi-util support variable data offset & size. BUG=b:70294260 BRANCH=none TEST=Run the command as follows: $ cbi-util --create /tmp/cbi.bin \ --board_version 0x202 --oem_id 2 --sku_id 3 --size 256 $ cbi-util --show /tmp/cbi.bin CBI blob: /tmp/cbi2.bin TOTAL_SIZE: 18 CBI_VERSION: 0 BOARD_VERSION: 514 (0x202) OEM_ID: 1 (0x1) SKU_ID: 2 (0x2) Data validated successfully Change-Id: Id290c33e8625223c8f3fa34fdf8a13ea9308c42e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/922272 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CBI: Make data offset and size variableDaisuke Nojiri2018-02-165-156/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently CBI data offset and size are fixed. This patch makes them variable. Each data item consists of <tag><size><value> where <tag> is a numeric value assigned to each data item, <size> is the number of bytes used for <value>. BUG=b:70294260 BRANCH=none TEST=Use 'ectool cbi set' to set board version, oem, sku. Verify the contents by cbi console command and ectool cbi get. 1. ectool cbi set 0 0x202 2 2 (Init CBI and write board ver. of size 2) 2. ectool cbi set 1 1 1 (write oem id of size 1) 3. ectool cbi set 2 2 1 (write sku id of size 1) 4. ectool cbi get 0 514 (0x202) 5. ectool cbi get 1 1 (0x1) 6. ectool cbi get 2 2 (0x2) 7. Run cbi console command: CBI_VERSION: 0x0000 TOTAL_SIZE: 18 BOARD_VERSION: 514 (0x202) OEM_ID: 1 (0x1) SKU_ID: 2 (0x2) 43 42 49 8c 00 00 12 00 00 02 02 02 01 01 01 02 01 02 Change-Id: I5a30a4076e3eb448f4808d2af8ec4ef4c016ae5e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/920905 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* meowth_fp: update pins configurationVincent Palatin2018-02-162-2/+15
| | | | | | | | | | | | | | | | | Disable the system lock (ie ignore Write-protect) until we have fully defined our secure update scheme. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:73337313 TEST=On Meowth, run 'ectool --name=cros_fp gpioget WP' Change-Id: I3323f5d1e48debae9e2ca6e18f4439e2849a3683 Reviewed-on: https://chromium-review.googlesource.com/924125 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* fpsensor: add quality test capture typeVincent Palatin2018-02-163-18/+29
| | | | | | | | | | | | | | | | | | | Add support for an additional finger image capture type used for quality testing. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575, b:71770455 TEST=On Meowth, run 'ectool --name=cros_fp fpmode capture qual' then 'ectool --name=cros_fp fpframe raw > finger_mq.bin' Change-Id: I1b9525dc2adf0b91aef2f7124803c90d6a3bb0ca Reviewed-on: https://chromium-review.googlesource.com/924124 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* grunt: Add power/battery LED supportSimon Glass2018-02-164-173/+58
| | | | | | | | | | | | | | | | | | | | | | | | Replace the current led code with an implementation that uses the new led_pwm interface. Grunt has a blue LED which we use for power and an amber LED which we use for battery. The colours used are documented in update_leds() in led_pwm.c BUG=b:71902053 BRANCH=none TEST=manual Check for the various states: * Solid Amber == Charging * Solid Blue == Charging (near full) * Fast Flash Amber == Charging error or battery not present Did not test low / critical battery Change-Id: Ie46075855ab17e6e7301025b62e57db2c596b2a4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919765 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* grunt: Add pull-up to EC_BATT_PRES_ODL GPIOEdward Hill2018-02-161-1/+1
| | | | | | | | | | | | | | | | The EC_BATT_PRES_ODL is an open drain signal. The SN74LVC1G07 IC which drives that signal is an open drain buffer. There is no external pull. Therefore, an internal pullup is required. BRANCH=none BUG=b:73286869 TEST=gpioget shows 0 with battery and 1 without Change-Id: I98e18f54b62ddd558bedd9cec65aa003589a0681 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/923102 Commit-Ready: Jett Rink <jettrink@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Removing unnecessary register writesJett Rink2018-02-161-6/+1
| | | | | | | | | | | | | | | | | | | | According to Nuvoton datasheet, when SHM windows are in IO mode, only the bottom 16-bits of registers @ offset xF4 and xF8 are used. "This register is ignored when WRAM1_IO bit in WIN_CFG register is set to 1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This register is set to its default value by Host Domain reset." BRANCH=none BUG=none TEST=boot grunt and verify host communication still works. Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919006 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Fizz/CBI: Buid cbi-util as host-utilDaisuke Nojiri2018-02-162-33/+2
| | | | | | | | | | | | | | | This patch also removes make rules to stop producing CBI blobs. CBI blobs will be produced by another protage package. BUG=b:73123025,chromium:809250 BRANCH=none TEST=emerge-fizz chromeos-firmware-fizz and verify /build/fizz/firmware/cbi contains EEPROM images. Verify emerge ec-utils ec-devutils succeeds. Change-Id: I13744b0ab97675afa0247046bffa3edac3e62ceb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/909692
* tpm: ccd: allow alternative commands when ap is held in resetVadim Bendebury2018-02-151-6/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical CCD use case is when the DUT is not fully functional, or even completely dead, including corrupted AP/EC firmware. We still want to be able to enable CCD in this case, but routing CCD commands through TPM task context (necessary to ensure the large stack size some CCD commands require) is blocked if TPM was not reset after startup. Let's allow both reset requests and alternative commands when AP is held in reset after reboot. The only situation when the alternative command arrives would be the CCD use case of the system not generating TPM reset pulse at startup and the operator is trying to execute a CCD or RMA reset command. BRANCH=cr50, cr50-mp BUG=b:73292631 TEST=on a reef device: destroyed AP firmware and observed that the 'ccd open' command indeed results in the hung Cr50 console after Cr50 is reset in this state. Loaded the new Cr50 image, (which caused another Cr50 reset), successfully took it through the 'ccd open' sequence resulting in enabling AP flash write access, restored the AP flash and observed the DUT boot into Chrome OS. Change-Id: I4413bc200f5b2be563ba666ff80dd2d889ae5790 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/920924 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* led_pwm: Add a few more features to the ledtest commandSimon Glass2018-02-151-5/+10
| | | | | | | | | | | | | | | | | | | Add a way to report the current state using this command. This is useful when debugging. BUG=b:71902053 BRANCH=none TEST=manually > ledtest 0 PWM LED 0: led_id=0, auto_control=1 > ledtest 0 enable amber > ledtest 0 PWM LED 0: led_id=0, auto_control=0 Change-Id: I478980d82573b60b536ea0f4dcf324b7ccfb6fdb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919764
* grunt: Remove pull-up on UART pins.Aseda Aboagye2018-02-151-1/+2
| | | | | | | | | | | | | | | BUG=b:73135908 BRANCH=None TEST=Flash grunt; verify EC UART still functional. Reboot Cr50 a bunch without servo connected, verify that Cr50 never reports servo as "connected". Change-Id: I1ec402b4e3d0e9debdbb2af3a1ba5e1c45aa655a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917182 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: Convert spihash to TPM vendor commandRandall Spangler2018-02-152-128/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The console command now calls the vendor command to do the work. Otherwise, the same as before. BUG=chromium:804507 BRANCH=cr50 release (after testing) TEST=manual: # Sample sequence spihash ap -> requires physical presence; tap power button spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin spihash dump 0 128 -> dumps first 128 bytes; compare with image.bin spihash 128 128 -> offset works spihash 0 0x100000 -> gives a hash; doesn't watchdog reset spihdev ec spihash 0 1024 -> compare with ec.bin spihash disable # Test timeout spihash ap # Wait 30 seconds spihash 0 1024 -> still works # Wait 60 seconds; goes back disabled automatically spihash 0 1024 -> fails because spihash is disabled # Presence not required when CCD opened ccd open spihash ap -> no PP required spihash 0 1024 -> works spihash disable # Possible for owner to disable via CCD config ccd -> HashFlash is "Always" ccd set HashFlash IfOpened ccd lock spihash ap -> access denied # Cleanup ccd open ccd reset ccd lock Change-Id: Ife9335a1e402a7596d99bf515ec89ff94e8a0044 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910083 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* meowth: zoombini: enable CONFIG_CMD_PD_CONTROLCaveh Jalali2018-02-151-0/+2
| | | | | | | | | | | | | | | | we need to enable CONFIG_CMD_PD_CONTROL so the AP (depthcharge) can do TCPC firmware update. this was left disabled for bringup. BUG=b:69010531 BRANCH=none TEST=booted on meowth, was able to update TCPC firmware Change-Id: If383cff27c7b79f46f451c6380585d1300fc3413 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910322 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: set eSPI speed to max supported by hardwareCaveh Jalali2018-02-152-3/+12
| | | | | | | | | | | | | | | | | | the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up to 66MHz. so, set the max speed to whatever the hardware can actually do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's not even define it in the npcx7 case. BUG=b:72838699, b:71859563 BRANCH=none TEST="make buildall" passes; boots on meowth Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910321 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* meowth: zoombini: Remove internal pullups on UART.Aseda Aboagye2018-02-141-2/+2
| | | | | | | | | | | | | | | | | Cr50 requires no pullups on the EC UART pins. BUG=b:73135908 BRANCH=None TEST=Flash meowth; Reboot Cr50 a bunch, verify that servo is never seen as "connected". Change-Id: I88e4a2e510c1c795f2b240c3d742a7466acf696b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917181 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* charger/rt946x: Disable charge timerPhilip Chen2018-02-142-0/+9
| | | | | | | | | | | | | | | | | If the charge timer expires, rt946x would stop charging. We don't need this function. BUG=b:72571372 BRANCH=scarlet TEST=read reg 0x12 and confirm TMR_EN == 0 Change-Id: I38137ac39c7e7dfd15f12342428708697f81922c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/915501 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
* signer: advance to new version number and erase new bit in the rollback mapVadim Bendebury2018-02-132-4/+4
| | | | | | | | | | | | | | | | | | | This will prevent earlier released images from running on the device unless Info1 is erased. BRANCH=cr50, cr50-mp BUG=b:70891959 TEST=verified that two bits in the rollback mask have been erased now: > sysinfo Reset flags: 0x00000800 (hard) [...] Rollback: 2/2/128 Change-Id: Ic345c79010fbe0e075e14e652ea1eba263226ab1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/916737 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: move to prod RMA keyVadim Bendebury2018-02-131-6/+7
| | | | | | | | | | | | | | | The new key ID is set to zero. BRANCH=cr50, cr50-eve BUG=b:70891959 TEST=verified that prod server properly responds to the challenge generated by a CR50 running on Robo device. Change-Id: I1e0da4a2cebca7f985c5f2a6da509c850924a874 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/915503 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Michael Tang <ntang@chromium.org>
* npcx: do not power down eSPI when enabledCaveh Jalali2018-02-122-4/+11
| | | | | | | | | | | | | | | | | | | | if we're using eSPI for connectivity to the AP, we should never power it down... powering it down just causes transient errors on eSPI. BUG=b:72838699 BRANCH=none TEST=booted on meowth, no more eSPI bus errors. Change-Id: I737a03bb745868c7e8e02ffd5607db4d2da74c30 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910320 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* power_button_x86: Honor power_button_pulse setting on sysjumpFurquan Shaikh2018-02-121-2/+7
| | | | | | | | | | | | | | | | | | | On sysjump, if power button is held down, first check power_button_pulse_enabled setting to decide if powerbtn to pch should be asserted. This is important to prevent accidental shutdowns when user is attempting to do an EC reset with Vup+Pwr held down. BUG=b:73129177 BRANCH=None TEST=Verified following: 1. Reset EC by holding Vup+Pwr. 2. Keep holding Vup+Pwr until AP reaches depthcharge. 3. Ensure that AP does not shutdown. Change-Id: I0375fc8e8baabb40807dfdc6d4c9fa70c9b3b87d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912364 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usb-pd: Apply Vconn before Vbus as per USB TypeC spec (v 1.3)Jett Rink2018-02-121-7/+16
| | | | | | | | | | | | | | | | | | According to table 4-25 in USB TypeC spec version 1.3, Vconn should be sourced before Vbus or within 2ms. On Grunt I am see tVconnON around 2.3 ms, which is out of spec. We can simply source Vconn first to comply with spec. BRANCH=none BUG=b:72811851 TEST=Grunt's tVonnOn is now <2ms Change-Id: I52ca6a52bf576487061b2c33f348edf58eb06ca0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911928 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* grunt: Disable system power (_A rails) in G3Edward Hill2018-02-122-34/+49
| | | | | | | | | | | | | | | | | | | | | | EN_PWR_A GPIO turns on PP1800_A, PP5000_A, PP3300_A, PP950_A. These should be off in G3 and on in S5 and higher. VGATE (S0 power) is pulled high in G3 when SPOK (system power, S5) is low because PP5000_A turns off, so add a check for this and only pass through high VGATE when SPOK is also high. Leave kahlee behavior unchanged (power stays on in G3). BUG=b:72744306 BRANCH=none TEST=power on and off SOC, see GPIO_EN_PWR_A go low in G3 Change-Id: I68a1ac10263ad84d5ee154613e5e248edb4d287c Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/904729 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* eve: Use PCH ACOK signal to control Deep Sleep entryDuncan Laurie2018-02-123-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Deep Sleep states (DS3, DS5) are a special mode of the Intel PCH chipset that has very limited wake capabilities and breaks a number of common user expected behahviors. In particular, when in Deep S3 the USB ports are turned off and cannot continue to charge, wake the system, or maintain their internal state as they will lose 5V power. This is particularly painful with gnubby devices as they will need unlocked after every DS3 suspend/resume cycle. The only external signal that the PCH uses to determine whether or not to enter Deep Sx states is the ACPRESENT (aka ACOK) pin. Currently this pin is simply buffered from the charger and will be asserted whenever a charger is connected. This change extends the EC control over the pin to also assert ACPRESENT if either Type-C port is currently supplying VBUS. Now when a USB device is inserted the system will be enter S3 state, but not go into Deep S3 state. This allows the USB device to continue to charge, maintain it's internal state, and wake the system. BUG=b:64406191 BRANCH=eve TEST=verify GPIO_PCH_ACOK pin from the EC in different scenarios and test that system goes into S3 or DS3 state as expected: 1) no charger, no USB device: ACOK not asserted, DS3 enabled 2) charger but no USB device: ACOK asserted, DS3 disabled 3) no charger but USB device: ACOK asserted, DS3 disabled 4) charger and USB device: ACOK asserted, DS3 disabled Change-Id: I1cd132459194382e418970d29b1b195d8132cfad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/896164 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Enable hibernate using silegoElthan_Huang2018-02-125-12/+14
| | | | | | | | | | | | | | | | | | | | Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the EC. Thus, we don't use the internal hibernate/wake-up feature in npcx. BUG=b:72641658 BRANCH=none TEST=Test system will shutdown and doesn't auto wake up when type hibernate in ec console. And wake up by AC plugin, LID open, or power button. Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4 Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/890569 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* grunt: Turn PP1800_SENSOR off in S5Edward Hill2018-02-092-1/+19
| | | | | | | | | | | | | | | | | Disable sensor power (lid accel, gyro) in G3+S5. Enable it in S3+S0. We want it on in S3 for calculating the lid angle (needed on convertibles to disable resume from keyboard in tablet mode). BUG=b:72741289 BRANCH=none TEST=GPIO_EN_PP1800_SENSOR =0 in G3+S5 and =1 in S3+S0 Change-Id: I043b880b9fbd44242df0d2ac01c92a066d6b4377 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/912452 Reviewed-by: Lann Martin <lannm@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/mchp: Default SPI image script verobse output to disabledScott Worley2018-02-092-44/+73
| | | | | | | | | | | | | | | | | Disable MCHP chip Python SPI image generator verbose output. Verbose output only enabled if V=1 passed on make command line. Implemented by importing print as function and overloading. BRANCH=none BUG=810731 TEST=Build mchpevb1 with command line V unset, V=0, and V=1. Change-Id: I3da02b97796a8fe95f5e54634b84c962e14a19bf Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/911749 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb-pd: Clear active contract bit before browning out systemJett Rink2018-02-091-1/+6
| | | | | | | | | | | | | | | | In the case where we are resetting Vbus and it is our only power source, then we will brown out before we set the active port to 0. BRANCH=none BUG=none TEST=Did a cold reset on grunt with no battery power. System booted as normal. Change-Id: I3823af6b0475e4cf8abbe12dd8ae4ceef26d1eab Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911613 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* grunt: Making control of SCI and SMI interrupt pins more clearJett Rink2018-02-091-2/+5
| | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: I82d0a68f192fdc339af8682b99781cb16802ac32 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/911590 Reviewed-by: Edward Hill <ecgh@chromium.org>
* sn5s330: Disable vSafe0V interruptsEdward Hill2018-02-091-10/+11
| | | | | | | | | | | | | | | | | | | | | | | Turn off vSafe0V interrupts. They were not being handled or cleared causing the interrupt line to be stuck low after unplugging a USB device. Also don't use read-modify-write for INT_STATUS_REG4 since this would clear the dead battery mode bit before it has been checked. BUG=b:73076662 BRANCH=none TEST=unplug USB device, see USB_C1_SWCTL_INT_ODL=1 TEST=USB2 mouse can be connected multiple times, PPC VBUS detection works, BC1.2 chip turns on and off correctly (USB_C1_BC12_VBUS_ON_L). Change-Id: I96980ee330dd6e5f98e447e5e87f11dd60768a5d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/909549 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* meowth_fp: put fingerprint code in RW onlyVincent Palatin2018-02-094-7/+70
| | | | | | | | | | | | | | | | | | | | | | | | | Configure the fingerprint to be compile only in the RW partition for size reason, and keep the RO for firmware update only. Enable the RW signature to jump automatically to RW. The dev key was generated with the following command: openssl genrsa -3 -out board/meowth_fp/dev_key.pem 3072 Enable the new STM32H7 internal flash support along the way. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=run on ZerbleBarn and see the firmware jumping to RW, then run 'fptest' console command and get a proper capture. CQ-DEPEND=CL:*552559 Change-Id: Icc894b8a59b255b4c6a139f177e99d0fde7c4e19 Reviewed-on: https://chromium-review.googlesource.com/880955 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scarlet: shutdown PP900_S0 power rail when S3Lin Huang2018-02-091-2/+2
| | | | | | | | | | | | | | | | | | | we need to shutdown PP900_S0 power rail when S3 to save power consumption, let's do it. BUG=b:62644399 BRANCH=none TEST=run suspend_stress_test, it pass 1000 cycles CQ-DEPEND=CL:890228 Change-Id: I366effe9d2a99cb608069dd5d599171d32a9b4ce Signed-off-by: Lin Huang <hl@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/841902 Commit-Ready: Brian Norris <briannorris@chromium.org> Tested-by: Derek Basehore <dbasehore@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* charge_state_v2: No base/lid power transfer in S0ix/S5Nicolas Boichat2018-02-091-0/+10
| | | | | | | | | | | | BRANCH=none BUG=b:71881017 TEST=Suspend system, see that base does not provide power to lid, and vice-versa. Change-Id: I54e26c9b8decff2afdebc34adb62d4f5cef18e37 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/882524 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* battery: Allow 2 batteries to be fetched via ACPINicolas Boichat2018-02-095-15/+159
| | | | | | | | | | | | | | | | | | | | | We share the same shared memory fields for both batteries. When the host wants to switch battery to read out: - The host sets EC_ACPI_MEM_BATTERY_INDEX to the required index - EC then swaps the data is the shared memory fields, then update EC_MEMMAP_BATT_INDEX - Host waits for EC_MEMMAP_BATT_INDEX to have the required value, then fetches the data BRANCH=none BUG=b:65697620 TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are present, data is valid. TEST=Unplug base, BAT1 goes away, replug, BAT1 comes back. Change-Id: Icce12f9eef2f6f8cde9bae0a968a65e1703d0369 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/888382 Reviewed-by: Gwendal Grignou <gwendal@google.com>
* stm32: add internal flash support for STM32H7 familyVincent Palatin2018-02-096-8/+564
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32H7 family has 2 banks of flash (with 2 hardware controllers able to do 2 parallel operations at the same time). Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB variants). The flash can only be written by 256-bit word (with an additional 10-bit ECC computed by the hardware). For the flash write-protection, we cannot use our 'classical' PSTATE scheme as the erase-blocks are too large (128-kB) to dedicate one to this and the embedded word in the RO partition would not work as the flash has ECC and triggers bus-fault when the ECC is incorrect (which includes the case where the 256-bit word is written a second time). So we will do the following: - use the RSS1 bit in the option bytes as the Write-Protect enabled bit. - if the WP GPIO is set, lock at startup the option bytes until next reboot. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC console. Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6 Reviewed-on: https://chromium-review.googlesource.com/901423 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Fix shmalloc unit testVincent Palatin2018-02-092-2/+2
| | | | | | | | | | | | | | | | | | | | | We want to build the shmalloc common code in test mode *only* for the shmalloc test not for all test binaries (which are missing the helper functions). The previous version was broken for any board declaring CONFIG_SHMALLOC (but none were excepted cr50 which has tests disabled) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=emerge-meowth chromeos-ec Change-Id: Ic89c74569fbadbc75d9090b084adab8f40ddfa5d Reviewed-on: https://chromium-review.googlesource.com/909210 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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