| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=none
TEST=none
Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155066
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Owners-Override: Jora Jacobi <jora@google.com>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
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The extentions were added to make the compiler perform most
of the verification that the conversion was being done correctly
to remove 8bit addressing as the standard I2C/SPI address type.
Now that the compiler has verified the code, the extra
extentions are being removed
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
TEST=verify sensor functionality on arcada_ish
Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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* Update **test** directory description to README.md.
* Add ** fuzz** directory description to README.md.
* Add unit test and fuzzer make targets to `make help`
* Change showboards to print-boards to be more consistent
* Change showboards to use auto pretty print
* Add print-tests, print-host-tests, and print-host-fuzzers
This is necessary to remove the ambiguity about what a special
name is for a given unit test.
Documentation Story:
The idea is to give a brief overview of what the test and fuzz
directories are in README.md.
README.md also mentions you should see `make help` for more detail.
Running `make help` shows you more general test/fuzz commands,
including the print-* commands.
Running the print-* commands show you exact target names for all
possible unit/fuzz test (both the build-only and run target names).
BRANCH=none
BUG=none
TEST=make help
TEST=make print-tests
TEST=make print-host-tests
TEST=make print-host-fuzzers
TEST=make print-host-fuzzers | cat
TEST=make print-boards
TEST=make print-boards | cat
TEST=make buildall -j
Change-Id: I34b68196ac635ba71a1d45ceb5d35a3b36fd129f
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684714
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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For the normal lab use, emulating a sink has no PD comm, like a passive
hub. For the PD FAFT use, we need to validate some PD behavior, should
support sink roles with PD comm enabled. Two new roles "pdsnk" and
"pdsnkdts" are introduced.
BRANCH=servo
BUG=b:134700685
TEST=Typed "cc pdsnk" or "cc pdsnkdts" can transit the DUT port to
the PD state "SNK_READY", instead "SNK_DISCOVERY".
Change-Id: If6a7c39cd296986b8b28de1c1fbe66ee8438c709
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682920
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Support a new flag to enable DRP. The do_cc() function becomes having 4
arguments. So change to merge them into a single cc_config with
different bit masks.
For the force_source or force_sink role, we explicitly set the the Rp
or Rd resistors on CC lines. But for DRP role, the Rp/Rd toggling is
controlled by the PD state machine. So don't set any CC pull resistor
for DRP.
Support an "on" option in "cc" command to restore the previous role
before emulating detach.
Add "usbc_action drp" to toggle the DRP state, which is compatible with
Plankton.
BRANCH=servo
BUG=b:135691171
TEST=Ran the firmware_PDTrySrc test passed, and not break all the
existing PD FAFT tests.
Change-Id: I3b90611c9840f502e496c42f80354e7ee002f96e
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682919
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Update the PD policy and comments:
* Only allow data role swap on DUT port;
* Remove the dts mode condition to initiate a data role swap
(not necessary to limit it to dts mode).
BRANCH=servo
BUG=b:135691171
TEST=Checked the CHG port is always UFP.
TEST=Checked the DUT port is SRC/UFP, a data role swap happened (but
it was initiated by DUT).
Change-Id: I668703209301a9542e94768f31f6ce8e2d9eb0f4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The pd_config_init() does two things:
* pd_tx_init() to init the GPIO MODULE_USB_PD;
* pd_set_host_mode() to set CC pull resistors.
The pd_config_init() is called on PD phy init hook.
For setting CC pull resistors, calling pd_set_host_mode() is enough.
Don't need to reinit GPIO MODULE_USB_PD.
BRANCH=servo
BUG=b:135691171
TEST=Set "cc" role to "src", "snk", "srcdts", "snkdts", and "off".
TEST=Unplugged and replugged the CHG port cable.
Change-Id: I1e783dfa5da4f8e8f1d9d591818eb1128b7a8caa
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1682917
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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When the requester does not expect the chip information from the live
target, return the hardcoded vendor and product id.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=Boot to ChromeOS
Change-Id: I74affb00951411a3483258a8db165038e7eb683f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617894
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as
follows:
0 -> Return hard-coded info for Vendor ID/Product ID and cached info for
the Firmware Version
1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version
Also rename the 'renew' field to 'live' to match the new semantics.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS.
Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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The octopus baseboard should only declare the sensor CONFIG_ values
if we didn't define the NO_SENSORS variant
BUG=b:137758297
BRANCH=None
TEST=buildall
Change-Id: I32443f08ee7d1412b425bd55c8c40d67f22ef089
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706687
Reviewed-by: Enrico Granata <egranata@chromium.org>
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Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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In servo v4 hardware logic, both CC lines are wired directly
to DUT. When servo v4 as a snk, DUT may source Vconn to CC2
and make the voltage high as vRd-3.0, which makes the PD
state mess up. As the PD state machine doesn't handle this
case. It assumes that CC2 is separated by a Type-C cable,
resulting a voltage lower than the max of vRa.
It fakes the voltage within vRa so the PD state machine
checks the value as expected.
This is an issue only happening on servo v4 as it wires both
CC lines to DUT.
BUG=b:134700685
BRANCH=servo
TEST=Servo v4 as snk, verified the CC2 is sensed vRa, i.e.
the output "CC1:0" (TYPEC_CC_VOLT_OPEN), instead of "CC1:7"
(TYPEC_CC_VOLT_SNK_3_0).
2019-06-18 15:05:47 > cc snk
2019-06-18 15:05:50 cc: on
2019-06-18 15:05:50 dts mode: off
2019-06-18 15:05:50 chg mode: off
2019-06-18 15:05:50 chg allowed: off
2019-06-18 15:05:50 > C1 st2 SNK_DISCONNECTED
2019-06-18 15:05:50 C1 st3 SNK_DISCONNECTED_DEBOUNCE
2019-06-18 15:05:50 C1 st5 SNK_DISCOVERY
2019-06-18 15:05:51 > tcpc 1 state
2019-06-18 15:05:53 Port C1, Dis - CC:2, CC0:6, CC1:0
2019-06-18 15:05:53 Alert: 0x00 Mask: 0x007d
2019-06-18 15:05:53 Power Status: 0x48 Mask: 0x00
TEST=Ran the PD FAFT test firmware_PDConnect passed.
Change-Id: I10f1ffe80768100ee3ed4c374598df7c2f9a8d05
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1666468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This patch let the tester exit with an error code on test failure.
It would make easy the future autotest to detect a failure.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
[before patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
...
$ echo $?
0
[after patch]
...
INFO | UartSerial| EC | 14888 char lost / 1382400 (1.1 %)
INFO | UartSerial| AP | 0 char lost / 1382400 (0.0 %)
ERROR | ChargenTest | FAIL: lost 14888 character(s) from the test
Error: Test failed for losing 144888 character(s)
...
$ echo $?
1
$ ./util/uart_stress_tester.py /dev/ttyUSB1 /dev/ttyUSB2 -t 120 -d
Error: /dev/ttyUSB1 does not exist.
$ echo $?
1
Change-Id: I210efd4ad7fdb8eb612206624eda6c39c5bb3b1c
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696115
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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During initialization, uart_stress_tester checks each of ports
exists, and raises an error if not.
BUG=None
BRANCH=None
TEST=ran on fleex.
$ uart_stress_tester.py /dev/ttyUSBX -t 120
Error: [Errno 2] No such file or directory: '/dev/ttyUSBX'
$ ./util/uart_stress_tester.py ./util/uart_stress_tester.py -t 120
Error: ./util/uart_stress_tester.py is not a character device.
Change-Id: I989a9e767796b04b059861aea2a3412877c1d739
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706626
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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According to the DisplayPort Alt Mode on USB Type-C specification, if
the DisplayPort Source device does not need to maintain HPD connectivity
information prior to entering a low power state, the device shall exit
the DP Alternate Mode. Previously, we were always entering DP Alt Mode
regardless of the SoC state. When we are shutting the device down to S5
or G3, there's no need to monitor the HPD connectivity information.
This commit simply does not enter DP Alt Mode when the SoC is off.
BUG=chromium:927636
BRANCH=firmware-nocturne-10984.B
TEST=Flash nocturne, shut DUT down to S5/G3, plug in a USB-C monitor
that can also act as a Source, verify with PD analyzer that DUT does not
Enter DP Alt mode, boot system up, verify that external display works.
Change-Id: I2ad3619cabeae5d90e8af1bfa9cab67452d9fc16
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1450815
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This patch adds a usual inclusion guard (#ifdef __CROS_EC_*_H) and
fixes API descriptions.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I96149cfe76cff7ab85be4785252a600b565e4a92
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1696913
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
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Markdown docs don't affect the build. Make presubmit slightly nicer.
BUG=none
BRANCH=none
TEST=run util/presubmit_check.sh after committing docs/ only changes
Change-Id: I273dd071e3cf5e859a0a4f0f97e9011cc4391f0d
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1706613
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The power rail for the 5V used for sourcing is not available while the
chipset is off. Therefore pd_set_power_supply_ready() should return an
error if chipset is off.
BUG=b:118646299
BRANCH=firmware-nocturne-10984.B
TEST=Flash nocturne; plug in a USB Type-C ethernet adapter, run
`dut-control power_state:rec` and verify that VBUS is present at the
insert screen.
TEST=Repeat the above test 20 times and verify that it always succeeds.
Change-Id: Ie675d862dfbbe1e1ce08f6b203008ee784eb8ede
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/1307699
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit b6db88f25366a4519ad45d4b54e91cb40e7ea7fb)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1708266
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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In EMULATED_IRQ_EVENT mode, we try to estimate the time between a read
request and data ready. If the estimated time is shorter, an error
message is printed to the console on every retry.
On Kukui, this caused ec console spamming one line per second.
Change the behavior to print only when returning error.
No need to adjust the estimate time because one retry per read is still
good enough.
BUG=b:137345336
TEST=manually, verify that error message disappeared.
BRANCH=None
Change-Id: Ie85e8f1a80ea36ca5c50f57a19eba35f3f79f86d
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697889
Tested-by: Fei Shao <fshao@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Setting Type-C Port1 controller register 0xE8 (High Speed Signal
Detector threshold adjustment) to 0x80 (-25%).
BUG=b:136531130
BRANCH=master
TEST=Manual
Check Type-C Port1 register 0xE8.
Change-Id: I5957fcd3389296500992ea3075dcde4a3b690f98
Signed-off-by: Barney_Liao <barney_liao@pegatron.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703724
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch addresses a few issues with the current formatter.
The major points are as follows:
1. Cannot specify precision 0 (truncate all) for string or hexdump
2. Forced safe precision for malformed strings
3. No padding when using hexdump
4. Bad error EC_ERROR_INVAL in vsnprintf
5. Documentation errors
For (1), no piece of code explicitly sets the precision to 0 in
order to invoke the default behavior, which is currently no
precision limit.
You can check using the following grep line:
grep -rI '%[\*0-9]\{0,20\}\.0\{1,20\}[a-zA-Z]'
However, there are many cases where the precision is used to limit
the character output (as it should be).
grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]'
There are many more instances that use variable precision without
checking if the precision is zero. One of which is the following:
crrev.com/4a4e2c71a0f6aaa50e0728922f84a7d54c14380a/test/host_command_fuzz.c#116
https://clusterfuzz.com/testcase-detail/5699023975088128
Our current implementation will insert ERROR and stop processing,
if a precision of zero is detected when using the hexdump flag.
This results in a badly formatted console line or runtime string,
when the intended behavior would be to simply read no bytes.
In the aforementioned fuzzer case, outputting ERROR triggers
a false positive.
Our printf should handle explicit zero precision similar to
stdlib's printf, which means truncating all the way to zero
positions, if specified.
For (2), our current implementation uses strlen to identify the
length of the input string, regardless of the set precision.
Since this is an embedded platform, we should use strnlen to
impose safe limits, when a precision is specified.
For (3), our implementation should support padding and adjusting
of all formatter types, since that is a primary feature of a
printf formatter.
The remaining commented code highlights odd behavior that should
be fixed at some point, but is not critical.
BUG=chromium:974084
TEST=Checked for any format lines that rely on a set precision of 0
grep -rI '%[\*0-9]\{0,20\}\.[\*0-9]\{1,20\}[a-zA-Z]'
TEST=make run-printf V=1
BRANCH=none
Change-Id: I897c53cce20a701fcbe8fb9572eb878817525cc3
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1659835
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This adds fake SPI Master and TRNG support to the
host target.
This change also adds the missing emulated gpio
interface function.
Although general purpose, these changes are setup for
allowing fuzzing of the FPMCU specific host commands.
Thus, they do not impact any outstanding code.
BRANCH=none
BUG=b:116065496
TEST=make buildall -j
Change-Id: Icfc40e7bf8ee421a4c3ad15377fd56ae68c763d7
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684223
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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By fixing the bug(b/136282898) to allow MKBP events to wake the system
in suspend, all MKBP events would wake the system which goes against our
chrome OS wake sources spec. By defining CONFIG_MKBP_EVENT_WAKEUP_MASK,
nocturne will not wake on any MKBP event.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, suspend DUT, plug in powered charge-thru
hub w/ an external display connected, verify that DUT does not wakes up
and display is not shown.
Change-Id: I0810d0ea625689ee39f0e52b62a8ee7c00c49aad
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685788
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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Previously, the EC could notify the AP that it had entered into
DisplayPort Alternate mode by sending a MODE_CHANGE host event.
However, there was no mechanism to disable that functionality if desired
without effecting the other MODE_CHANGE events (i.e. - base
attach/detach). By changing the DisplayPort Alternate mode entry to an
MKBP event, we can have more granularity and only affect this single
event.
- This commit adds a new MKBP event, EC_MKBP_EVENT_DP_ALT_MODE_ENTERED.
- The commit also changes the DP AltMode entry notification from sending
a MODE_CHANGE host event to this new MKBP event.
BUG=chromium:786721
BRANCH=None
TEST=Build and flash nocturne, verify that system still wakes up on
DisplayPort Alternate Mode entry.
Change-Id: Ia5f294b26701c3c98c9b7f948fc693d26234c835
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685787
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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MKBP was recently refactored to offer choice in the MKBP notification
method. However, if a board is using a GPIO to notify the AP of a MKBP
event, and the AP cannot wake from the GPIO, the MKBP event cannot wake
the system up from suspend as is. This commit simply adds a new config
option, CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT such that MKBP events can
wake the system from suspend. Note that the board will have to add MKBP
events to the host event sleep mask in coreboot. Typically on ARM
devices, EC_INT_L is already a wake pin, but on Intel devices it is not;
there's actually a different pin, PCH_WAKE_L which is set via sending a
host event and wakes the system.
BUG=b:136272898,chromium:786721
BRANCH=None
TEST=Enable config option on nocturne, flash nocturne, suspend DUT,
verify that MKBP events can wake the AP.
Change-Id: If5026bfe3efacbc051f99a180e061c6fd679ce5a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685786
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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crbug.com/982442 requests a way for developers to enable tracing of
i2c commands when debugging. This adds a new debug feature, the
i2ctrace command, which provides that. The command is guarded by
CONFIG_I2C_DEBUG.
BUG=chromium:982442
BRANCH=none
TEST=enabled CONFIG_I2C_DEBUG on arcada_ish, made sure that command
functioned as it says on the tin
Change-Id: I9c762271237cbf131e5ef7c0f605c89af4f209fd
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699347
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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Includes System Clock, Timer, Uart, Watchdog
Change-Id: I195059c87d97e70c6a134304143613b86b623e22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647741
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Jerry Bradshaw <jerry.bradshaw@maximintegrated.com>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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CONFIG_SMBUS is not used. Cleaning up the code by
removing this.
Added a comment to document the removal and why. This will
give a way to find the code if we ever needed to bring it back
BUG=chromium:982316
BRANCH=none
TEST=make buildall
Change-Id: I40703a95bc849538e1aee32f6f96beab811285bd
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704279
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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EAR (extended address register) is used to access addresses above
16MiB when 3-byte address mode is used. These two functions allow to
write to and read from EAR to set up what addresses to access in
3-byte mode. For example, for a 64MiB EEPROM:
EAR value Addresses to access
0 0x0000000 - 0x0FFFFFF
1 0x1000000 - 0x1FFFFFF
2 0x2000000 - 0x2FFFFFF
3 0x3000000 - 0x3FFFFFF
BUG=b:132252340
BRANCH=none
TEST=manual
Testing:
1. Writing to EAR returns successfully.
2. Writing different values to EAR, verify that accessing EERPOM
in 3-byte mode is to the correct address, e.g., when EAR=2,
accessing 0x0FFFFFF is actually to 0x2FFFFFF.
Change-Id: I2a8bde7fc4b9069afc80a81042fb47359bffa015
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688150
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Pai Peng <paipeng@google.com>
Commit-Queue: Pai Peng <paipeng@google.com>
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There is no room in the flash for both dcrypto tests and the TPM
library. Let's disable TPM function (and not link the library) when
the image is compiled with dcrypto tests included.
BRANCH=cr50, cr50-mp
BUG=b:137659935
TEST=verified that there is plenty of room for tests now:
$ make BOARD=cr50 -j -k CRYPTO_TEST=1 CR50_DEV=1
.
.
.
*** 8124 bytes in flash and 61564 bytes in RAM still ... in cr50 RO ***
*** 66100 bytes in flash and 6000 bytes in RAM still ... in cr50 RW ***
- building without CRYPTO_TEST=1 still produces a functional Cr50
image;
- when building with CRYPTO_TEST=1, the version string reflects it:
$ strings build/cr50/ec.bin | grep cr50_v | head -1
DBG/CT/cr50_v2.0.1776-46b015f6a
- CCD of the images built with crypto test enabled is fully
functional, in particular USB updates are operational.
Change-Id: Iae91ca36dc203301ac423fe048fc67eb44ef5de6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704608
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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Presently the CR50_DEV environment variable is overloaded, if its
value is a number exceeding 1, it enables inclusion in the image of
the dcrypto tests.
To make things cleaner let's use a separate environment variable to
add dcrypto tests to the image. Note that the tests still can not be
enabled, as they do not fit into the flash code space.
BRANCH=cr50, cr50-mp
BUG=b:137659935
TEST=verified that image building with CRYPTO_TEST=1 fails due to
exceeded code size.
Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Looking at where the non-standard %T printf modifier is used in EC
codebase, the majority is cases where CPRINTS could have been used
instead of CPRINTF. This is a somewhat-mechanical refactor of these
cases, which will make implementing a standard printf easier.
BUG=chromium:984041
BRANCH=none
TEST=buildall
Change-Id: I75ea0be261bfbfa50fb850a0a37fe2ca6ab67cb9
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703128
Reviewed-by: Evan Green <evgreen@chromium.org>
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Prevent a starved waiting IPC.
IPC may be requested while SCP_IRQ_IPC0 is disabled, and this may
result in AP dead waiting for a reply from SCP. This CL forces
triggering the SCP_IRQ_IPC0 if seeing a pending IPC when re-enable
the SCP_IRQ_IPC0.
TEST=run factory front_camera_test for over 1 hr and see AP doesn't
complains HC not respsonsed.
BUG=b:136809224, b:136616282
BRANCH=None
Change-Id: Ic36da774994f6c571c3b79fd6717562f8866b7df
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697884
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
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This config has been moved to kernel https://crrev.com/c/1687454 to
correctly initialize L1 cache. We should drop the config in SCP side.
Also, update the comment for CM4_MOD registers.
TEST=Boot SCP with kernel https://crrev.com/c/1627394/10
BUG=b:132658087
BRANCH=none
Change-Id: I37613533563acc00017f96a3d3009383057f072b
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Erin Lo <erin.lo@mediatek.com>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Auto-Submit: Yilun Lin <yllin@chromium.org>
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Depend on placement modify rotation matrix for the lid and base sensor.
BUG=b:135554555
BRANCH=ToT
TEST=Manual
Check EC console accleinfo.
Change-Id: I287808dde06ff752f9e10766f3c348e0d63606f3
Signed-off-by: Barney_Liao <barney_liao@pegatron.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1687037
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Although these registers files may support other variants,
these listed variants are the only ones that are referenced
throughout EC codebase.
They were collected using the following grep line:
grep -rIi 'variant.*stm32.'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I3691d8db5c2a6c1a94bb5df40edf12504c3fee7e
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700168
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This extracts the STM32F76X variant from the STM32F4 family
registers file.
This also removed a redundant #ifdef CHIP_FAMILY_STM32F4
inside the F4 family register file.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
# Make dummy board for STM32F76X using STM32f7 fammily
mkdir -p board/usestm32f7
printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f7\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk
touch board/usestm32f7/board.h
./registers-extract.bash board-regs-new
git checkout cros/master
# Change family back to STM32F4
printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f4\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
# Expect only a difference in CHIP_FAMILY
Change-Id: I5ff87e1c82c5d27d78c3ea62fed29d647a0f98db
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700167
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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We enforce that all family specific registers file can only be
included from registers.h.
We add a brief history and rationale behind splitting registers.h into
multiple family specific header files.
We fix formatting of preprocessor conditionals and documentation.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
./registers-extract.bash board-regs-new
git checkout cros/master
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
[ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad"
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: I5d5983eb1e0cf7fb46339cba2987d551ff6b16cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693879
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: If44a363d1288cbfabe5c6545e550f2b8fc623227
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700793
Reviewed-by: Jett Rink <jettrink@chromium.org>
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BUG=b:130578043
BRANCH=none
TEST=battery command on EC console
Change-Id: I2518892dac3daeae8734bd3b45f225f4723dc7c6
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704788
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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fo* should come before fp*
TEST=print help
Change-Id: Ic8ea8582bd1aebfb389427d959b8819aecb67378
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703391
Tested-by: Curtis Malainey <cujomalainey@chromium.org>
Auto-Submit: Curtis Malainey <cujomalainey@chromium.org>
Reviewed-by: Jon Flatley <jflat@chromium.org>
Commit-Queue: Jon Flatley <jflat@chromium.org>
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This commit adds a new CONFIG_* option, CONFIG_MKBP_EVENT_WAKEUP_MASK.
This allows a board to specify which MKBP events are allowed to wake the
system when it is in suspend.
BUG=b:136282898,chromium:786721
BRANCH=None
TEST=With some other code, flash nocturne, suspend DUT, verify that only
the MKBP events in the CONFIG_MKBP_EVENT_WAKEUP_MASK wake the system up.
Change-Id: Ib4d04418aacab209d0e26703500df119924090b7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1685785
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This contains the initial firmware for Fluffy rev 1.1 boards.
Fluffy is a 20:1 USB-C power mux. For more information, see
go/usbc-fluffy.
BUG=b:136671092,b:134075217,b:134074302,b:134074465,b:134075521,
b:134075834
BRANCH=None
TEST=flash fluffy, verify it boots and functions.
Change-Id: Ica6817e7cfa4481aa98fed1c24ea243bf622eb2a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1535117
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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This fixes the CPP conditionals that could not be separated
using the split script.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
./registers-extract.bash board-regs-new
git checkout cros/master
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
[ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad"
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: I40eac114cd5ed7abe708cc51242a3b267aaaf118
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693876
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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For kohaku board id 1, there is a known issue which prevents in
getting battery presence signal correctly. This change returns BP_YES
if the board id reads out as 1. In all other cases, it returns
BP_NOT_SURE to allow baseboard to read gpio to determine battery
present state.
BUG=b:135278000
BRANCH=None
TEST=None
Change-Id: I882f05ddcf4e8a0127f336b4a524bf162ad796b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1702870
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YongBeum Ha <ybha@samsung.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Tested-by: YongBeum Ha <ybha@samsung.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
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In case of some hatch variants, there might be a need to identify
battery hardware presence using custom method
i.e. GPIO_EC_BATT_PRES_ODL might not work correctly. In order to
accommodate these variants, this change provides a callback
variant_battery_present() that allows variant to provide its own
implementation if required. By default, a weak implementation is
provided which returns BP_NOT_SURE to use the default GPIO for reading
battery present state.
BUG=b:135278000
BRANCH=None
TEST=None
Change-Id: I8504e807cff853dc3276d76a0cd3db1ccb587b9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1702869
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YongBeum Ha <ybha@samsung.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Tested-by: YongBeum Ha <ybha@samsung.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
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I noticed Coverity is complaining about a handful of printf format
warnings. These were all valid. It looks like a robot, or perhaps a
very hasty human went through and split printf strings that
extended over 80 columns into multiple calls. But they didn't make
sure that the arguments went into the correct corresponding
printf call.
Recombine a few of those printfs back into a single call, and fix a
few other printf-related odds and ends.
Also, add the format specifier to my_printf so that these errors are
detected at compile time in the future.
BUG=chromium:984041
TEST=make -j buildall
BRANCH=None
Change-Id: I27b352b97d50fbbaee2fb801b817ef82ad90ca98
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1698488
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Using the sort_file.bash script from this bit:
http://go/bit/hesling/5840756455505920/7
$ git fetch "https://chromium.googlesource.com/chromiumos/platform/ec" refs/changes/78/1674678/6 && git cherry-pick FETCH_HEAD
$ cp registers.h registers-split.h
$ ./sort_file.bash chip/stm32/registers-split.h f0=chip/stm32/registers-stm32f0.h f3=chip/stm32/registers-stm32f3.h f4=chip/stm32/registers-stm32f4.h h7=chip/stm32/registers-stm32h7.h l=chip/stm32/registers-stm32l.h l4=chip/stm32/registers-stm32l4.h com=chip/stm32/registers.h
Modified registers.h to include chip family specific header file.
Modify copyright year of output files.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
./registers-extract.bash board-regs-new
git checkout cros/master
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
[ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad"
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: Ia7804e9a346ed94f881bd5583f5a4bf78422cb47
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674679
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:132444384
TEST=On hatch_fp:
ectool --name=cros_fp reboot_ec;
sleep 0.5;
ectool --name=cros_fp rwsigaction abort;
dd if=/dev/urandom of=/tmp/rand_file bs=1 count=131072;
ectool --name=cros_fp flashwrite 262144 /tmp/rand_file
Change-Id: I22f70ae29285dc5bded558b9f0bcbe5040a80750
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677234
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Extend the unit test for checking FPTPM seed status, specifically:
1. After seed is set, try set the seed again, expect failure.
2. At this point, check that the seed is still set.
BRANCH=nocturne
BUG=chromium:952275
TEST=make -j buildall
TEST=tested enrollment, matching and multifinger on DUT nocturne.
Change-Id: I2be9d2c21b552f242dd88f33361398755b6c2e84
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1643659
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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