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* Clear OWNERS for factory/firmware branchfactory-beltino-5140.14.BBrian Norris2021-09-101-0/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3155041 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* mec1322: ADC driverVic (Chun-Ju) Yang2013-12-206-0/+172
| | | | | | | | | | | | | ADC driver for MEC1322 with ADC interrupt support. BUG=chrome-os-partner:24107 TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180832
* Move ADC console command to commonVic (Chun-Ju) Yang2013-12-205-51/+70
| | | | | | | | | | | | | | | | | | | We have three duplicated ADC read console command, and we are about to have the fourth. Let's consolidate them to a single implementation in common/. Note that we have to add a simple implementation of adc_read_all_channels() for LM4. BUG=chrome-os-partner:18343 TEST=Build all boards TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I079c0b33ab6b81a188f309cf99875eb02e9d78a4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180831
* nyan: wait 225ms for PMIC RTC start-upLouis Yung-Chieh Lo2013-12-201-0/+20
| | | | | | | | | | | | | | | | | The first time the PMIC sees power (AC or battery) it needs 200ms (+/-12% oscillator tolerance) for the RTC startup. In addition there is a startup time of approx. 0.5msec until V2_5 regulator starts up. BUG=None BRANCH=nyan TEST=verified on rev 3.12 with AC/battery replug * 10. Power button on/off and 'power on/off' are not effected. Change-Id: I706829017a53c549601a925cb18d33b21c50eb76 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180677 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Lower critical temps below CONIFG_PECI_TJMAXChromeOS Developer2013-12-204-4/+4
| | | | | | | | | | | | | | | | | | | | | This lowers, the WARN, HIGH, and HALT temp thresholds for x86 boards to below their CONFIG_PECI_TJMAX value. Also lowers the FAN_MIN and FAN_MAX temps by 5 degrees on Haswell boards to compensate for lowering TJ_MAX by 5 degrees in an earlier patch. BUG=chrome-os-partner:24455 BRANCH=none TEST=Manual. Run boards without a fan and without any host-side throttling. Verify that board either reaches a steady state temp due to throttling or hits SHUTDOWN and turns off before EC reset is triggered. Change-Id: I499baa0b4100201525e69752af3465feb592262c Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179886 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* nyan: change the XPSHOLD waiting timeLouis Yung-Chieh Lo2013-12-191-21/+8
| | | | | | | | | | | | | | | | According to the nVidia power engineer, we shall wait for 40ms to see XPSHOLD asserted after PMIC_PWRON_L is asserted. Also change the code since it was obscured. Comments was out-of-sync too. BUG=None BRANCH=None TEST=Verified on rev 3.12. Change-Id: If479d8398f4008f0b029d450b3d28ac98cdf969f Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Increase hook task size on x86 platformsRandall Spangler2013-12-195-5/+5
| | | | | | | | | | | | | | | | AP throttling in the thermal task ends up calling a pretty deep nested set of calls, and in the worst case can overflow the stack. Bump up the stack size for the hook task on x86 platforms to compensate. BUG=chrome-os-partner:24536 BRANCH=peppy/falco TEST=taskinfo shows hook task increased from 512 to 640 bytes stack shmem shows at least 4000 bytes free Change-Id: I63da7c47b993c935d895f91d787844655071da0d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180684 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* nyan: change the PMIC_WARM_RESET_L pin to open-drainLouis Yung-Chieh Lo2013-12-191-1/+1
| | | | | | | | | | | | | | So that Tegra wants to drive the PMIC_WARM_RESET_L low it will not be fighting the EC. BUG=None BRANCH=None TEST=Verified on the board rev 3.12 Change-Id: I5980a3ba096c152a4ccc28ad64e675c53b7cb337 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180520 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-1958-251/+248
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* cleanup: Remove mixed-case macrosRandall Spangler2013-12-192-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | We've had uppercase macros (BOARD_FOO) for a week for PROJECT_ BOARD_ CORE_ CHIP_ CHIP_FAMILY_ CHIP_VARIANT_ and I've just made a pass to fix the last leftover mixed-case usage from changes that were in flight when I made the initial cleanup. It is now time to remove the old mixed-case macros (BOARD_foo). BUG=chromium:322144 BRANCH=none TEST=Build all boards. Diff build/$(BOARD)/ec.RO.map before and after this change. Should be no changes - indicating that the same code was compiled before and after. Change-Id: Ic5a1e83d31be4b8e9fdbacc3eb10176fd126d84a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180384
* Add AP hang detectionRandall Spangler2013-12-179-0/+379
| | | | | | | | | | | BUG=chrome-os-partner:24558 BRANCH=none TEST=see procedure in bug Change-Id: I42614a1da5f24c93b6267d81339ff9d721bf0d8f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180080 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Fix the last few mixed-case BOARD_ macrosRandall Spangler2013-12-171-6/+6
| | | | | | | | | | | | | | All macros are now uppercase. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, TEST, CHIP_FAMILY, CHIP_VARIANT.) Change-Id: I04850e569b3950bb88f9dff107de06dfa49b04fc Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180430 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: handle dummy GPIO gracefullystabilize-springlte-5116.46.Bstabilize-5116.88.Bstabilize-5116.53.Bstabilize-5116.115.Bstabilize-5116.113.Brelease-R33-5116.BVic (Chun-Ju) Yang2013-12-171-11/+31
| | | | | | | | | | | | | | | | When a GPIO signal is defined by GPIO_SIGNAL_NOT_IMPLEMENTED, it should still be able to call various GPIO methods on that GPIO signal. Since __builtin_clz dies when the value passed in is zero, we need to check this before calling __builtin_clz. BUG=chrome-os-partner:24107 TEST='sysjump RW' and the system doesn't crash BRANCH=None Change-Id: I5025a2f218d549316fe096c07bd3c7207fe9dbc2 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180183 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i8042 interfaceVic (Chun-Ju) Yang2013-12-172-0/+62
| | | | | | | | | | | | | This implements i8042 keyboard interface at LPC 0x60/0x64. BUG=chrome-os-partner:21407 TEST=Enable keyboard and keystroke from host ACPI commands. Short KSO pins and KSI pins, and read different key codes from host. BRANCH=None Change-Id: Ie4e5e236bdeefd7e44974f92fcbafab5e4af2b30 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179940
* Protect inactive EC image from code executionDaisuke Nojiri2013-12-173-70/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change configures MPU to prevent instruction fetch from the flash image that is not running at the time system_disable_jump is called. Violating the protection causes instruction access violation, then the EC reboots. RO image protection is tested as follows: ... [6.255696 MPU type: 00000800] [6.255874 RAM locked. Exclusion 20005680-200056a0] [6.256168 RO image locked] ... > sysjump 0 Jumping to 0x00000000 === PROCESS EXCEPTION: 03 ====== xPSR: 60000000 === r0 :00000000 r1 :2000541c r2 :00001388 r3 :20007fe8 r4 :200032f0 r5 :00000000 r6 :20002b70 r7 :20002df4 r8 :0002d308 r9 :20002df4 r10:00000000 r11:00000000 r12:00000002 sp :20002358 lr :0002a1a7 pc :00000000 Instruction access violation, Forced hard fault mmfs = 1, shcsr = 70000, hfsr = 40000000, dfsr = 0 =========== Process Stack Contents =========== 200023c0: 00000098 00000000 00000000 0002a785 200023d0: 00000002 20002dfd 00000007 20002b70 200023e0: 00000002 00025777 00000000 20002dfd 200023f0: 20002df4 20002dfc 00000000 00000000 Rebooting... Memory management fault status register has bit0 set, indicating there was an instruction fetch volation. FYI, RAM protection is still working: > sysjump 0x20000000 Jumping to 0x20000000 === PROCESS EXCEPTION: 03 ====== xPSR: 60000000 === r0 :00000000 r1 :2000541c r2 :00001388 r3 :20007fe8 r4 :200032f0 r5 :20000000 r6 :20002b70 r7 :20002df4 r8 :0002d308 r9 :20002df4 r10:00000000 r11:00000000 r12:00000002 sp :20002358 lr :0002a1a7 pc :20000000 Instruction access violation, Forced hard fault mmfs = 1, shcsr = 70000, hfsr = 40000000, dfsr = 0 =========== Process Stack Contents =========== 200023c0: 00000098 00000000 20000000 0002a785 200023d0: 00000002 20002e06 00000007 20002b70 200023e0: 00000002 00025777 00000000 20002e06 200023f0: 20002df4 20002dfc 00000000 00000000 Rebooting... TEST=Booted Peppy. Tested lid close & open. Ran Flashrom from userspace to update main firmware then software-synched an EC image. BUG=chrome-os-partner:16904 BRANCH=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Id4f84d24325566a9f648194166bde0d94d1124dc Reviewed-on: https://chromium-review.googlesource.com/169050 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Tested-by: Daisuke Nojiri <dnojiri@google.com>
* Let AP read sensor IDs when DPTF thermal thresholds crossedBill Richardson2013-12-164-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spec does not mandate any way to read back the threshold settings themselves, but when a threshold is crossed the AP needs a way to determine which sensor(s) are responsible. Each reading of the EC_ACPI_MEM_TEMP_ID register clears and returns one sensor ID that has crossed one of its thresholds (in either direction) since the last read. A value of 0xFF means "no new thresholds have tripped". Changing or enabling the thresholds for any sensor will clear the unread event count for that sensor. BUG=chrome-os-partner:23970 BRANCH=none TEST=manual On the host, set a couple of thresholds to low values so they trip immediately (I'm testing on Link): # dptf() { [ "$#" -eq "2" ] || return; iotools io_write8 0x66 0x81 iotools io_write8 0x62 $1 iotools io_write8 0x62 $2 } # # dptf 5 0 # dptf 6 10 # dptf 7 3 # dptf 5 2 # dptf 6 10 # dptf 7 2 On the EC console, see that two thresholds have triggered, and that there are two bits set in the AP seen mask: [45.755365 DPTF sensor 0, threshold -63 C, index 1, enabled] [45.768940 DPTF sensor 2, threshold -63 C, index 0, enabled] [46.169490 DPTF over threshold [0][1] [46.169820 DPTF over threshold [2][0] > dptftemp sensor thresh0 thresh1 0 --- 210* I2C-USB C-Die 1 --- --- I2C-USB C-Object 2 210* --- I2C-PCH D-Die 3 --- --- I2C-PCH D-Object 4 --- --- I2C-Hinge C-Die 5 --- --- I2C-Hinge C-Object 6 --- --- I2C-Charger D-Die 7 --- --- I2C-Charger D-Object 8 --- --- ECInternal 9 --- --- PECI AP seen mask: 0x00000005 > Read the EC_ACPI_MEM_TEMP_ID register from the host, to get the two active sensor IDs (0 and 2), then 0xff when those are seen. # iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62 0x00 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62 0x02 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62 0xff # iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62 0xff # Change-Id: I8f047a517357617f18ad59d21fa13409bc81821b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180224 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rambi: Invert SOC_OVERRIDE signalRandall Spangler2013-12-162-2/+2
| | | | | | | | | | | | | | | | SOC_OVERRIDE now drives a FET, so the signal is inverted (high=active, not low). EC must drive it push-pull because there is no pullup/pulldown on the input to the FET. BUG=chrome-os-partner:24118 BRANCH=none TEST='gpioget' shows signal is 0 by default, not 1. Change-Id: I8a86587c7fad8bf5a583cd3976bd6ed3069f2975 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180287 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* rambi: Add duplicate GPIO outputs for proto 2.0 boardRandall Spangler2013-12-164-0/+42
| | | | | | | | | | | | | | | | | | | Proto 2.0 makes these changes: KBD_IRQ# moves from PM4 to PM3. EC_PWROK moves from PH2 to PJ1. Since PM3 and PJ1 are unused on proto 1.5, it's harmless to duplicate the current functionality on those outputs. We can remove the old outputs when we deprecate the 1.5 boards. BUG=chrome-os-partner:24424 BRANCH=none TEST=boot rambi Change-Id: Iff77651ef575a8405878fe75f025a0507b02b771 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180081 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Rename mixed-case config constantsRandall Spangler2013-12-1617-61/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: ACPI and host event supportVic (Chun-Ju) Yang2013-12-143-6/+163
| | | | | | | | | | | | | | | | | This wires 0x62/0x66 to ACPI module and also implements the host event functions. BUG=chrome-os-partner:24107 TEST=ACPI memory test and compliment memory test. TEST=Set SCI mask and host event to trigger SCI. Check SCI pin pulse low. TEST=Query host event from ACPI. BRANCH=None Change-Id: Ib1f557e995a861c92a603491229ad361e17d2129 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179942 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: propagate EC reset to the AP reset for old boards.Louis Yung-Chieh Lo2013-12-143-0/+18
| | | | | | | | | | | | | | | New boards (rev >= 2.2) are not affected since chipset_force_shutdown() is called. On old boards the power rails of old boards are not removed completely. This CL ensures the AP is warm-reset after EC is reset. BUG=None BRANCH=nyan TEST=nVidia verified on old boards. Change-Id: Ia2c2b243534d8a73b9b4d5320aad4664b1ac8b12 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179521 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix uppercased macrosRandall Spangler2013-12-132-17/+19
| | | | | | | | | | | | | | | | | | | | | | The macros must be defined prior to evaluating config.h, since test_config.h needs them. Also define an uppercase version of the PROJECT variable, so that we define TEST_FOO in addition to TEST_foo. BUG=chromium:322144 BRANCH=none (but might need it if you later cherry-pick something with an uppercase #ifdef BOARD_FOO TEST=Build each board with V=1 option: 'make V=1 BOARD=foo all tests'. Check that the compile command line has both mixed-case and uppercase defines. Check that per-board tests from test/build.mk were built (for example, BOARD_PIT should compile kb_scan and stress, and BOARD_SAMUS should build none of them). Change-Id: I029552cfdf90a4191cf7a61cdcc65fe75d3ca86c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179902 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Implement DPTF thermal thresholdsBill Richardson2013-12-133-3/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any of the EC's temp sensors can have up to two independent thresholds attached to them. When the temperature crosses the threshold (rising or falling), a EC_HOST_EVENT_THERMAL_THRESHOLD event is sent to the AP. It's up to the AP to read the sensor values and figure out why the event was sent. The thresholds are set and enabled with ACPI writes to three registers in the EC interface space: EC_ACPI_MEM_TEMP_ID, EC_ACPI_MEM_TEMP_THRESHOLD, and EC_ACPI_MEM_TEMP_COMMIT. Refer to the comments in ec_commands.h for details on their use. ACPI does not provide any means to read the threshold settings (the AP will just have to remember), but there is an EC console command "dptftemp", that can be used to examine the current settings. BUG=chrome-os-partner:23970 BRANCH=none TEST=manual On the EC console, check the current threshold settings and temperatures: > dptftemp sensor thresh0 thresh1 0 --- --- PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die 3 --- --- I2C-Charger-Object 4 --- --- I2C-CPU-Die 5 --- --- I2C-CPU-Object 6 --- --- I2C-Left C-Die 7 --- --- I2C-Left C-Object 8 --- --- I2C-Right C-Die 9 --- --- I2C-Right C-Object 10 --- --- I2C-Right D-Die 11 --- --- I2C-Right D-Object 12 --- --- I2C-Left D-Die 13 --- --- I2C-Left D-Object > > temps PECI : 318 K = 45 C ECInternal : 306 K = 33 C I2C-Charger-Die : 309 K = 36 C I2C-Charger-Object : Not calibrated I2C-CPU-Die : 309 K = 36 C I2C-CPU-Object : Not calibrated I2C-Left C-Die : 306 K = 33 C I2C-Left C-Object : Not calibrated I2C-Right C-Die : 307 K = 34 C I2C-Right C-Object : Not calibrated I2C-Right D-Die : 307 K = 34 C I2C-Right D-Object : Not calibrated I2C-Left D-Die : 306 K = 33 C I2C-Left D-Object : Not calibrated > In this case, the PECI temp is 318 K, so let's set a threshold at 322 K. On the AP: [ "$#" -eq "2" ] || return; iotools io_write8 0x66 0x81 iotools io_write8 0x62 $1 iotools io_write8 0x62 $2 } Back on the EC console, we see that the threshold has been set: [768.176648 DPTF sensor 0, threshold 49 C, index 1, enabled] > dptftemp sensor thresh0 thresh1 0 --- 322 PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Now do something on the AP to increase the temperature (webgl aquarium, etc). When the temp goes above 322 K, the EC console reports it and sends a host event, and the "dptftemp" command indicates the over-temp condition: [815.367442 DPTF over threshold [0][1] [815.367878 event set 0x00000100] [815.368069 sci 0x00000100] [815.368619 event clear 0x00000100] > dptftemp sensor thresh0 thresh1 0 --- 322* PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Log out and wait for the temp to drop. You'll see that trigger a host event as well: [854.375713 DPTF under threshold [0][1] [854.376147 event set 0x00000100] [[854.376396 event clear 0x00000100] > dptftemp sensor thresh0 thresh1 0 --- 322 PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Change-Id: I6bb34c615f37477ccf37163caaa94737baed8dae Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179962 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: bring back set_ap_reset() for old boards.Louis Yung-Chieh Lo2013-12-131-1/+22
| | | | | | | | | | | | | | | | | | Since some folks are still using old boards (rev <= 2.0), bring this back so that they can reset system gracefully. BUG=None BRANCH=nyan TEST=tested on rev 2.0 reboot // EC and AP are rebooted reset button on board // EC and AP are reset power off // AP (rev 2.0) is expected NOT powered off. power on Change-Id: I35dbc5648b092c892dc06ce5676e1e68c695d477 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179851 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: keyboard scan supportVic (Chun-Ju) Yang2013-12-135-0/+91
| | | | | | | | | | | | | | | | | | | | | This adds keyboard scan module driver. Keyboard scan task is not enabled yet as the LPC layer is not finished and thus i8042 protocol cannot be enabled. Since KSO00-KSO03 are used as JTAG, we use KSO04-KSO16 so as to preserve JTAG functionality. Unfortunately we don't have enough KSO pins, so trace debug port must be disabled, as done in this CL. BUG=chrome-os-partner:24107 TEST=Set 'ksstate on'. Short KSI pins and KSO pins, and see corresponding key shown as pressed. TEST=Check keypress is detected when console shows 'KB wait'. BRANCH=None Change-Id: I366a27453ef95030d251e525313eb4627eb4340f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add stubs for DPTF thermal thresholdsBill Richardson2013-12-134-20/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds three new registers to the ACPI->EC interface, which will allow the AP to set/clear two DPTF thermal threshold points for each temp sensor. The registers are EC_ACPI_MEM_TEMP_ID 0x05 EC_ACPI_MEM_TEMP_THRESHOLD 0x06 EC_ACPI_MEM_TEMP_COMMIT 0x07 It doesn't actually do anything yet, but the AP can now write those values. BUG=chrome-os-partner:23970 BRANCH=none TEST=manual On the host: dptf() { [ "$#" -eq "2" ] || return; iotools io_write8 0x66 0x81 iotools io_write8 0x62 $1 iotools io_write8 0x62 $2 } Now watch the EC console while running on the host: dptf 5 1 dptf 6 80 dptf 7 2 dptf 7 3 The EC should say DPTF sensor 1, threshold 7 C, index 0, enabled DPTF sensor 1, threshold 7 C, index 1, enabled Change-Id: I71fa57e3ca7c7b5bb8892e63212bf294b44dece5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179778 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Change PECI_TJMAX to a board config optionChromeOS Developer2013-12-136-13/+17
| | | | | | | | | | | | | BUG=chrome-os-partner:24455 BRANCH=none TEST=Manual: Verify that CONIFG_PECI_TJMAX set per-board matches the value queried over the PECI bus with the restricted "peciprobe" command. Change-Id: I8e99a23a66f26d6101e01cc751d0a8ca79686321 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179682 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Changed timer module to expire timers on deadline matchAlec Berg2013-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | Modified the commond timer module to expire timers as soon as time matches the deadline instead of only after the deadline is passed. BRANCH=none BUG=chrome-os-partner:24490 TEST=On a peppy: - Run EC tests on host. - Run all EC tests on the target. - Keep the system on for days and occasionally verify that system is up and the keyboard is working. On a spring: - Run all EC tests on the target. Change-Id: Ieabfb769cf22ff8b04ca6d0a306312b90ea20ff3 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179460 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Move ACPI stuff out of chip/lm4 and into commonBill Richardson2013-12-126-106/+190
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The port 62/66 ACPI commands were implemented in chip/lm4/lpc.c. They should be handled in common instead of being tied to a particular EC. BUG=chrome-os-partner:23774 BRANCH=none TEST=manual read EC_ACPI_MEM_VERSION # iotools io_write8 0x66 0x80; iotools io_write8 0x62 0; iotools io_read8 0x62 0x01 write & read EC_ACPI_MEM_TEST # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x5a # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x44 read & write EC_ACPI_MEM_KEYBOARD_BACKLIGHT # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 100 (keyboard lights up) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 50 (keyboard dimmer) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 0 (keyboard goes dark) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x00 read & write EC_ACPI_MEM_FAN_DUTY # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 100 (fan on full) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 50 (fan on half speed) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0 (fan off) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x00 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0xff (fan back to EC control) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0xff test EC_CMD_ACPI_QUERY_EVENT # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 On EC console: > hostevent set 0x0f000000 # ectool eventget Current host events: 0x0f000000 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x19 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1a # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1b # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1c # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 # ectool eventget Current host events: 0x00000000 Change-Id: I011a5a2051171ec1d37e55ce03e1ce74b93a7e14 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179692
* nyan: pull up AP_RESET_L for old boardsstabilize-5085.BLouis Yung-Chieh Lo2013-12-111-1/+1
| | | | | | | | | | | | | | | On older boards (< Rev2.2), AP_RESET_L was connecting to PMIC reset pin. However, after 2.2 we use the PMIC_THERM pin instead. Thus, change this pin to pull high for old boards. T\Otherwise cannot boot up. BUG=None BRANCH=nyan TEST=verified on old board by nvidia. Change-Id: If4dccaf0bd0671c55b0d703d4d4b16a2b9c4f543 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179377 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: re-factor power button to use common/power_button.cLouis Yung-Chieh Lo2013-12-113-22/+36
| | | | | | | | | | | | | | | | | | | | | | This is the first step of tegra power state re-factoring. Move the power button logic to common/power_button.c. Also, the GPIO KB_PWR_ON_L is renamed to POWER_BUTTON_L. BUG=None BRANCH=nyan TEST=tested on nyan rev 3.12, reboot: PASS, power on 2 power off / power on: PASS, power on 5 lid close / power off / lid open: PASS, power on 3 button on / off: PASS, ending loop 3, power on 4 power off / button on: PASS, ending loop 4, power on 4 button off / power on: PASS, ending loop 3, power on 5 button off / lid open: PASS, ending loop 3, power on 3 Change-Id: If07806b9c11cdba2b478a9a74d2b75be1d9f7acf Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179451
* nds32: WORKAROUND for toolchain bug on rodataVincent Palatin2013-12-104-4/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the toolchain tries to put a relocation which is not suitable to access variables in a read-only section. The nds32 gcc uses GP-relative signed 17-bit relocation to access variables stored in .rodata (eg lwi.gp $r0, [ +gp ]) That's wrong since $gp is pointing in the middle of .data and .bss in the SRAM, while .rodata is sitting in flash. Since on IT8380, the flash is at 0x00000 and the SRAM is at 0x80000 (512kB further), the linker will fail trying to create the signed 17-bit relocation (it detect that it needs to truncate it) Force the compiler to put another relocation as a workaround for now. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24378 TEST=./util/make_all.sh ; make BOARD=it8380dev check "version" and "gpioget" on spring, link and it8380dev. Change-Id: Ife50adf3a26be28f113292f73a1a70e8d74b5d8c Reviewed-on: https://chromium-review.googlesource.com/176913 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ite: Port OS layer to Andestar v3m architectureVincent Palatin2013-12-1013-0/+1320
| | | | | | | | | | | | | | | | | This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Remove unneeded TODO commentVic (Chun-Ju) Yang2013-12-101-5/+0
| | | | | | | | | | | | | | | | | | | | | When we are detecting Apple charger type, we disable TSU6721 interrupt. This, however, doesn't create a race condition, because any pending interrupt fires immediately after we re-enable TSU6721 interrupt, and in turns schedules charger task. As a result, charger task gets waken right after it finishes its current iteration. As for overcurrent detection, the current algorithm seems to do a good enough job. BUG=chrome-os-partner:23743, chrome-os-partner:23744 TEST=None BRANCH=None Change-Id: Ib3a6d562a305020ef5413e2a493e4163a6e70954 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179303 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* keyboard: Improve kbpress reliability for automationDoug Anderson2013-12-102-8/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "kbpress" command had a few issues if you wanted to reliably use it for automation. Specifically it was not possible to guarantee how much time would pass between the press of a key and the release of a key. Sometimes you might press and release before the key was officially "there" and sometimes you might get a press and hold of a key. Fix this: 1. Make it so that kbpress with no press/release parameter gives a press and release (and guarantees that the press / release will actually take effect). 2. Make it so that kbpress guarantees that when it finishes that the key has actually been pressed or released. BRANCH=pit BUG=chrome-os-partner:24249 TEST=kbtype is (https://chromium-review.googlesource.com/178680) reliable TEST=make -j32 BOARD=bds tests && make BOARD=bds runtests TEST=Pick Ibe00a796bde7d06416889b621359671a2f68e162 and test. Change-Id: Ia213ab2e8d8da273e3ac4876d97d5452df88f47d Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 247650ecc90385417f5dcb2d60bb6ae1e5cfa32f) Reviewed-on: https://chromium-review.googlesource.com/179325 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix bug in Samus DPTF fan controlBill Richardson2013-12-101-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It worked on Link because the fan number and the fan channel were both 0. Samus has two fans, connected to different GPIOs. In the EC's ACPI interface block, register 0x04 is used to get and set the fan's target duty cycle, as a percentage value. Writing a 0 to this register will set the target duty cycle to 0, writing a 100 (0x64) will set it to 100%. Writing any other value will return the fan control to the EC, rather than driving it manually from the host. Likewise, reading from this register returns the current fan target duty cycle, as a percentage. If the EC is controlling the fan automatically, the returned value will be 0xFF. BUG=chrome-os-partner:23972 BRANCH=samus TEST=manual You can monitor the fan state from the EC console with the "faninfo" command. From the host side, test this interface from a root shell. Read fan duty: iotools io_write8 0x66 0x80 iotools io_write8 0x62 4 iotools io_read8 0x62 Set fan duty to 100%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 100 Set fan duty to 50%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 50 Set fan duty to 0%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 0 Set fan control back to automatic: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 -1 Change-Id: I3a133b0b16e2a5e1ce04b16cb2bf035a04a83daf Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179373 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Fix potential false over-temperature on entry to S0Alec Berg2013-12-091-1/+9
| | | | | | | | | | | | | | | | | | | This fixes a rare problem in which the EC could shutdown due to a false over-temperature when entering S0 on Haswell architectures. The fix involves requiring two valid reads of the temperature sensor (out of the last 4 readings) in order to report it. BUG=chrome-os-partner:24204 BRANCH=none TEST=See bug report for a patch that recreates the bug at a significantly higher rate then it would occur on its own. Using that patch, I implemented this fix, and made sure that there were no false over-temperatures reported. Change-Id: I0454eca1b96fd2fa1833b080026ed8f1caeeddc4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177963 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add uppercase defined constants for BOARD_, CHIP_, etc.Randall Spangler2013-12-093-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, per-board defines use mixed case (BOARD_pit). This causes the presubmit script to complain because that's a style violation. Using --no-verify to bypass that also allows other style violations to creep in. This change adds uppercase variants (BOARD_PIT). It also adds a CORE_ define with '-' changed to '_', since CORE_cortex-m isn't a valid symbol but CORE_CORTEX_M is (so now we can #ifdef CORE_CORTEX_M). This does not remove the old mixed-case defines yet, nor does it find/replace them in the C source files. This is intentional, so this change can be cherry-picked into branches without needing to change files in the branch that may have picked up new #ifdefs. I will rename the constants in the C source files and remove the old mixed-case defines in a follow-on CL, which should not need to get picked into existing branches. BUG=chromium:322144 BRANCH=none (but might need it if you later cherry-pick something with an uppercase #ifdef BOARD_FOO TEST=Build each board with V=1 option: 'make V=1 BOARD=foo all tests'. Check that the compile command line has both mixed-case and uppercase defines. Check that per-board tests from test/build.mk were built (for example, BOARD_PIT should compile kb_scan and stress, and BOARD_SAMUS should build none of them). Change-Id: I5eb0d1fe57f1c694d7449e5f148e2f13fb290a39 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179205 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up g781 temp sensor function namesChromeOS Developer2013-12-091-35/+35
| | | | | | | | | | | | | | | BUG=None BRANCH=None TEST=Manual. Run the following console commands: g781 - verify temps and status look sane. temps - verify local and remote values for the 781 are listed g781 settemp 0x05 80 - verify local high alarm set to 80C g781 setbyte 0x09 0x80 - verify config register is 1000 0000 Change-Id: Ia437647fd052295dfd8901c2ef241ff69c0d950e Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179152 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add lightbar calibration for samusBill Richardson2013-12-071-0/+22
| | | | | | | | | | | | | | | | | The samus lightbar uses different LEDs from Link. Adjust the per-color current limits accordingly. Also swizzle the layout, since LEDs 0/1 and 2/3 are swapped. BUG=chrome-os-partner:24405 BRANCH=samus TEST=manual The colors were ugly and weird. Now they should be pretty and Googley. Change-Id: I19f317243ff46852628b8b28f2bf6f5e02c6e631 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179160 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Rambi: Switch from g781 to tmp432 temperature sensorChromeOS Developer2013-12-072-10/+13
| | | | | | | | | | | BUG=chrome-os-partner:23985 BRANCH=rambi TEST=Run 'tmp432' and 'temps' command on EC console. Signed-off-by: Dave Parker <dparker@chromium.org> Change-Id: I0f246c82ea5f9d5d153b7dc57f7371ea931d6189 Reviewed-on: https://chromium-review.googlesource.com/178689 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Basic driver for tmp432 temperature sensorChromeOS Developer2013-12-074-0/+315
| | | | | | | | | | | | | | | | | | | | | This allows local and remote temp values to be added to a board's list of temp sensors. It also adds a 'tmp432' EC console command to query temps and set alert thresholds. Fractional degrees are not supported. DPTF support is not addressed. BUG=chrome-os-partner:23985 BRANCH=none TEST=Add tmp432 support to a board with the sensor then run the 'tmp432' and 'temps' EC console commands. Signed-off-by: Dave Parker <dparker@chromium.org> Change-Id: Ifee47cf4d4cf5eedef9ef2bfa2149f183f1d7a7b Reviewed-on: https://chromium-review.googlesource.com/178688 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> Tested-by: Dave Parker <dparker@chromium.org>
* mec1322: I2C driverVic (Chun-Ju) Yang2013-12-065-3/+388
| | | | | | | | | | | | | | | | | | This adds the driver for MEC1322 I2C controller. BUG=chrome-os-partner:24107 TEST=Hook up TSU6721 to eval board. Do the following tests: - 'i2cscan' and see TSU6721. - Read device ID register and get correct value. - Add 3 tasks randomly doing I2C read and writes. Check there is no error. BRANCH=None Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178591 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* extract common core codeVincent Palatin2013-12-059-197/+255
| | | | | | | | | | | | | | | | | | | | | | Move the non-core dependent code out of core/$(CORE) directory to common/ directory. Put all panic printing code in common/panic_output.c Put timer management code in common/timer.c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=./util/make_all.sh use "crash divzero" and "panicinfo" on Link. Change-Id: Ia4e1ebc74cd53da55fe24f69e96f39f512b9336d Reviewed-on: https://chromium-review.googlesource.com/178871 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Disable EC jump after RW image startsstabilize-5062.BDaisuke Nojiri2013-12-051-8/+13
| | | | | | | | | | | | | | | | | | Remove jumped_to_image check in system_run_image_copy because it's redundant. disable_jump will be set by VbExEcDisableJump explicitly, whether the EC stays in RO or jumps to RW. TEST=Built and booted Peppy. Ran flashrom from user space and verified the EC firmware was updated after reboot. BRANCH=none BUG=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: If1a3cf6158b3bc97c965298d2ab958b5fa7a5d7e Reviewed-on: https://chromium-review.googlesource.com/172651 Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Tested-by: Daisuke Nojiri <dnojiri@google.com>
* nyan: force shutdown uses PMIC THERM instead.Louis Yung-Chieh Lo2013-12-053-22/+47
| | | | | | | | | | | | | | | | | | | Add a new pin PMIC_THERM_L (PA1) since AP_RESET_L (PA15) is removed. To force shutdown, drive PMIC_THERM_L to low (default high) for 32us. Also rename set_pmic_pwrok() -> set_pmic_pwron(). And add a debounce time for PMIC_PWRON_L pin. BUG=chrome-os-partner:24206 BRANCH=nyan TEST=Verified on the frank's rework board. 'power off' shutdowns the AP immediately. 'reboot' reboots the EC and resets the AP as well. 'sysjump RW' still keeps AP alive. Change-Id: I8643e19081a824e1f6adc812dfad0269222db8ea Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178631
* mec1322: Fan control driverVic (Chun-Ju) Yang2013-12-045-0/+194
| | | | | | | | | | | | | | | | | | | | This adds the driver for PWM duty cycle based and RPM based fan control. BUG=chrome-os-partner:24107 TEST='fanset 5000' and fan spins up. 'fanset 8000' and fan spins faster. 'fanset 0' and fan stops. 'fanduty 30' and fan spins up. 'fanduty 50' and fan spins faster. 'fanduty 30' and fan slows down. 'fanset 6000' and fan goes to ~6000 RPM. Unplug fan power and see 'fan 0 stalled'. Plug power back and doesn't see stall warning anymore. BRANCH=None Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178402
* mec1322: temporary hack for using EMI moduleVic (Chun-Ju) Yang2013-12-042-1/+352
| | | | | | | | | | | | | | | | | | We are using EMI module instead of LPC memory transaction. This requires a different protocol for accessing mapped memory from host. For easier development, let's add a new comm-mec1322.c until we can switch back to LPC memory transaction. BUG=chrome-os-partner:24280 TEST=ectool version TEST=util/make_all.sh BRANCH=None Change-Id: Id8914d0413561991d3e46bef7e3fe76c4f8b83e4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178251 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-046-2/+179
| | | | | | | | | | | | | | | | | | | With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nyan: add support of different battery typesYen Lin2013-12-042-43/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan EC supports 2 different boards: Venice2 and Norrin. Venice2 uses 2S battery, and Norrin uses 3S battery. This CL is to support 2 different battery types (2S or 3S) automatically at init time by reading battery's MANUF_NAME, DEVICE_NAME and DESIGN_VOLTAGE from Smart Battery Interface to determine which battery type to use. To workaround the problem that battery may not be attached at init time, a patch is added to call battery_get_info() in PWR_STATE_INIT state to get the current battery info. Note the battery info is only determined once. BUG=none BRANCH=nyan TEST=tested on Vencie2 with 2S battery and on Norrin with 3S battery attached at init time and made sure correct battery info are installed; tested on Venice2 and Norrin without battery at init time, then attached 2S or 3S battery and made sure correct battery info are installed. Change-Id: I135909c7fe1e1dfdb0f706e0eadba6e904b6221e Signed-off-by: Yen Lin <yelin@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/178088 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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