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* Clear OWNERS for factory/firmware branchfactory-2268.16.BBrian Norris2021-09-101-0/+1
| | | | | | | | | | | | BUG=none TEST=none Change-Id: I0f03f432ada1064ffba9595be78ca7ab4d25ecd1 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3154574 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Owners-Override: Jora Jacobi <jora@google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org>
* Drop DPWROK when system is off for more than 10 secrelease-R20-2268.BRandall Spangler2012-05-096-94/+201
| | | | | | | | | | | | | | | | | | | | | | | | | | This saves ~70mw of power. To make this work, I also had to stretch the power button signal to give the system a chance to come back up when the user taps the power button. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9574 TEST=manual For each of the following tests, wait ~15 sec after the system is powered off to give it a chance to drop DPWROK. 1) tap power button -> system turns on 2) hold power button 1 sec -> system turns on 3) open lid -> system turns on 4) silego reset (power+refresh, or power+esc on proto1) -> system stays off 5) silego recovery (power+esc+refresh) -> system turns on 6) hold down power button and type 'reboot' on EC console -> system turns on 7) type 'powerbtn' on EC console -> system turns on Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
* Add hooks for chipset power transitionsRandall Spangler2012-05-0910-53/+134
| | | | | | | | | | | | This is cleaner than having x86_power explicitly know about everything else in the system that cares about power transitions. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=boot and shutdown system; still works. Mouse powered to system is off in S5. Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
* Fix polarity of radio-disable GPIOsRandall Spangler2012-05-093-4/+8
| | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8932 TEST=manual 1) gpioget with system off -> ENABLE_WLAN = 0, RADIO_ENABLE_* = 0 2) gpioget with system on -> ENABLE_WLAN = 1, RADIO_ENABLE_* = 1 Change-Id: I397a195b4539083c622b85d63703c334cae931fb
* stm32: set default i2c mode to noopDavid Hendricks2012-05-091-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | This CL initializes the default transmit mode for I2C to CMDC_NOP. When we introduced the protocol, we changed the default mode to send message protocol version. This didn't take into account that U-Boot's probe command (and probably other userspace commands) do a single-byte read to probe. So when the probe was asking for a single byte, by default we were sending multiple bytes for the version message. This CL also makes the EC reset the mode to noop after each EC-to-AP transmission. This will help ensure that the EC ends up in a known state e.g. if the system is reset. That will require the AP to set the mode before requesting any real data, but that's how we do things now anyway. BUG=chrome-os-partner:9556 TEST=Tested on Daisy. Tested by running "i2c dev 4; i2c probe" at U-Boot prompt, booting system, and typing on keyboard. Everything seems to work okay. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I0849c94588a9a60ade657af8f941f7267553e316
* Merge "stm32: add flash programming support"Gerrit2012-05-096-4/+305
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| * stm32: add flash programming supportVincent Palatin2012-05-096-4/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements the on-chip flash erasing and writing functions. The actual writing is done from a routine in internal RAM (using the special .iram.text section) with interrupt disabled as we cannot read flash during the writing process. The write-protect feature is only lightly tested. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8865 TEST=run on Daisy, from the EC console, use flasherase and flashwrite commands and observe the results using rw command. Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
* | Make CPU_PROCHOTn high-Z (input) unless we're driving it low.Randall Spangler2012-05-082-2/+4
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9563 TEST=manual Measure +3VALW power before and after change with system in S5. Should drop by ~50mW. Change-Id: I264694a80b2e558e46708de6ab1bfb146f79eb68
* | Change recovery key to ESC on EVT systemsRandall Spangler2012-05-081-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9554 TEST=manual 1) Boot system. No recovery. 2) Boot system holding down Refresh+Esc. No recovery. 3) Hold down Power+Esc. System reboots and stays shut down. 4) Hold down Power+Esc+Refresh. System reboots into recovery mode. Change-Id: I53db224b6d2a03406244e79fb64fb67851919857
* | Add gpio_set_flags() and system_get_board_version()Randall Spangler2012-05-086-37/+113
| | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=version; board version should be 0 on proto1 and 1 on EVT Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
* | Merge "Automatically switch USB charging mode"Gerrit2012-05-083-4/+35
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| * | Automatically switch USB charging modeVic Yang2012-05-093-4/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable USB ports when system is down and set USB ports to standard downstream mode when system is up or sleeping. Signed-off-by: Vic Yang <victoryang@google.com> BUG=chrome-os-partner:9249 TEST=Plug in a phone and see it charge when system is on. Turn off the system and see it stop charging. Change-Id: I02850dee7051ed6589e0f176a933069203f0efdf
* | | stm32: Fix an off-by-one error in select_column()David Hendricks2012-05-081-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes an off-by-one error that was preventing two keys (left and right arrow) on output 12 from being driven properly, and causing some other weird ghosting effects. BUG=chrome-os-partner:9516 TEST=Tested on Daisy Pressing the right arrow shows this at the EC console: [1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 40] and pressing the left arrow shows this at the EC console: [1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 80] Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib7af21444c2d03a0787fb1a28b520a779013774d
* | Merge "Move gpio list into gpio.h header file"Gerrit2012-05-086-16/+3
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| * | Move gpio list into gpio.h header fileSimon Glass2012-05-086-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is referenced by various files, so should be in the gpio.h header. BUG=none TEST=manual: build and boot on daisy, see that USB download still works build on all platforms Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4 Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Add LPC lightbar command to get the current sequence.Bill Richardson2012-05-085-54/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of making the STOP command synchronous, we can just have the host-side app tell the EC to stop, then poll until it has. BUG=chrome-os-partner:9349 TEST=manual "make BOARD=link", then copy build/link/util/lbplay to the host and run it. Change-Id: I846924ae7994a498e0089197785cf239898fe2a3 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* | | Mark end of each RW firmware image so we can find it.Bill Richardson2012-05-081-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | This just adds a single byte to the end of the RW firmware, so that we can scan backwards from the end of the reserved block, skipping 0xff until we find the actual firmware size. We need this so we can resign existing firmware images without either signing a bunch of padding or forgetting to sign a trailing 0xff that might be important. BUG=chrome-os-partner:7459 TEST=none Change-Id: If5cadb4d58c1bce39f66815c328ffd18cc3d444b Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* | Add EC_RO/EC_RW and WP_RO FMAP area for fw_updater and factory.Louis Yung-Chieh Lo2012-05-081-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_RO and WP_RO area are identical and should cover whole range needed to be write-protected. While EC_RO is for legacy firmware updater, the WP_RO is for future factory finalize test. EC_RW is for fw_updater to update both A/B at once. Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> BUG=chrome-os-partner:9536 TEST=build in chroot and dump_fmap build/link/ec.bin opened build/link/ec.bin hit at 0x00013800 fmap_signature __FMAP__ fmap_version: 1.0 fmap_base: 0x0 fmap_size: 0x0003f800 (260096) fmap_name: EC_FMAP fmap_nareas: 16 area: 1 area_offset: 0x00000000 area_size: 0x00014000 (81920) area_name: RO_SECTION area: 2 area_offset: 0x00000000 area_size: 0x00013000 (77824) area_name: BOOT_STUB area: 5 area_offset: 0x00013800 area_size: 0x00000302 (770) area_name: FMAP area: 7 <---- area_offset: 0x00000000 <---- area_size: 0x00014000 (81920) <---- area_name: EC_RO <---- area: 8 <---- area_offset: 0x00014000 <---- area_size: 0x00028000 (163840) <---- area_name: EC_RW <---- area: 9 <---- area_offset: 0x00000000 <---- area_size: 0x00014000 (81920) <---- area_name: WP_RO <---- area: 10 area_offset: 0x00014000 area_size: 0x00014000 (81920) area_name: RW_SECTION_A area: 14 area_offset: 0x00028000 area_size: 0x00014000 (81920) area_name: RW_SECTION_B Change-Id: I11b9450f87e26ef1cd0ac65ecd059e13d8489e26
* | Add GPIO for PCH SRTCRST#Randall Spangler2012-05-072-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | In case ctl decides to put it on a separate GPIO, he'll use PC7. If he doesn't, we can reclaim this GPIO. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7576 TEST=gpioget; signals should be present. PCH_SRTCRSTn should be 1. Change-Id: I4ca4437515d62c36d00fd28093ca41e806ce351a
* | Clean up sysjump struct parsing and add memmove()Randall Spangler2012-05-074-41/+51
| | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9447 TEST=update from old EC 517 to this one Change-Id: I275b5bf6c4ae1ab6e0c0a05cf9260314d644c79b
* | Add GPIOs for WLAN power control and PCH RTCRST#Randall Spangler2012-05-073-0/+16
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7576 TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1. Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
* Add GPIOs for EVT board version stuffing resistorsRandall Spangler2012-05-072-2/+8
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=gpioget; signals should be present Change-Id: I27473d4d4e0a0b2832ffe3b3dde7cd487367390e
* Merge "Initial Snow board port"Gerrit2012-05-057-8/+227
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| * Initial Snow board portDavid Hendricks2012-05-047-8/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mostly stolen from Daisy. Notable differences: - No SYSCFGEN required for external interrupts ? - No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available --> CODEC_INT and ENTERING_RW signals are missing BUG=None TEST=Tested on ADV2/Snow, able to see EC serialconsole Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
* | Merge "stm32f: Fix clock_init"Gerrit2012-05-041-2/+2
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| * stm32f: Fix clock_initDavid Hendricks2012-05-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | 0b00 for bits 1:0 (system clock switch) indicates HSI, 0b01 indicates HSE. Also, bit 23 is reserved (maybe it was just a copying error from earlier). BUG=None TEST=Compiled and run on Snow Change-Id: Ie6891492ae6e7e3bd30e4d7b183b156de1290fe0 Signed-off-by: David Hendricks <dhendrix@chromium.org>
* | Merge "daisy: fix a bug in the GPIO enum listing"Gerrit2012-05-041-2/+0
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| * | daisy: fix a bug in the GPIO enum listingDavid Hendricks2012-05-041-2/+0
| |/ | | | | | | | | | | | | | | | | | | | | These GPIOs should have been removed in fd5d6c. BUG=Yes. TEST=built a new image and booted Daisy-EVT1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Idce4384cdbe548c2e4fe2be8b52e4275445c9f1b
* | Update EC config and FMAP to reserve room for vboot signaturesBill Richardson2012-05-045-41/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | This just reserves room. It doesn't actually perform any verification yet. BUG=chrome-os-partner:7459 TEST=manual make BOARD=link dump_fmap build/link/ec.bin Change-Id: I424db1d601a614be3dfe5abb200e24e8bc62e47e Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* | Merge "Add link helper procedure"Gerrit2012-05-041-0/+6
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| * Add link helper procedureVadim Bendebury2012-05-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Jim procedure to program the Link EC image from the default location as generated by 'emerge-link chromeos-ec'. BUG=none TEST=manual . emerge-link chromeos-ec . start openocd as described in the Link care and feeding document . in the port 4444 terminal session type flash_emerged_link . observe it succeed Change-Id: Ibfbc38060d7e82ec8c83a73e2ccadff81d633ae4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
* | Implement new write protect for host commands.Louis Yung-Chieh Lo2012-05-041-31/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework to call functions in flash_common.c. Also fixed a bug in parsing size of parse_offset_size(). Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> BUG=chrome-os-partner:8448 TEST=on link (CONSOLE) flashwp set 0x3d000 0x1000 (CONSOLE) flashwp lock (HOST) flashrom -p internal:bus=lpc --wp-status WP: write protect is enabled WP: write protect range: start=0x0003d000, len=0x00001000 Change-Id: I4a53735c851ebf4bb0c01a55a1d301d5b706ee0c
* | Merge "Assert PROCHOT when overheated and lower fan control threshold"Gerrit2012-05-041-5/+12
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| * | Assert PROCHOT when overheated and lower fan control thresholdVic Yang2012-05-031-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to assert PROCHOT signal at/before 68 degree-C. Let's assert it when CPU is at 68 degree-C. Also, we lower fan speed control threshold to max fan speed at 65 degree-C. Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=chrome-os-partner:8982 TEST=none Change-Id: Iec0d05308b1310f89bc0a2edb1ad632c8ca96c87
* | | daisy: Rename power signals to indicate polaritySimon Glass2012-05-033-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO_KB_PWR_ON and GPIO_PMIC_PWRON are active low, so add _L to each name to make this clearer. BUG=chrome-os-partner:9424 TEST=very ad-hoc: 1. build and boot on daisy, flash U-Boot with USB using 'cros_bundle_firmware -w usb', inserting daisy USB cable when it says 'Reseting board via servo...' 2. Press cold reset, then power on, see that it powers on 3. Then hold power-on for 8 seconds and see that it power off 4. XPSHOLD function not tested yet Change-Id: Ibdc0064477c36e8658ef5605cdd5811c2283aff9 Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Add gpio_get_name() to return the name of a signalSimon Glass2012-05-033-0/+20
| |/ |/| | | | | | | | | | | | | | | | | | | | | Add this to the GPIO API. It seems that the implementation is copied in LM4 and STM32 so I have reluctantly done the same with this new function. BUG=chrome-os-partner:9424 TEST=build and boot on Daisy Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge "Add header_size in struct jump_data."Gerrit2012-05-031-1/+38
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| * | Add header_size in struct jump_data.Louis Yung-Chieh Lo2012-05-031-1/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The position of jump_tags was shifted every time a new field was added to struct jump_data. This broke the sysjump hook badly. To make this more scalable, add a header_size field in struct jump_data. Then the new code can always prepend (or reduce if jump_data becomes smaller) some spaces between jump_data and jump_tags. BUG=chrome-os-partner:9447 TEST=EC upgrade from EC 517 (2231) to this version, and keyboard keeps working. Note that EC 526 (2235) to this version is not working because we have no way to identify that header version change. Change-Id: If1b506c6f7d22e5affaaf8ada15990f60d2f957a
* | | daisy: Re-introduce SPI protocol supportSimon Glass2012-05-031-11/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The changes in the message protocol break SPI support, so re-introduce these, this time in the driver itself. We add the concept of an option preamble in the message, a length and a trailing byte. BUG=chrome-os-partner:9426 TEST=run U-Boot, see that keyboard works correctly now. Change-Id: I83b4af7e3745b935ffafcd9e2f521fce77e3bc6e Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge "timer: Add timestamp_expired() to check for expiry"Gerrit2012-05-032-0/+14
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| * | | timer: Add timestamp_expired() to check for expirySimon Glass2012-05-022-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than open code this each time, create a function for this. The wrap-around condition may not be needed, if the timer starts at zero, since we have 64 bits to play with. BUG=chrome-os-partner:9424 TEST=build and boot on daisy Change-Id: I84ae651212769b5927c452bc03f31f60a25a829e Signed-off-by: Simon Glass <sjg@chromium.org>
* | | | Merge "Add charger option output in interactive console"Gerrit2012-05-031-0/+6
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| * | | Add charger option output in interactive consoleRong Chang2012-05-031-0/+6
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:8982 TEST=manual run console command 'charger' charger option will be displayed in bin and hex output Change-Id: I461bce347f13eeb4f2c8595b83a7ba4c7d40ea58
* | | Fix a bug in temperature sensor address definitionVic Yang2012-05-031-2/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | The address of charger temperature sensor and memory temperature sensor are interchanged. Fix this in this CL. Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=chrome-os-partner:9450 TEST=Manual Change-Id: I20ae4d39ef13992ca7cac32bb2e6be12e195731e
* | remove deprecated stm32-based boardsVincent Palatin2012-05-0213-352/+5
| | | | | | | | | | | | | | | | | | | | | | We no longer support ADV EVT0 board and Discovery reference design. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=daisy && make BOARD=link Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
* | Merge "daisy: EVT1 pin mapping"Gerrit2012-05-021-7/+7
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| * | daisy: EVT1 pin mappingDavid Hendricks2012-05-021-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This modifies the existing daisy's board.c to use the new pin mapping. BUG=None TEST=Tested on Daisy-EVT1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I717ce78df1ed29843d1498e979956c6ffdb05e80
* | | Merge "Make lightbar task stop dropping events."Gerrit2012-05-021-1/+1
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| * | | Make lightbar task stop dropping events.Bill Richardson2012-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:9350 TEST=none Change-Id: I5a208aeb74f34e82393a3208f4a0cd48cdc7bff4 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* | | | Merge "Enhance LPC EC REBOOT reset command to allow to request recovery"Gerrit2012-05-025-22/+55
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