diff options
Diffstat (limited to 'zephyr/program/myst/gpio.dtsi')
| -rw-r--r-- | zephyr/program/myst/gpio.dtsi | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/zephyr/program/myst/gpio.dtsi b/zephyr/program/myst/gpio.dtsi new file mode 100644 index 0000000000..4980b066f0 --- /dev/null +++ b/zephyr/program/myst/gpio.dtsi @@ -0,0 +1,52 @@ +/* Copyright 2021 The ChromiumOS Authors + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/ { + aliases { + gpio-wp = &gpio_ec_wp_l; + /* There is no CBI WP on myst... remove this ASAP */ + gpio-cbi-wp = &gpio_usb_c0_sbu_flip; + gpio-kbd-kso2 = &gpio_ec_kso_02_inv; + }; +}; + +/* PSL input pads */ +&psl_in1_gpd2 { + /* MECH_PWR_BTN_ODL */ + psl-in-mode = "edge"; + psl-in-pol = "low-falling"; +}; + +&psl_in2_gp00 { + /* ACOK_OD */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +&psl_in4_gp02 { + /* LID_OPEN */ + psl-in-mode = "edge"; + psl-in-pol = "high-rising"; +}; + +/* Power domain device controlled by PSL (Power Switch Logic) IO pads */ +&power_ctrl_psl { + status = "okay"; + pinctrl-names = "sleep"; + pinctrl-0 = <&psl_in1_gpd2 &psl_in2_gp00 &psl_in4_gp02>; +}; + +/* host interface */ +&espi0 { + status = "okay"; + pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>; + pinctrl-names = "default"; +}; + +/* Required node label that is named differently on Myst */ +gpio_ec_pch_wake_odl: &gpio_ec_soc_wake_odl {}; +gpio_slp_s0_l: &gpio_slp_s3_l { + alias = "GPIO_PCH_SLP_S0_L"; +}; |