diff options
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/clock-stm32h7.c | 12 | ||||
| -rw-r--r-- | chip/stm32/registers.h | 8 |
2 files changed, 20 insertions, 0 deletions
diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index e99ce03517..48915aca09 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -384,6 +384,18 @@ void clock_init(void) STM32_AXI_TARG_FN_MOD(7) |= READ_ISS_OVERRIDE; /* + * Lock (SCUEN=0) power configuration with the LDO enabled. + * + * The STM32H7 Reference Manual says: + * The lower byte of this register is written once after POR and shall + * be written before changing VOS level or ck_sys clock frequency. + * + * The interesting side-effect of this that while the LDO is enabled by + * default at startup, if we enter STOP mode without locking it the MCU + * seems to freeze forever. + */ + STM32_PWR_CR3 = STM32_PWR_CR3_LDOEN; + /* * Ensure the SPI is always clocked at the same frequency * by putting it on the fixed 64-Mhz HSI clock. * per_ck is clocked directly by the HSI (as per the default settings). diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index b7d62af766..37a49da00a 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -875,6 +875,14 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #ifdef CHIP_FAMILY_STM32H7 #define STM32_PWR_CR2 REG32(STM32_PWR_BASE + 0x08) #define STM32_PWR_CR3 REG32(STM32_PWR_BASE + 0x0C) +#define STM32_PWR_CR3_BYPASS (1 << 0) +#define STM32_PWR_CR3_LDOEN (1 << 1) +#define STM32_PWR_CR3_SCUEN (1 << 2) +#define STM32_PWR_CR3_VBE (1 << 8) +#define STM32_PWR_CR3_VBRS (1 << 9) +#define STM32_PWR_CR3_USB33DEN (1 << 24) +#define STM32_PWR_CR3_USBREGEN (1 << 25) +#define STM32_PWR_CR3_USB33RDY (1 << 26) #define STM32_PWR_CPUCR REG32(STM32_PWR_BASE + 0x10) #define STM32_PWR_CPUCR_PDDS_D1 (1 << 0) #define STM32_PWR_CPUCR_PDDS_D2 (1 << 1) |