diff options
Diffstat (limited to 'chip/ish/registers.h')
| -rw-r--r-- | chip/ish/registers.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index bdd04a7cb2..ba83b7bef8 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -48,6 +48,7 @@ enum ish_i2c_port { #define ISH_IOAPIC_BASE 0xFEC00000 #define ISH_HPET_BASE 0x04700000 #define ISH_LAPIC_BASE 0xFEE00000 +#define ISH_SBEP_BASE 0x04500000 #else #define ISH_I2C0_BASE 0x00100000 #define ISH_I2C1_BASE 0x00102000 @@ -128,6 +129,13 @@ enum ish_i2c_port { #define ISH_GPIO_GWSR REG32(ISH_GPIO_BASE + 0x118) /* Wake Source */ #define ISH_GPIO_GSEC REG32(ISH_GPIO_BASE + 0x130) /* Secure Input */ +#if defined(CHIP_VARIANT_ISH5P4) +/* Side Band End Point registers */ +#define SBEP_REG_CLK_GATE_ENABLE REG32(ISH_SBEP_BASE + 0x006C) +#define SB_CLK_GATE_EN_LOCAL_CLK_GATE BIT(0) +#define SB_CLK_GATE_EN_TRUNK_CLK_GATE BIT(1) +#endif + /* APIC interrupt vectors */ #define ISH_TS_VECTOR 0x20 /* Task switch vector */ #define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */ @@ -208,6 +216,7 @@ enum ish_i2c_port { #define PMU_PMC_PG_WAKE REG32(ISH_PMU_BASE + 0xF18) #define PMU_INTERNAL_PCE REG32(ISH_PMU_BASE + 0xF30) #define PMU_D3_STATUS REG32(ISH_PMU_BASE + 0x100) +#define PMU_D3_STATUS_1 REG32(ISH_PMU_BASE + 0x104) #define PMU_HOST_RST_B BIT(0) #define PMU_PCE_SHADOW_MASK 0x1F #define PMU_PCE_PG_ALLOWED BIT(4) @@ -232,6 +241,10 @@ enum ish_i2c_port { #define PMU_BME_BIT_FALLING_EDGE_STATUS BIT(26) #define PMU_BME_BIT_RISING_EDGE_MASK BIT(27) #define PMU_BME_BIT_FALLING_EDGE_MASK BIT(28) +#define PMU_REG_MASK_D3_RISE REG32(ISH_PMU_BASE + 0x200) +#define PMU_REG_MASK_D3_FALL REG32(ISH_PMU_BASE + 0x208) +#define PMU_REG_MASK_BME_RISE REG32(ISH_PMU_BASE + 0x220) +#define PMU_REG_MASK_BME_FALL REG32(ISH_PMU_BASE + 0x228) #endif #define PMU_GPIO_WAKE_MASK0 REG32(ISH_PMU_BASE + 0x250) @@ -322,6 +335,7 @@ enum ish_i2c_port { #define DEST_BURST_SIZE 3 #define PMU_MASK_EVENT REG32(ISH_PMU_BASE + 0x10) +#define PMU_MASK_EVENT2 REG32(ISH_PMU_BASE + 0x4C) #define PMU_MASK_EVENT_BIT_GPIO(pin) BIT(pin) #define PMU_MASK_EVENT_BIT_HPET BIT(16) #define PMU_MASK_EVENT_BIT_IPC BIT(17) @@ -332,6 +346,16 @@ enum ish_i2c_port { #define PMU_MASK_EVENT_BIT_SPI BIT(22) #define PMU_MASK_EVENT_BIT_UART BIT(23) #define PMU_MASK_EVENT_BIT_ALL (0xffffffff) +#define PMU_MASK_EVENT2_SRAM_ERASE1 BIT(3) +#define PMU_MASK_EVENT2_SRAM_ERASE0 BIT(4) +#define PMU_MASK_EVENT2_ISOL_ACK_RISE BIT(14) +#define PMU_MASK_EVENT2_ISOL_ACK_FALL BIT(15) +#define PMU_MASK_EVENT2_HOST_RST_RISE BIT(16) +#define PMU_MASK_EVENT2_HOST_RST_FALL BIT(17) +#define PMU_MASK2_ALL_EVENTS \ + (PMU_MASK_EVENT2_SRAM_ERASE0 | PMU_MASK_EVENT2_SRAM_ERASE1 | \ + PMU_MASK_EVENT2_ISOL_ACK_RISE | PMU_MASK_EVENT2_ISOL_ACK_FALL | \ + PMU_MASK_EVENT2_HOST_RST_RISE | PMU_MASK_EVENT2_HOST_RST_FALL) #define PMU_RF_ROM_PWR_CTRL REG32(ISH_PMU_BASE + 0x30) |