diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/bds/board.c | 76 | ||||
| -rw-r--r-- | board/bds/board.h | 129 | ||||
| -rw-r--r-- | board/bds/board_temp_sensor.c | 22 | ||||
| -rw-r--r-- | board/bds/build.mk | 13 | ||||
| -rw-r--r-- | board/bds/dummy_charger.c | 88 | ||||
| -rw-r--r-- | board/bds/ec.tasklist | 23 | ||||
| -rw-r--r-- | board/discovery/board.c | 67 | ||||
| -rw-r--r-- | board/discovery/board.h | 34 | ||||
| -rw-r--r-- | board/discovery/build.mk | 10 | ||||
| -rw-r--r-- | board/discovery/ec.tasklist | 18 | ||||
| -rw-r--r-- | board/link/board.c | 123 | ||||
| -rw-r--r-- | board/link/board.h | 170 | ||||
| -rw-r--r-- | board/link/board_temp_sensor.c | 37 | ||||
| -rw-r--r-- | board/link/build.mk | 12 | ||||
| -rw-r--r-- | board/link/ec.tasklist | 23 |
15 files changed, 845 insertions, 0 deletions
diff --git a/board/bds/board.c b/board/bds/board.c new file mode 100644 index 0000000000..2e2a1915f6 --- /dev/null +++ b/board/bds/board.c @@ -0,0 +1,76 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* Stellaris EKB-LM4F-EAC board-specific configuration */ + +#include "board.h" +#include "gpio.h" +#include "power_button.h" +#include "registers.h" +#include "util.h" +#include "lm4_adc.h" +#include "adc.h" + +/* ADC channels. Must be in the exactly same order as in enum adc_channel. */ +const struct adc_t adc_channels[ADC_CH_COUNT] = +{ + /* EC internal temperature is calculated by + * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2 + * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5 + */ + {"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420, + LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */}, + + /* Charger current is mapped from 0~4000mA to 0~1.6V. + * And ADC maps 0~3.3V to ADC_READ_MAX. + */ + {"ChargerCurrent", LM4_ADC_SEQ1, 33 * 4000, ADC_READ_MAX * 16, 0, + LM4_AIN(ADC_IN0), 0x06 /* IE0 | END0 */}, +}; + + +/* GPIO signal list. Must match order from enum gpio_signal. */ +const struct gpio_info gpio_list[GPIO_COUNT] = { + /* Inputs with interrupt handlers are first for efficiency */ + {"POWER_BUTTONn", LM4_GPIO_C, (1<<5), GPIO_PULL_UP | GPIO_INT_BOTH, + power_button_interrupt}, + {"LID_SWITCHn", LM4_GPIO_D, (1<<0), GPIO_PULL_UP | GPIO_INT_BOTH, + power_button_interrupt}, + /* Other inputs */ + /* Outputs */ + {"DEBUG_LED", LM4_GPIO_A, (1<<7), GPIO_OUT_LOW, NULL}, + /* Unimplemented signals which we need to emulate for now */ + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_LID_SWITCHn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_PWRBTNn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_BKLTEN"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_An"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_ME_CSW_DEVn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S3n"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S4n"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_S5n"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SLP_SUSn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SUSWARNn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_1_5V_DDR"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_1_5V_PCH"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_1_8VS"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_5VALW"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_CPU_CORE"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_VCCP"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_VCCSA"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PGOOD_VGFX_CORE"), + GPIO_SIGNAL_NOT_IMPLEMENTED("ENABLE_1_5V_DDR"), + GPIO_SIGNAL_NOT_IMPLEMENTED("ENABLE_BACKLIGHT"), + GPIO_SIGNAL_NOT_IMPLEMENTED("ENABLE_VCORE"), + GPIO_SIGNAL_NOT_IMPLEMENTED("ENABLE_VS"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_DPWROK"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_PWROK"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_RSMRSTn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("PCH_SUSACKn"), + GPIO_SIGNAL_NOT_IMPLEMENTED("SHUNT_1_5V_DDR"), +}; + + +void configure_board(void) +{ +} diff --git a/board/bds/board.h b/board/bds/board.h new file mode 100644 index 0000000000..e5cab1f212 --- /dev/null +++ b/board/bds/board.h @@ -0,0 +1,129 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Stellaris EKB-LM4F-EAC board configuration */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* 66.667 Mhz clock frequency */ +#define CPU_CLOCK 66666667 + +/* Fan PWM channels */ +#define FAN_CH_KBLIGHT 1 /* Keyboard backlight */ +#define FAN_CH_POWER_LED 3 /* Power adapter LED */ +#define FAN_CH_CPU 4 /* CPU fan */ + +/* TODO: these should really only be used inside lpc.c; once they are, remove + * from board header files. */ +/* LPC channels */ +#define LPC_CH_KERNEL 0 /* Kernel commands */ +#define LPC_CH_PORT80 1 /* Port 80 debug output */ +#define LPC_CH_CMD_DATA 2 /* Data for kernel/user-mode commands */ +#define LPC_CH_KEYBOARD 3 /* 8042 keyboard emulation */ +#define LPC_CH_USER 4 /* User-mode commands */ +#define LPC_CH_COMX 7 /* UART emulation */ +/* LPC pool offsets */ +#define LPC_POOL_OFFS_KERNEL 0 /* Kernel commands - 0=in, 1=out */ +#define LPC_POOL_OFFS_PORT80 4 /* Port 80 - 4=in, 5=out */ +#define LPC_POOL_OFFS_COMX 8 /* UART emulation range - 8-15 */ +#define LPC_POOL_OFFS_KEYBOARD 16 /* Keyboard - 16=in, 17=out */ +#define LPC_POOL_OFFS_USER 20 /* User commands - 20=in, 21=out */ +#define LPC_POOL_OFFS_CMD_DATA 512 /* Data range for commands - 512-1023 */ +/* LPC pool data pointers */ +#define LPC_POOL_KERNEL (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KERNEL) +#define LPC_POOL_PORT80 (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_PORT80) +#define LPC_POOL_COMX (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_COMX) +#define LPC_POOL_KEYBOARD (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KEYBOARD) +#define LPC_POOL_CMD_DATA (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD_DATA) +#define LPC_POOL_USER (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_USER) +/* LPC COMx I/O address (in x86 I/O address space) */ +#define LPC_COMX_ADDR 0x2f8 /* COM2, since superIO uses COM1 */ + +/* ADC inputs */ +/* TODO: really just need a lookup table for channels to inputs */ +#define ADC_IN0 0 /* Turn POT on badger board */ + +enum adc_channel +{ + /* EC internal die temperature in degrees K. */ + ADC_CH_EC_TEMP = 0, + /* Treat BDS pot input as charger current. */ + ADC_CH_CHARGER_CURRENT, + + ADC_CH_COUNT +}; + +/* I2C ports */ +#define I2C_PORT_BATTERY 5 // port 0 / PB2:3 on Link, open on badger +#define I2C_PORT_CHARGER 5 // port 1 / PA6:7 on Link, user LED on badger +#define I2C_PORT_THERMAL 5 // port 5 / PB6:7 on link, but PG6:7 on badger +/* I2C port speeds in kbps */ +#define I2C_SPEED_BATTERY 100 +#define I2C_SPEED_CHARGER 100 +#define I2C_SPEED_THERMAL 400 /* TODO: TMP007 supports 3.4Mbps + operation; use faster speed? */ + +/* Keyboard scanner uses an entire GPIO bank for row inputs */ +#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOH +#define KB_SCAN_ROW_GPIO LM4_GPIO_H + +/* USB charge port */ +#define USB_CHARGE_PORT_COUNT 0 + +/* GPIO signal list */ +enum gpio_signal { + /* Inputs with interrupt handlers are first for efficiency */ + GPIO_POWER_BUTTONn = 0, /* Power button */ + GPIO_LID_SWITCHn, /* Lid switch */ + /* Other inputs */ + /* Outputs */ + GPIO_DEBUG_LED, /* Debug LED */ + /* Signals which aren't implemented on BDS but we'll emulate anyway, to + * make it more convenient to debug other code. */ + GPIO_PCH_LID_SWITCHn, /* Lid switch output to PCH */ + GPIO_PCH_PWRBTNn, /* Power button output to PCH */ + + GPIO_PCH_BKLTEN, /* Backlight enable signal from PCH */ + GPIO_PCH_SLP_An, /* SLP_A# signal from PCH */ + GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */ + GPIO_PCH_SLP_S3n, /* SLP_S3# signal from PCH */ + GPIO_PCH_SLP_S4n, /* SLP_S4# signal from PCH */ + GPIO_PCH_SLP_S5n, /* SLP_S5# signal from PCH */ + GPIO_PCH_SLP_SUSn, /* SLP_SUS# signal from PCH */ + GPIO_PCH_SUSWARNn, /* SUSWARN# signal from PCH */ + GPIO_PGOOD_1_5V_DDR, /* Power good on +1.5V_DDR */ + GPIO_PGOOD_1_5V_PCH, /* Power good on +1.5V_PCH */ + GPIO_PGOOD_1_8VS, /* Power good on +1.8VS */ + GPIO_PGOOD_5VALW, /* Power good on +5VALW */ + GPIO_PGOOD_CPU_CORE, /* Power good on +CPU_CORE */ + GPIO_PGOOD_VCCP, /* Power good on +VCCP */ + GPIO_PGOOD_VCCSA, /* Power good on +VCCSA */ + GPIO_PGOOD_VGFX_CORE, /* Power good on +VGFX_CORE */ + GPIO_ENABLE_1_5V_DDR, /* Enable +1.5V_DDR supply */ + GPIO_ENABLE_BACKLIGHT, /* Enable backlight power */ + GPIO_ENABLE_VCORE, /* Enable +CPU_CORE and +VGFX_CORE */ + GPIO_ENABLE_VS, /* Enable VS power supplies */ + GPIO_PCH_DPWROK, /* DPWROK signal to PCH */ + GPIO_PCH_PWROK, /* PWROK / APWROK signals to PCH */ + GPIO_PCH_RSMRSTn, /* Reset PCH resume power plane logic */ + GPIO_PCH_SUSACKn, /* Acknowledge PCH SUSWARN# signal */ + GPIO_SHUNT_1_5V_DDR, /* Shunt +1.5V_DDR; may also enable +3V_TP + * depending on stuffing. */ + + /* Number of GPIOs; not an actual GPIO */ + GPIO_COUNT +}; + +enum temp_sensor_id { + TEMP_SENSOR_EC_INTERNAL = 0, /* EC internal temperature sensor */ + TEMP_SENSOR_CASE_DIE, + + TEMP_SENSOR_COUNT +}; + +void configure_board(void); + +#endif /* __BOARD_H */ diff --git a/board/bds/board_temp_sensor.c b/board/bds/board_temp_sensor.c new file mode 100644 index 0000000000..65b73005a1 --- /dev/null +++ b/board/bds/board_temp_sensor.c @@ -0,0 +1,22 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* BDS-specific temp sensor module for Chrome EC */ + +#include "temp_sensor.h" +#include "chip_temp_sensor.h" +#include "board.h" +#include "i2c.h" + +#define TEMP_CASE_DIE_REG_ADDR ((0x40 << 1) | I2C_FLAG_BIG_ENDIAN) +#define TEMP_CASE_DIE_ADDR \ + TMP006_ADDR(I2C_PORT_THERMAL, TEMP_CASE_DIE_REG_ADDR) + +const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = { + {"ECInternal", TEMP_SENSOR_EC_INTERNAL, TEMP_SENSOR_NO_ADDR, + chip_temp_sensor_read, TEMP_SENSOR_NO_PRINT}, + {"CaseDie", TEMP_SENSOR_CASE_DIE, TEMP_CASE_DIE_ADDR, + temp_sensor_tmp006_read_die_temp, temp_sensor_tmp006_print} +}; diff --git a/board/bds/build.mk b/board/bds/build.mk new file mode 100644 index 0000000000..73f193751f --- /dev/null +++ b/board/bds/build.mk @@ -0,0 +1,13 @@ +# Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +# the IC is TI Stellaris LM4 +CHIP:=lm4 + +board-y=board.o +board-$(CONFIG_CHARGER)+=dummy_charger.o +board-$(CONFIG_TEMP_SENSOR)+=board_temp_sensor.o diff --git a/board/bds/dummy_charger.c b/board/bds/dummy_charger.c new file mode 100644 index 0000000000..c4ee308e1c --- /dev/null +++ b/board/bds/dummy_charger.c @@ -0,0 +1,88 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "board.h" +#include "charger.h" +#include "console.h" +#include "i2c.h" +#include "uart.h" +#include "util.h" + +/* Address of battery charger */ +#define CHARGER_ADDR 0x12 + +/* Address of battery */ +#define BATTERY_ADDR 0x16 + +int charger_init(void) +{ + return EC_SUCCESS; +} + +/*****************************************************************************/ +/* Console commands */ + +static int command_charger(int argc, char **argv) +{ + int rv; + int d; + + uart_puts("Reading battery charger...\n"); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0xfe, &d); + if (rv) + return rv; + uart_printf(" Manufacturer ID: 0x%04x\n", d); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0xff, &d); + uart_printf(" Device ID: 0x%04x\n", d); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0x12, &d); + uart_printf(" Option: 0x%04x\n", d); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0x14, &d); + uart_printf(" Charge current: 0x%04x\n", d); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0x15, &d); + uart_printf(" Charge voltage: 0x%04x\n", d); + + rv = i2c_read16(I2C_PORT_CHARGER, CHARGER_ADDR, 0x3f, &d); + uart_printf(" Input current: 0x%04x\n", d); + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(charger, command_charger); + +static int command_battery(int argc, char **argv) +{ + int rv; + int d; + + uart_puts("Reading battery...\n"); + + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x08, &d); + if (rv) + return rv; + uart_printf(" Temperature: 0x%04x = %d C\n", + d, (d-2731)/10); + + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x09, &d); + uart_printf(" Voltage: 0x%04x = %d mV\n", d, d); + + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x0f, &d); + uart_printf(" Remaining capacity: 0x%04x = %d mAh\n", d, d); + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x10, &d); + uart_printf(" Full charge capacity: 0x%04x = %d mAh\n", d, d); + + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x14, &d); + uart_printf(" Desired charge current: 0x%04x = %d mA\n", d, d); + rv = i2c_read16(I2C_PORT_BATTERY, BATTERY_ADDR, 0x15, &d); + uart_printf(" Desired charge voltage: 0x%04x = %d mV\n", d, d); + + + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(battery, command_battery); + diff --git a/board/bds/ec.tasklist b/board/bds/ec.tasklist new file mode 100644 index 0000000000..a56e6769e1 --- /dev/null +++ b/board/bds/ec.tasklist @@ -0,0 +1,23 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK(n, r, d) where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + */ +#define CONFIG_TASK_LIST \ + TASK(WATCHDOG, watchdog_task, NULL) \ + TASK(KEYSCAN, keyboard_scan_task, NULL) \ + TASK(POWERBTN, power_button_task, NULL) \ + TASK(X86POWER, x86_power_task, NULL) \ + TASK(CONSOLE, console_task, NULL) \ + TASK(HOSTCMD, host_command_task, NULL) \ + TASK(I8042CMD, i8042_command_task, NULL) diff --git a/board/discovery/board.c b/board/discovery/board.c new file mode 100644 index 0000000000..e6a360dbbd --- /dev/null +++ b/board/discovery/board.c @@ -0,0 +1,67 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* STM32L Discovery board-specific configuration */ + +#include "board.h" +#include "common.h" +#include "gpio.h" +#include "registers.h" +#include "util.h" + +/* GPIO signal list. Must match order from enum gpio_signal. */ +const struct gpio_info gpio_list[GPIO_COUNT] = { + /* Inputs with interrupt handlers are first for efficiency */ + {"USER_BUTTON", GPIO_A, (1<<0), GPIO_INT_BOTH, NULL}, + /* Other inputs */ + /* Outputs */ + {"BLUE_LED", GPIO_B, (1<<6), GPIO_OUT_LOW, NULL}, + {"GREEN_LED", GPIO_B, (1<<7), GPIO_OUT_LOW, NULL}, +}; + +void configure_board(void) +{ + /* Enable all GPIOs clocks + * TODO: more fine-grained enabling for power saving + */ + STM32L_RCC_AHBENR |= 0x3f; + + /* Select Alternate function for USART3 on pins PB10/PB11 */ + STM32L_GPIO_AFRH(B) = (STM32L_GPIO_AFRH(B) & ~0x0000FF00) | + (0x7 << 12) | (0x7 << 8); + STM32L_GPIO_MODER(B) = (STM32L_GPIO_MODER(B) & ~0x00F00000) | + 0x00A00000; +} + +/** + * Stubs for non implemented drivers + * TODO: implement + */ +int jtag_pre_init(void) +{ + /* stop TIM2, TIM3 and watchdogs when the JTAG stops the CPU */ + STM32L_DBGMCU_APB1FZ |= 0x00001803; + + return EC_SUCCESS; +} + +int eeprom_init(void) +{ + return EC_SUCCESS; +} + +int i2c_init(void) +{ + return EC_SUCCESS; +} + +int power_button_init(void) +{ + return EC_SUCCESS; +} + +int adc_init(void) +{ + return EC_SUCCESS; +} diff --git a/board/discovery/board.h b/board/discovery/board.h new file mode 100644 index 0000000000..72fca4690a --- /dev/null +++ b/board/discovery/board.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* STM32L Discovery board configuration */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* 16 MHz SYSCLK clock frequency */ +#define CPU_CLOCK 16000000 + +/* Use USART3 as console serial port */ +#define CONFIG_CONSOLE_UART 1 + +#define USB_CHARGE_PORT_COUNT 0 + +/* GPIO signal list */ +enum gpio_signal { + /* Inputs with interrupt handlers are first for efficiency */ + GPIO_USER_BUTTON = 0, /* Blue user button */ + /* Other inputs */ + /* Outputs */ + GPIO_BLUE_LED, /* Blue debug LED */ + GPIO_GREEN_LED, /* Green debug LED */ + + /* Number of GPIOs; not an actual GPIO */ + GPIO_COUNT +}; + +void configure_board(void); + +#endif /* __BOARD_H */ diff --git a/board/discovery/build.mk b/board/discovery/build.mk new file mode 100644 index 0000000000..2f0ebe32af --- /dev/null +++ b/board/discovery/build.mk @@ -0,0 +1,10 @@ +# Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +# the IC is STmicro STM32L151R8H6 +CHIP:=stm32l + +board-y=board.o diff --git a/board/discovery/ec.tasklist b/board/discovery/ec.tasklist new file mode 100644 index 0000000000..0e5992b96b --- /dev/null +++ b/board/discovery/ec.tasklist @@ -0,0 +1,18 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK(n, r, d) where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + */ +#define CONFIG_TASK_LIST \ + TASK(WATCHDOG, watchdog_task, NULL) \ + TASK(CONSOLE, console_task, NULL) diff --git a/board/link/board.c b/board/link/board.c new file mode 100644 index 0000000000..830426743b --- /dev/null +++ b/board/link/board.c @@ -0,0 +1,123 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ +/* EC for Link board configuration */ + +#include "board.h" +#include "config.h" +#include "gpio.h" +#include "power_button.h" +#include "registers.h" +#include "util.h" +#include "x86_power.h" +#include "lm4_adc.h" +#include "adc.h" + +#ifndef CONFIG_TASK_X86POWER +#define x86_power_interrupt NULL +#endif +#ifndef CONFIG_TASK_POWERBTN +#define power_button_interrupt NULL +#endif + + +/* GPIO signal list. Must match order from enum gpio_signal. */ +const struct gpio_info gpio_list[GPIO_COUNT] = { + /* Inputs with interrupt handlers are first for efficiency */ + {"POWER_BUTTONn", LM4_GPIO_K, (1<<7), GPIO_INT_BOTH, + power_button_interrupt}, + {"LID_SWITCHn", LM4_GPIO_K, (1<<5), GPIO_INT_BOTH, + power_button_interrupt}, + /* Other inputs */ + {"POWER_ONEWIRE", LM4_GPIO_H, (1<<2), 0, NULL}, + {"THERMAL_DATA_READYn", LM4_GPIO_B, (1<<4), 0, NULL}, + {"AC_PRESENT", LM4_GPIO_H, (1<<3), 0, NULL}, + {"PCH_BKLTEN", LM4_GPIO_J, (1<<3), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_An", LM4_GPIO_G, (1<<5), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_ME_CSW_DEVn", LM4_GPIO_G, (1<<4), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_S3n", LM4_GPIO_J, (1<<0), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_S4n", LM4_GPIO_J, (1<<1), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_S5n", LM4_GPIO_J, (1<<2), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SLP_SUSn", LM4_GPIO_G, (1<<3), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PCH_SUSWARNn", LM4_GPIO_G, (1<<2), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_1_5V_DDR", LM4_GPIO_K, (1<<0), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_1_5V_PCH", LM4_GPIO_K, (1<<1), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_1_8VS", LM4_GPIO_K, (1<<3), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_5VALW", LM4_GPIO_H, (1<<0), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_CPU_CORE", LM4_GPIO_M, (1<<3), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_VCCP", LM4_GPIO_K, (1<<2), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_VCCSA", LM4_GPIO_H, (1<<1), GPIO_INT_BOTH, + x86_power_interrupt}, + {"PGOOD_VGFX_CORE", LM4_GPIO_D, (1<<2), GPIO_INT_BOTH, + x86_power_interrupt}, + {"RECOVERYn", LM4_GPIO_H, (1<<7), 0, NULL}, + {"USB1_STATUSn", LM4_GPIO_E, (1<<7), 0, NULL}, + {"USB2_STATUSn", LM4_GPIO_E, (1<<1), 0, NULL}, + {"WRITE_PROTECTn", LM4_GPIO_J, (1<<4), 0, NULL}, + /* Outputs; all unasserted by default */ + {"CPU_PROCHOTn", LM4_GPIO_F, (1<<2), GPIO_OUT_HIGH, NULL}, + {"ENABLE_1_5V_DDR", LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL}, + {"ENABLE_BACKLIGHT", LM4_GPIO_H, (1<<4), GPIO_OUT_LOW, NULL}, + {"ENABLE_VCORE", LM4_GPIO_F, (1<<7), GPIO_OUT_LOW, NULL}, + {"ENABLE_VS", LM4_GPIO_G, (1<<6), GPIO_OUT_LOW, NULL}, + {"ENTERING_RW", LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL}, + {"PCH_A20GATE", LM4_GPIO_Q, (1<<6), GPIO_OUT_LOW, NULL}, + {"PCH_DPWROK", LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL}, + {"PCH_HDA_SDO", LM4_GPIO_G, (1<<1), GPIO_OUT_LOW, NULL}, + {"PCH_LID_SWITCHn", LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL}, + {"PCH_NMIn", LM4_GPIO_M, (1<<2), GPIO_OUT_HIGH, NULL}, + {"PCH_PWRBTNn", LM4_GPIO_G, (1<<7), GPIO_OUT_HIGH, NULL}, + {"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL}, + {"PCH_RCINn", LM4_GPIO_Q, (1<<7), GPIO_OUT_HIGH, NULL}, + /* Exception: RSMRST# is asserted at power-on */ + {"PCH_RSMRSTn", LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL}, + {"PCH_SMIn", LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL}, + {"PCH_SUSACKn", LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL}, + {"SHUNT_1_5V_DDR", LM4_GPIO_F, (1<<6), GPIO_OUT_HIGH, NULL}, + {"USB1_CTL1", LM4_GPIO_E, (1<<2), GPIO_OUT_LOW, NULL}, + {"USB1_CTL2", LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL}, + {"USB1_CTL3", LM4_GPIO_E, (1<<4), GPIO_OUT_LOW, NULL}, + {"USB1_ENABLE", LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL}, + {"USB1_ILIM_SEL", LM4_GPIO_E, (1<<6), GPIO_OUT_LOW, NULL}, + {"USB2_CTL1", LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL}, + {"USB2_CTL2", LM4_GPIO_D, (1<<5), GPIO_OUT_LOW, NULL}, + {"USB2_CTL3", LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL}, + {"USB2_ENABLE", LM4_GPIO_D, (1<<7), GPIO_OUT_LOW, NULL}, + {"USB2_ILIM_SEL", LM4_GPIO_E, (1<<0), GPIO_OUT_LOW, NULL}, +}; + +/* ADC channels. Must be in the exactly same order as in enum adc_channel. */ +const struct adc_t adc_channels[ADC_CH_COUNT] = +{ + /* EC internal temperature is calculated by + * 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2 + * = -225 * ADC_VALUE / ADC_READ_MAX + 420.5 + */ + {"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420, + LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */}, + + /* Charger current is mapped from 0~4000mA to 0~1.6V. + * And ADC maps 0~3.3V to ADC_READ_MAX. + */ + {"ChargerCurrent", LM4_ADC_SEQ1, 33 * 4000, ADC_READ_MAX * 16, 0, + LM4_AIN(ADC_IN0), 0x06 /* IE0 | END0 */}, +}; + +void configure_board(void) +{ +} diff --git a/board/link/board.h b/board/link/board.h new file mode 100644 index 0000000000..d199d6c74f --- /dev/null +++ b/board/link/board.h @@ -0,0 +1,170 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Configuration for Link mainboard */ + +#ifndef __BOARD_H +#define __BOARD_H + +/* 66.667 Mhz clock frequency */ +#define CPU_CLOCK 66666667 + +/* Fan PWM channels */ +#define FAN_CH_CPU 0 /* CPU fan */ +#define FAN_CH_KBLIGHT 1 /* Keyboard backlight */ +#define FAN_CH_POWER_LED 5 /* Power adapter LED */ + +/* TODO: these should really only be used inside lpc.c; once they are, remove + * from board header files. */ +/* LPC channels */ +#define LPC_CH_KERNEL 0 /* Kernel commands */ +#define LPC_CH_PORT80 1 /* Port 80 debug output */ +#define LPC_CH_CMD_DATA 2 /* Data for kernel/user-mode commands */ +#define LPC_CH_KEYBOARD 3 /* 8042 keyboard emulation */ +#define LPC_CH_USER 4 /* User-mode commands */ +#define LPC_CH_COMX 7 /* UART emulation */ +/* LPC pool offsets */ +#define LPC_POOL_OFFS_KERNEL 0 /* Kernel commands - 0=in, 1=out */ +#define LPC_POOL_OFFS_PORT80 4 /* Port 80 - 4=in, 5=out */ +#define LPC_POOL_OFFS_COMX 8 /* UART emulation range - 8-15 */ +#define LPC_POOL_OFFS_KEYBOARD 16 /* Keyboard - 16=in, 17=out */ +#define LPC_POOL_OFFS_USER 20 /* User commands - 20=in, 21=out */ +#define LPC_POOL_OFFS_CMD_DATA 512 /* Data range for commands - 512-1023 */ +/* LPC pool data pointers */ +#define LPC_POOL_KERNEL (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KERNEL) +#define LPC_POOL_PORT80 (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_PORT80) +#define LPC_POOL_COMX (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_COMX) +#define LPC_POOL_KEYBOARD (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_KEYBOARD) +#define LPC_POOL_CMD_DATA (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_CMD_DATA) +#define LPC_POOL_USER (LM4_LPC_LPCPOOL + LPC_POOL_OFFS_USER) +/* LPC COMx I/O address (in x86 I/O address space) */ +#define LPC_COMX_ADDR 0x3f8 /* COM1 */ + +/* Define the following to print repeated duplicate port 80 writes. Normally + * we only print the port 80 value when it changes, because the kernel spams + * port 80 with repeated writes as a delay mechanism. */ +#define CONFIG_PORT80_PRINT_DUPLICATES + +/* ADC inputs */ +/* TODO: assign real ADC inputs */ +#define ADC_IN0 11 /* Charger current */ + +enum adc_channel +{ + /* EC internal die temperature in degrees K. */ + ADC_CH_EC_TEMP = 0, + /* Charger current in mA. */ + ADC_CH_CHARGER_CURRENT, + + ADC_CH_COUNT +}; + +/* Charger module */ +#define CONFIG_CHARGER_BQ24725 +#define CONFIG_BQ24725_R_SNS 10 /* 10 mOhm charge sense resistor */ +#define CONFIG_BQ24725_R_AC 20 /* 20 mOhm input current sense resistor */ + +/* I2C ports */ +#define I2C_PORT_BATTERY 0 +#define I2C_PORT_CHARGER 1 +#define I2C_PORT_THERMAL 5 +/* I2C port speeds in kbps */ +#define I2C_SPEED_BATTERY 100 +#define I2C_SPEED_CHARGER 100 +#define I2C_SPEED_THERMAL 400 /* TODO: TMP007 supports 3.4Mbps + operation; use faster speed? */ + +/* Keyboard scanner uses an entire GPIO bank for row inputs */ +#define KB_SCAN_ROW_IRQ LM4_IRQ_GPION +#define KB_SCAN_ROW_GPIO LM4_GPIO_N + +/* USB charge port */ +#define USB_CHARGE_PORT_COUNT 2 + +/* GPIO signal definitions. */ +enum gpio_signal { + /* Inputs with interrupt handlers are first for efficiency */ + GPIO_POWER_BUTTONn = 0, /* Power button */ + GPIO_LID_SWITCHn, /* Lid switch */ + GPIO_POWER_ONEWIRE, /* 1-wire interface to power adapter LEDs */ + GPIO_THERMAL_DATA_READYn, /* Data ready from I2C thermal sensor */ + /* Other inputs */ + GPIO_AC_PRESENT, /* AC power present */ + GPIO_PCH_BKLTEN, /* Backlight enable signal from PCH */ + GPIO_PCH_SLP_An, /* SLP_A# signal from PCH */ + GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */ + GPIO_PCH_SLP_S3n, /* SLP_S3# signal from PCH */ + GPIO_PCH_SLP_S4n, /* SLP_S4# signal from PCH */ + GPIO_PCH_SLP_S5n, /* SLP_S5# signal from PCH */ + GPIO_PCH_SLP_SUSn, /* SLP_SUS# signal from PCH */ + GPIO_PCH_SUSWARNn, /* SUSWARN# signal from PCH */ + GPIO_PGOOD_1_5V_DDR, /* Power good on +1.5V_DDR */ + GPIO_PGOOD_1_5V_PCH, /* Power good on +1.5V_PCH */ + GPIO_PGOOD_1_8VS, /* Power good on +1.8VS */ + GPIO_PGOOD_5VALW, /* Power good on +5VALW */ + GPIO_PGOOD_CPU_CORE, /* Power good on +CPU_CORE */ + GPIO_PGOOD_VCCP, /* Power good on +VCCP */ + GPIO_PGOOD_VCCSA, /* Power good on +VCCSA */ + GPIO_PGOOD_VGFX_CORE, /* Power good on +VGFX_CORE */ + GPIO_RECOVERYn, /* Recovery signal from servo */ + GPIO_USB1_STATUSn, /* USB charger port 1 status output */ + GPIO_USB2_STATUSn, /* USB charger port 2 status output */ + GPIO_WRITE_PROTECTn, /* Write protect input */ + /* Outputs */ + GPIO_CPU_PROCHOTn, /* Force CPU to think it's overheated */ + GPIO_ENABLE_1_5V_DDR, /* Enable +1.5V_DDR supply */ + GPIO_ENABLE_BACKLIGHT, /* Enable backlight power */ + GPIO_ENABLE_VCORE, /* Enable +CPU_CORE and +VGFX_CORE */ + GPIO_ENABLE_VS, /* Enable VS power supplies */ + GPIO_ENTERING_RW, /* Indicate when EC is entering RW code */ + GPIO_PCH_A20GATE, /* A20GATE signal to PCH */ + GPIO_PCH_DPWROK, /* DPWROK signal to PCH */ + GPIO_PCH_HDA_SDO, /* HDA_SDO signal to PCH; when high, ME + * ignores security descriptor */ + GPIO_PCH_LID_SWITCHn, /* Lid switch output to PCH */ + GPIO_PCH_NMIn, /* Non-maskable interrupt pin to PCH */ + GPIO_PCH_PWRBTNn, /* Power button output to PCH */ + GPIO_PCH_PWROK, /* PWROK / APWROK signals to PCH */ + GPIO_PCH_RCINn, /* RCIN# signal to PCH */ + GPIO_PCH_RSMRSTn, /* Reset PCH resume power plane logic */ + GPIO_PCH_SMIn, /* System management interrupt to PCH */ + GPIO_PCH_SUSACKn, /* Acknowledge PCH SUSWARN# signal */ + GPIO_SHUNT_1_5V_DDR, /* Shunt +1.5V_DDR; may also enable +3V_TP + * depending on stuffing. */ + GPIO_USB1_CTL1, /* USB charger port 1 CTL1 output */ + GPIO_USB1_CTL2, /* USB charger port 1 CTL2 output */ + GPIO_USB1_CTL3, /* USB charger port 1 CTL3 output */ + GPIO_USB1_ENABLE, /* USB charger port 1 enable */ + GPIO_USB1_ILIM_SEL, /* USB charger port 1 ILIM_SEL output */ + GPIO_USB2_CTL1, /* USB charger port 2 CTL1 output */ + GPIO_USB2_CTL2, /* USB charger port 2 CTL2 output */ + GPIO_USB2_CTL3, /* USB charger port 2 CTL3 output */ + GPIO_USB2_ENABLE, /* USB charger port 2 enable */ + GPIO_USB2_ILIM_SEL, /* USB charger port 2 ILIM_SEL output */ + + /* Number of GPIOs; not an actual GPIO */ + GPIO_COUNT +}; + +enum temp_sensor_id { + /* I2C die temperature sensor near CPU */ + TEMP_SENSOR_I2C_DIE_NEAR_CPU = 0, + /* PCH temperature sensor */ + TEMP_SENSOR_I2C_DIE_NEAR_PCH, + /* DDR memory temperature sensor */ + TEMP_SENSOR_I2C_DIE_NEAR_DDR, + /* Battery charger temperature sensor */ + TEMP_SENSOR_I2C_DIE_NEAR_CHARGER, + /* EC internal temperature sensor */ + TEMP_SENSOR_EC_INTERNAL, + + /* TODO: I2C temperature sensors. */ + + TEMP_SENSOR_COUNT +}; + +void configure_board(void); + +#endif /* __BOARD_H */ diff --git a/board/link/board_temp_sensor.c b/board/link/board_temp_sensor.c new file mode 100644 index 0000000000..4a937c9bf3 --- /dev/null +++ b/board/link/board_temp_sensor.c @@ -0,0 +1,37 @@ +/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Link-specific temp sensor module for Chrome EC */ + +#include "temp_sensor.h" +#include "chip_temp_sensor.h" +#include "board.h" +#include "i2c.h" + +#define TEMP_CPU_REG_ADDR ((0x40 << 1) | I2C_FLAG_BIG_ENDIAN) +#define TEMP_PCH_REG_ADDR ((0x41 << 1) | I2C_FLAG_BIG_ENDIAN) +#define TEMP_DDR_REG_ADDR ((0x43 << 1) | I2C_FLAG_BIG_ENDIAN) +#define TEMP_CHARGER_REG_ADDR ((0x45 << 1) | I2C_FLAG_BIG_ENDIAN) + +#define TEMP_CPU_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_CPU_REG_ADDR) +#define TEMP_PCH_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_PCH_REG_ADDR) +#define TEMP_DDR_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_DDR_REG_ADDR) +#define TEMP_CHARGER_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_CHARGER_REG_ADDR) + +/* Temperature sensors data. Must be in the same order as enum + * temp_sensor_id. + */ +const struct temp_sensor_t temp_sensors[TEMP_SENSOR_COUNT] = { + {"CPU", TEMP_SENSOR_I2C_DIE_NEAR_CPU, TEMP_CPU_ADDR, + temp_sensor_tmp006_read_die_temp, temp_sensor_tmp006_print}, + {"PCH", TEMP_SENSOR_I2C_DIE_NEAR_PCH, TEMP_PCH_ADDR, + temp_sensor_tmp006_read_die_temp, temp_sensor_tmp006_print}, + {"DDR", TEMP_SENSOR_I2C_DIE_NEAR_DDR, TEMP_DDR_ADDR, + temp_sensor_tmp006_read_die_temp, temp_sensor_tmp006_print}, + {"Charger", TEMP_SENSOR_I2C_DIE_NEAR_CHARGER, TEMP_CHARGER_ADDR, + temp_sensor_tmp006_read_die_temp, temp_sensor_tmp006_print}, + {"ECInternal", TEMP_SENSOR_EC_INTERNAL, TEMP_SENSOR_NO_ADDR, + chip_temp_sensor_read, TEMP_SENSOR_NO_PRINT}, +}; diff --git a/board/link/build.mk b/board/link/build.mk new file mode 100644 index 0000000000..b600d69d13 --- /dev/null +++ b/board/link/build.mk @@ -0,0 +1,12 @@ +# Copyright (c) 2012 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build +# + +# the IC is TI Stellaris LM4 +CHIP:=lm4 + +board-y=board.o +board-$(CONFIG_TEMP_SENSOR)+=board_temp_sensor.o diff --git a/board/link/ec.tasklist b/board/link/ec.tasklist new file mode 100644 index 0000000000..a56e6769e1 --- /dev/null +++ b/board/link/ec.tasklist @@ -0,0 +1,23 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK(n, r, d) where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + */ +#define CONFIG_TASK_LIST \ + TASK(WATCHDOG, watchdog_task, NULL) \ + TASK(KEYSCAN, keyboard_scan_task, NULL) \ + TASK(POWERBTN, power_button_task, NULL) \ + TASK(X86POWER, x86_power_task, NULL) \ + TASK(CONSOLE, console_task, NULL) \ + TASK(HOSTCMD, host_command_task, NULL) \ + TASK(I8042CMD, i8042_command_task, NULL) |