diff options
Diffstat (limited to 'board/stm32f446e-eval')
-rw-r--r-- | board/stm32f446e-eval/board.c | 58 | ||||
-rw-r--r-- | board/stm32f446e-eval/board.h | 54 | ||||
-rw-r--r-- | board/stm32f446e-eval/build.mk | 12 | ||||
-rw-r--r-- | board/stm32f446e-eval/ec.tasklist | 21 | ||||
-rw-r--r-- | board/stm32f446e-eval/gpio.inc | 62 |
5 files changed, 207 insertions, 0 deletions
diff --git a/board/stm32f446e-eval/board.c b/board/stm32f446e-eval/board.c new file mode 100644 index 0000000000..0b8691278c --- /dev/null +++ b/board/stm32f446e-eval/board.c @@ -0,0 +1,58 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include "common.h" +#include "dma.h" +#include "ec_version.h" +#include "gpio.h" +#include "gpio_list.h" +#include "hooks.h" +#include "registers.h" +#include "stm32-dma.h" + +#define GPIO_SET_HS(bank, number) \ + (STM32_GPIO_OSPEEDR(GPIO_##bank) |= (0x3 << (number * 2))) + +void board_config_post_gpio_init(void) +{ + /* We use MCO2 clock passthrough to provide a clock to USB HS */ + gpio_config_module(MODULE_MCO, 1); + /* GPIO PC9 to high speed */ + GPIO_SET_HS(C, 9); + + /* Set USB GPIO to high speed */ + GPIO_SET_HS(A, 11); + GPIO_SET_HS(A, 12); + + GPIO_SET_HS(C, 3); + GPIO_SET_HS(C, 2); + GPIO_SET_HS(C, 0); + GPIO_SET_HS(A, 5); + + GPIO_SET_HS(B, 5); + GPIO_SET_HS(B, 13); + GPIO_SET_HS(B, 12); + GPIO_SET_HS(B, 2); + GPIO_SET_HS(B, 10); + GPIO_SET_HS(B, 1); + GPIO_SET_HS(B, 0); + GPIO_SET_HS(A, 3); + + /* Set I2C GPIO to HS */ + GPIO_SET_HS(B, 6); + GPIO_SET_HS(B, 7); + GPIO_SET_HS(F, 1); + GPIO_SET_HS(F, 0); + GPIO_SET_HS(A, 8); + GPIO_SET_HS(B, 4); + GPIO_SET_HS(C, 6); + GPIO_SET_HS(C, 7); +} + +static void board_init(void) +{ +} +DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); + diff --git a/board/stm32f446e-eval/board.h b/board/stm32f446e-eval/board.h new file mode 100644 index 0000000000..24735a2dc7 --- /dev/null +++ b/board/stm32f446e-eval/board.h @@ -0,0 +1,54 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* STM32F446E-Eval board configuration */ + +#ifndef __CROS_EC_BOARD_H +#define __CROS_EC_BOARD_H + +/* Use external clock */ +#define CONFIG_STM32_CLOCK_HSE_HZ 8000000 + +/* Optional features */ +#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_LID_SWITCH +#define CONFIG_BOARD_POST_GPIO_INIT + +/* Enable console recasting of GPIO type. */ +#define CONFIG_CMD_GPIO_EXTENDED + +/* The UART console is on USART1 (PA9/PA10) */ +#undef CONFIG_UART_CONSOLE +#define CONFIG_UART_CONSOLE 1 +#undef CONFIG_UART_TX_BUF_SIZE +#define CONFIG_UART_TX_BUF_SIZE 4096 +#define CONFIG_UART_TX_REQ_CH 4 +#define CONFIG_UART_RX_REQ_CH 4 + +/* This is not actually an EC so disable some features. */ +#undef CONFIG_WATCHDOG_HELP +#undef CONFIG_LID_SWITCH +#undef CONFIG_WATCHDOG + +/* Optional features */ +#define CONFIG_STM_HWTIMER32 +#define CONFIG_DMA_HELP + +/* + * Allow dangerous commands all the time, since we don't have a write protect + * switch. + */ +#define CONFIG_SYSTEM_UNLOCKED + +#ifndef __ASSEMBLER__ +#undef CONFIG_FLASH + +/* Timer selection */ +#define TIM_CLOCK32 5 + +#include "gpio_signal.h" + +#endif /* !__ASSEMBLER__ */ +#endif /* __CROS_EC_BOARD_H */ diff --git a/board/stm32f446e-eval/build.mk b/board/stm32f446e-eval/build.mk new file mode 100644 index 0000000000..6b06f2bb8f --- /dev/null +++ b/board/stm32f446e-eval/build.mk @@ -0,0 +1,12 @@ +# -*- makefile -*- +# Copyright 2016 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Board specific files build + +CHIP:=stm32 +CHIP_FAMILY:=stm32f4 +CHIP_VARIANT:=stm32f446 + +board-y=board.o diff --git a/board/stm32f446e-eval/ec.tasklist b/board/stm32f446e-eval/ec.tasklist new file mode 100644 index 0000000000..c4605514e5 --- /dev/null +++ b/board/stm32f446e-eval/ec.tasklist @@ -0,0 +1,21 @@ +/* Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/** + * List of enabled tasks in the priority order + * + * The first one has the lowest priority. + * + * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and + * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, + * where : + * 'n' in the name of the task + * 'r' in the main routine of the task + * 'd' in an opaque parameter passed to the routine at startup + * 's' is the stack size in bytes; must be a multiple of 8 + */ +#define CONFIG_TASK_LIST \ + TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \ + TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) diff --git a/board/stm32f446e-eval/gpio.inc b/board/stm32f446e-eval/gpio.inc new file mode 100644 index 0000000000..3d1753d43b --- /dev/null +++ b/board/stm32f446e-eval/gpio.inc @@ -0,0 +1,62 @@ +/* -*- mode:c -*- + * + * Copyright 2016 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Declare symbolic names for all the GPIOs that we care about. + * Note: Those with interrupt handlers must be declared first. */ + +/* Outputs */ +GPIO(PD11, PIN(D, 11), GPIO_OUT_HIGH) + +GPIO(I2C1_SCL, PIN(B, 8), GPIO_INPUT) +GPIO(I2C1_SDA, PIN(B, 9), GPIO_INPUT) +GPIO(FMPI2C_SCL, PIN(C, 6), GPIO_INPUT) +GPIO(FMPI2C_SDA, PIN(C, 7), GPIO_INPUT) + +/* USART3 TX/RX */ +GPIO(MCU_UART1_TX, PIN(A, 9), GPIO_INPUT) +GPIO(MCU_UART1_RX, PIN(A, 10), GPIO_INPUT) +GPIO(MCU_UART3_TX, PIN(C, 10), GPIO_INPUT) +GPIO(MCU_UART3_RX, PIN(C, 11), GPIO_INPUT) + +GPIO(USB_FS_DM, PIN(A, 11), GPIO_INPUT) +GPIO(USB_FS_DP, PIN(A, 12), GPIO_INPUT) + + +GPIO(USB_HS_ULPI_NXT, PIN(C, 3), GPIO_INPUT) +GPIO(USB_HS_ULPI_DIR, PIN(C, 2), GPIO_INPUT) +GPIO(USB_HS_ULPI_STP, PIN(C, 0), GPIO_INPUT) +GPIO(USB_HS_ULPI_CK, PIN(A, 5), GPIO_INPUT) + +GPIO(USB_HS_ULPI_D7, PIN(B, 5), GPIO_INPUT) +GPIO(USB_HS_ULPI_D6, PIN(B,13), GPIO_INPUT) +GPIO(USB_HS_ULPI_D5, PIN(B,12), GPIO_INPUT) +GPIO(USB_HS_ULPI_D4, PIN(B, 2), GPIO_INPUT) +GPIO(USB_HS_ULPI_D3, PIN(B,10), GPIO_INPUT) +GPIO(USB_HS_ULPI_D2, PIN(B, 1), GPIO_INPUT) +GPIO(USB_HS_ULPI_D1, PIN(B, 0), GPIO_INPUT) +GPIO(USB_HS_ULPI_D0, PIN(A, 3), GPIO_INPUT) + + + +/* Unimplemented signals since this is a dev board */ +UNIMPLEMENTED(ENTERING_RW) +UNIMPLEMENTED(WP_L) + +ALTERNATE(PIN_MASK(A, 0x0600), 7, MODULE_UART, 0) /* USART1: PA9/PA10 - Console */ +ALTERNATE(PIN_MASK(C, 0x0C00), 7, MODULE_USART, 0) /* USART3: PC10/PC11 - NOT Console */ +ALTERNATE(PIN_MASK(A, 0x0100), 0, MODULE_MCO, 0) /* MCO1: PA8 */ +ALTERNATE(PIN_MASK(C, 0x0200), 0, MODULE_MCO, 0) /* MCO2: PC9 */ + +ALTERNATE(PIN_MASK(B, 0x0300), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* I2C1: PB8-9 */ +ALTERNATE(PIN_MASK(C, 0x00c0), 4, MODULE_I2C, GPIO_ODR_HIGH | GPIO_PULL_UP) /* FMPI2C MASTER:PC6/7 */ + +ALTERNATE(PIN_MASK(A, 0x1800), 10, MODULE_USB, 0) /* DWC USB OTG: PA11/12 */ + +/* OTG HS */ +ALTERNATE(PIN_MASK(A, 0x0028), 10, MODULE_USB, 0) /* DWC USB OTG HS */ +ALTERNATE(PIN_MASK(B, 0x3427), 10, MODULE_USB, 0) /* DWC USB OTG HS */ +ALTERNATE(PIN_MASK(C, 0x000d), 10, MODULE_USB, 0) /* DWC USB OTG HS */ |