diff options
| -rw-r--r-- | baseboard/grunt/baseboard.h | 9 | ||||
| -rw-r--r-- | chip/npcx/gpio.c | 18 | ||||
| -rw-r--r-- | chip/npcx/hwtimer.c | 14 | ||||
| -rw-r--r-- | chip/npcx/hwtimer_chip.h | 7 | ||||
| -rw-r--r-- | include/config.h | 13 |
5 files changed, 58 insertions, 3 deletions
diff --git a/baseboard/grunt/baseboard.h b/baseboard/grunt/baseboard.h index fcc5f60371..b47befb418 100644 --- a/baseboard/grunt/baseboard.h +++ b/baseboard/grunt/baseboard.h @@ -88,6 +88,15 @@ #define CONFIG_POWER_BUTTON #define CONFIG_POWER_BUTTON_X86 +/* + * On power-on, H1 releases the EC from reset but then quickly asserts and + * releases the reset a second time. This means the EC sees 2 resets: + * (1) power-on reset, (2) reset-pin reset. If we add a delay between reset (1) + * and configuring GPIO output levels, then reset (2) will happen before the + * end of the delay so we avoid extra output toggles. + */ +#define CONFIG_GPIO_INIT_POWER_ON_DELAY_MS 100 + #define CONFIG_KEYBOARD_BOARD_CONFIG #define CONFIG_KEYBOARD_COL2_INVERTED #define CONFIG_KEYBOARD_PROTOCOL_8042 diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index cabda69b15..7be79f4e54 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -22,6 +22,7 @@ #include "lpc_chip.h" #include "ec_commands.h" #include "host_command.h" +#include "hwtimer_chip.h" #if !(DEBUG_GPIO) #define CPUTS(...) @@ -402,6 +403,23 @@ void gpio_pre_init(void) system_check_bbram_on_reset(); is_warm = system_is_reboot_warm(); +#ifdef CONFIG_GPIO_INIT_POWER_ON_DELAY_MS + /* + * On power-on of some boards, H1 releases the EC from reset but then + * quickly asserts and releases the reset a second time. This means the + * EC sees 2 resets: (1) power-on reset, (2) reset-pin reset. If we add + * a delay between reset (1) and configuring GPIO output levels, then + * reset (2) will happen before the end of the delay so we avoid extra + * output toggles. + * + * Make sure to set up the timer before using udelay(). + */ + if (system_get_reset_flags() & RESET_FLAG_POWER_ON) { + __hw_early_init_hwtimer(0); + udelay(CONFIG_GPIO_INIT_POWER_ON_DELAY_MS * MSEC); + } +#endif + #ifdef CHIP_FAMILY_NPCX7 /* * TODO: Set bit 7 of DEVCNT again for npcx7 series. Please see Errata diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index e46a56fb1e..38a8fce548 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -303,7 +303,7 @@ static void update_prescaler(void) } DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT); -int __hw_clock_source_init(uint32_t start_t) +void __hw_early_init_hwtimer(uint32_t start_t) { /* * 1. Use ITIM16-1 as internal time reading @@ -321,11 +321,19 @@ int __hw_clock_source_init(uint32_t start_t) /* Set initial prescaler */ update_prescaler(); + hw_clock_source_set_preload(start_t, 1); +} + +/* Note that early_init_hwtimer() has already executed by this point */ +int __hw_clock_source_init(uint32_t start_t) +{ /* * Override the count with the start value now that counting has - * started. + * started. Note that we may have already called this function from + * gpio_pre_init(), but only in the case where we expected a reset, so + * we should not get here in that case. */ - hw_clock_source_set_preload(start_t, 1); + __hw_early_init_hwtimer(start_t); /* Enable interrupt of ITIM */ task_enable_irq(NPCX_IRQ_ITIM32); diff --git a/chip/npcx/hwtimer_chip.h b/chip/npcx/hwtimer_chip.h index 3b00b0dea5..d5939f77a8 100644 --- a/chip/npcx/hwtimer_chip.h +++ b/chip/npcx/hwtimer_chip.h @@ -35,4 +35,11 @@ uint32_t __hw_clock_get_sleep_time(uint16_t pre_evt_cnt); /* Handle ITIM32 overflow if interrupt is disabled */ void __hw_clock_handle_overflow(uint32_t clksrc_high); +/** + * Set up the timer for use before the task system is available + * + * @param start_t Value to assign to the counter + */ +void __hw_early_init_hwtimer(uint32_t start_t); + #endif /* __CROS_EC_HWTIMER_CHIP_H */ diff --git a/include/config.h b/include/config.h index fa30e2c4c4..261628c996 100644 --- a/include/config.h +++ b/include/config.h @@ -1648,6 +1648,19 @@ #undef CONFIG_GESTURE_SIGMO_EVENT +/* + * Delay between power on and configuring GPIOs. + * On power-on of some boards, H1 releases the EC from reset but then + * quickly asserts and releases the reset a second time. This means the + * EC sees 2 resets: (1) power-on reset, (2) reset-pin reset. If we add + * a delay between reset (1) and configuring GPIO output levels, then + * reset (2) will happen before the end of the delay so we avoid extra + * output toggles. + * + * NOTE: Implemented only for npcx + */ +#undef CONFIG_GPIO_INIT_POWER_ON_DELAY_MS + /* Do we want to detect the lid angle? */ #undef CONFIG_LID_ANGLE |