diff options
| -rw-r--r-- | chip/it83xx/clock.c | 10 | ||||
| -rw-r--r-- | core/nds32/ec.lds.S | 8 | ||||
| -rw-r--r-- | core/nds32/init.S | 1 |
3 files changed, 15 insertions, 4 deletions
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c index f2e2a6d37b..437cb3b4b7 100644 --- a/chip/it83xx/clock.c +++ b/chip/it83xx/clock.c @@ -37,6 +37,16 @@ void clock_init(void) /* Set EC Clock Frequency to PLL frequency. */ IT83XX_ECPM_SCDCR3 &= 0xf0; + /* + * The VCC power status is treated as power-on. + * The VCC supply of LPC and related functions (EC2I, + * KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI). + * It means VCC (pin 11) should be logic high before using + * these functions, or firmware treats VCC logic high + * as following setting. + */ + IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & 0x3F) + 0x40; + /* Turn off auto clock gating. */ IT83XX_ECPM_AUTOCG = 0x00; } diff --git a/core/nds32/ec.lds.S b/core/nds32/ec.lds.S index 84e08d34bc..f66412cd6d 100644 --- a/core/nds32/ec.lds.S +++ b/core/nds32/ec.lds.S @@ -22,7 +22,7 @@ MEMORY SECTIONS { .text : { - OUTDIR/core/CORE/init.o (.text.vecttable) + KEEP(OUTDIR/core/CORE/init.o (.text.vecttable)) . = ALIGN(4); __version_struct_offset = .; KEEP(*(.rodata.ver)) @@ -31,8 +31,8 @@ SECTIONS #else . = ALIGN(4); #endif - OUTDIR/core/CORE/init.o (.text.vectirq) - OUTDIR/core/CORE/init.o (.text) + KEEP(OUTDIR/core/CORE/init.o (.text.vectirq)) + KEEP(OUTDIR/core/CORE/init.o (.text)) *(.text*) #ifdef COMPILE_FOR_RAM } > IRAM @@ -48,7 +48,7 @@ SECTIONS . = ALIGN(4); __irqhandler = .; - OUTDIR/core/CORE/init.o (.rodata.vecthandlers) + KEEP(OUTDIR/core/CORE/init.o (.rodata.vecthandlers)) . = ALIGN(4); __cmds = .; diff --git a/core/nds32/init.S b/core/nds32/init.S index bd166ef668..0f2c0710d6 100644 --- a/core/nds32/init.S +++ b/core/nds32/init.S @@ -73,6 +73,7 @@ vector irq_14 /* HW 14 */ vector irq_15 /* HW 15 */ /* E-flash signature */ +.org 0x80 .balign 16 .global eflash_sig eflash_sig: |