diff options
| -rw-r--r-- | board/drawcia/board.c | 15 | ||||
| -rw-r--r-- | board/drawcia/gpio.inc | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/board/drawcia/board.c b/board/drawcia/board.c index f160335e53..e1f91871dd 100644 --- a/board/drawcia/board.c +++ b/board/drawcia/board.c @@ -450,6 +450,21 @@ __override void board_ocpc_init(struct ocpc_data *ocpc) ocpc->chg_flags[CHARGER_SECONDARY] |= OCPC_NO_ISYS_MEAS_CAP; } +__override void board_pulse_entering_rw(void) +{ + /* + * On the ITE variants, the EC_ENTERING_RW signal was connected to a pin + * which is active high by default. This causes Cr50 to think that the + * EC has jumped to its RW image even though this may not be the case. + * The pin is changed to GPIO_EC_ENTERING_RW2. + */ + gpio_set_level(GPIO_EC_ENTERING_RW, 1); + gpio_set_level(GPIO_EC_ENTERING_RW2, 1); + usleep(MSEC); + gpio_set_level(GPIO_EC_ENTERING_RW, 0); + gpio_set_level(GPIO_EC_ENTERING_RW2, 0); +} + void board_reset_pd_mcu(void) { /* diff --git a/board/drawcia/gpio.inc b/board/drawcia/gpio.inc index 429b952eef..890b6ee9e4 100644 --- a/board/drawcia/gpio.inc +++ b/board/drawcia/gpio.inc @@ -98,6 +98,7 @@ GPIO(EC_SUB_IO_2_1, PIN(F, 1), GPIO_INPUT) /* Misc */ GPIO(EN_BL_OD, PIN(K, 4), GPIO_ODR_LOW) GPIO(EC_ENTERING_RW, PIN(G, 0), GPIO_OUT_LOW) +GPIO(EC_ENTERING_RW2, PIN(C, 7), GPIO_OUT_LOW) GPIO(CCD_MODE_ODL, PIN(H, 5), GPIO_INPUT) GPIO(EC_BATTERY_PRES_ODL, PIN(I, 4), GPIO_INPUT) GPIO(EN_KB_BL, PIN(J, 3), GPIO_OUT_LOW) /* Currently unused */ |