diff options
| -rw-r--r-- | chip/mt_scp/clock.c | 8 | ||||
| -rw-r--r-- | chip/mt_scp/registers.h | 16 |
2 files changed, 20 insertions, 4 deletions
diff --git a/chip/mt_scp/clock.c b/chip/mt_scp/clock.c index edc50d5939..e28106bcc3 100644 --- a/chip/mt_scp/clock.c +++ b/chip/mt_scp/clock.c @@ -314,7 +314,13 @@ void scp_enable_clock(void) /* Enable default clock gate */ SCP_CLK_GATE |= CG_DMA_CH3 | CG_DMA_CH2 | CG_DMA_CH1 | CG_DMA_CH0 | - CG_I2C_M | CG_MAD_M; + CG_I2C_M | CG_MAD_M | CG_AP2P_M; + + /* Select pwrap_ulposc */ + AP_CLK_CFG_5 = (AP_CLK_CFG_5 & ~PWRAP_ULPOSC_MASK) | OSC_D16; + + /* Enable pwrap_ulposc clock gate */ + AP_CLK_CFG_5_CLR = PWRAP_ULPOSC_CG; } void clock_control_irq(void) diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 248a63e1ee..1e6b9f90a9 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -400,9 +400,9 @@ #define SCP_EINT_DBNC_CLR REG32_ADDR(SCP_EINT_BASE + 0x700) #define SCP_PMICWP2P_BASE (SCP_CFG_BASE + 0xB000) -#define PMICW_WACS_CMD REG32(SCP_PMICWP2P + 0x200) -#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P + 0x204) -#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P + 0x208) +#define PMICW_WACS_CMD REG32(SCP_PMICWP2P_BASE + 0x200) +#define PMICW_WACS_RDATA REG32(SCP_PMICWP2P_BASE + 0x204) +#define PMICW_WACS_VLDCLR REG32(SCP_PMICWP2P_BASE + 0x208) #define SCP_SPMP2P_BASE (SCP_CFG_BASE + 0xC000) #define SCP_DMA_BASE (SCP_CFG_BASE + 0xD000) #define DMA_ACKINT_CHX REG32(SCP_DMA_BASE + 0x20) @@ -471,6 +471,16 @@ #define TOPCK_BASE AP_BASE /* Top clock */ #define SCP_UART2_BASE (AP_BASE + 0x01002000) /* AP UART0 */ +/* CLK_CFG_5 regs */ +#define AP_CLK_CFG_5 REG32(TOPCK_BASE + 0x0090) +#define PWRAP_ULPOSC_MASK (0x3000000) +#define CLK26M (0 << 24) +#define OSC_D16 (1 << 24) +#define OSC_D4 (2 << 24) +#define OSC_D8 (3 << 24) +#define AP_CLK_CFG_5_CLR REG32(TOPCK_BASE + 0x0098) +#define PWRAP_ULPOSC_CG BIT(31) + /* OSC meter */ #define AP_CLK_MISC_CFG_0 REG32(TOPCK_BASE + 0x0104) #define MISC_METER_DIVISOR_MASK 0xff000000 |