diff options
| -rw-r--r-- | chip/stm32/clock-stm32l4.c | 14 | ||||
| -rw-r--r-- | chip/stm32/gpio.c | 37 | ||||
| -rw-r--r-- | chip/stm32/registers-stm32l5.h | 22 |
3 files changed, 60 insertions, 13 deletions
diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index 412771163c..6d10fbf79e 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -724,7 +724,14 @@ static void pre_work_set_rtc_alarm(void) while (!(STM32_RTC_ISR & STM32_RTC_ISR_ALRAWF)) ; STM32_RTC_ISR &= ~STM32_RTC_ISR_ALRAF; +#ifdef STM32_EXTI_RPR + /* Separate rising and falling edge pending registers. */ + STM32_EXTI_RPR = BIT(18); + STM32_EXTI_FPR = BIT(18); +#else + /* One combined rising/falling edge pending registers. */ STM32_EXTI_PR = BIT(18); +#endif } /* Register setup after RTC alarm is updated */ @@ -947,7 +954,14 @@ void reset_rtc_alarm(struct rtc_time_reg *rtc) /* Disable RTC alarm interrupt */ STM32_EXTI_IMR &= ~BIT(18); +#ifdef STM32_EXTI_RPR + /* Separate rising and falling edge pending registers. */ + STM32_EXTI_RPR = BIT(18); + STM32_EXTI_FPR = BIT(18); +#else + /* One combined rising/falling edge pending registers. */ STM32_EXTI_PR = BIT(18); +#endif /* Clear the pending RTC alarm IRQ in NVIC */ task_clear_pending_irq(STM32_IRQ_RTC_ALARM); diff --git a/chip/stm32/gpio.c b/chip/stm32/gpio.c index 2ad9f99d79..ade662d9d8 100644 --- a/chip/stm32/gpio.c +++ b/chip/stm32/gpio.c @@ -109,12 +109,20 @@ int gpio_enable_interrupt(enum gpio_signal signal) exti_events[bit] = signal; group = bit / 4; - shift = (bit % 4) * 4; + shift = bit % 4; bank = (g->port - STM32_GPIOA_BASE) / 0x400; +#ifdef STM32_EXTI_EXTICR + /* STM32L5 has 8-bit fields as part of EXTI registers. */ + STM32_EXTI_EXTICR(group) = + (STM32_EXTI_EXTICR(group) & ~(0xFF << (shift * 8))) | + (bank << (shift * 8)); +#else + /* Other STM chips have 4-bit fields as part of SYSCFG registers. */ STM32_SYSCFG_EXTICR(group) = - (STM32_SYSCFG_EXTICR(group) & ~(0xF << shift)) | - (bank << shift); + (STM32_SYSCFG_EXTICR(group) & ~(0xF << (shift * 4))) | + (bank << (shift * 4)); +#endif STM32_EXTI_IMR |= g->mask; return EC_SUCCESS; @@ -142,11 +150,19 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal) { const struct gpio_info *g = gpio_list + signal; - if (!g->mask || signal >= GPIO_IH_COUNT) + if (!g->mask || signal >= GPIO_IH_COUNT) { return EC_ERROR_INVAL; + } /* Write 1 to clear interrupt */ +#ifdef STM32_EXTI_RPR + /* Separate rising and falling edge pending registers. */ + STM32_EXTI_RPR = g->mask; + STM32_EXTI_FPR = g->mask; +#else + /* One combined rising/falling edge pending registers. */ STM32_EXTI_PR = g->mask; +#endif return EC_SUCCESS; } @@ -157,12 +173,21 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal) void __keep gpio_interrupt(void) { int bit; + uint8_t signal; +#ifdef STM32_EXTI_RPR + /* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */ + uint32_t pending_r = STM32_EXTI_RPR & 0xFFFF; + uint32_t pending_f = STM32_EXTI_FPR & 0xFFFF; + uint32_t pending = pending_r | pending_f; + /* Write 1 to clear interrupt */ + STM32_EXTI_RPR = pending_r; + STM32_EXTI_FPR = pending_f; +#else /* process only GPIO EXTINTs (EXTINT0..15) not other EXTINTs */ uint32_t pending = STM32_EXTI_PR & 0xFFFF; - uint8_t signal; - /* Write 1 to clear interrupt */ STM32_EXTI_PR = pending; +#endif while (pending) { bit = get_next_bit(&pending); diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index eec7413233..45f333951b 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -1941,7 +1941,6 @@ #define STM32_RCC_CRRCR_HSI48CAL_8 (0x100UL << STM32_RCC_CRRCR_HSI48CAL_POS) #define STM32_SYSCFG_CFGR1 REG32(STM32_SYSCFG_BASE + 0x04) -#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n)) #define STM32_SYSCFG_I2CFMP(n) BIT(n + 21) /* Peripheral bits for STM32_RCC_APB/AHB and DBGMCU regs */ @@ -2137,12 +2136,21 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t; #define STM32_OPTB_WRP1BR STM32_FLASH_WRP1BR /* --- External Interrupts --- */ -#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00) -#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04) -#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08) -#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c) -#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10) -#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14) +#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x00) +#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x04) +#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x08) +#define STM32_EXTI_RPR REG32(STM32_EXTI_BASE + 0x0C) +#define STM32_EXTI_FPR REG32(STM32_EXTI_BASE + 0x10) +#define STM32_EXTI_RTSR2 REG32(STM32_EXTI_BASE + 0x20) +#define STM32_EXTI_FTSR2 REG32(STM32_EXTI_BASE + 0x24) +#define STM32_EXTI_SWIER2 REG32(STM32_EXTI_BASE + 0x28) +#define STM32_EXTI_RPR2 REG32(STM32_EXTI_BASE + 0x2C) +#define STM32_EXTI_FPR2 REG32(STM32_EXTI_BASE + 0x30) +#define STM32_EXTI_EXTICR(n) REG32(STM32_EXTI_BASE + 0x60 + 4 * (n)) +#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x80) +#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x84) +#define STM32_EXTI_IMR2 REG32(STM32_EXTI_BASE + 0x80) +#define STM32_EXTI_EMR2 REG32(STM32_EXTI_BASE + 0x84) #define EXTI_RTC_ALR_EVENT BIT(18) |