Merge remote-tracking branch cros/main into firmware-corsola-15194.B-main

Generated by: util/update_release_branch.py -r -z --board corsla --relevant_paths_file
util/corsola-relevant-paths.txt firmware-corsola-15194.B-main

Relevant changes:

git log --oneline 012bda0c99..44842a951c -- zephyr/program/corsla
common/charge_state_v2.c common/dps.c common/mkbp_* common/usb_charger.c
common/usb_common.c common/usbc/*_pd_* common/usbc/dp_alt_mode.c
common/usbc/usb_pe_drp_sm.c common/usbc/usb_prl_sm.c
common/usbc/usb_sm.c common/usbc/usb_tc_drp_acc_trysrc_sm.c
driver/battery/smart.c driver/bc12/pi3usb9201.* driver/charger/isl923x.*
driver/charger/rt949* driver/ppc/nx20p348x.* driver/ppc/rt1718s.*
driver/ppc/syv682x.* driver/tcpm/anx7447.* driver/tcpm/rt1718s.*
driver/tcpm/tcpci.* driver/usb_mux/it5205.* driver/usb_mux/ps8743.*
power/mt8186.c zephyr/boards/arm/npcx9/* zephyr/boards/riscv/it8xxx2/*
zephyr/drivers/* zephyr/program/corsola/* zephyr/shim/*
util/getversion.sh

ad568190dd USB-PD: Support Vconn swap during EPR entry for Sink
a421b3380f Zephyr: Add NX20P3481 CONFIG
53f35199ba Zephyr test: Test NXP PPC interrupts
eea95bc3d1 mt8186,mt8188: check the holder of AP_RST_ODL
171aa03229 zmake: Track project inheritance in ProjectConfig
67d4a05823 NX20P348X: Correct dead battery exit error handling
5056315df0 mt8186,mt8188: fix chipset_force_shutdown before power_chipset_init
76c0324c1b zephyr/tcpc_emul: automatically include prerequisites
2921b0afa3 zephyr: Don't include autoconf.h
fafe10a6fe ppc/nx20p348x: Do not set reserved bit
a514bea1d0 battery: Remove dead sbs_passthrough host cmds
d32a389718 Charger: CONFIG gate bypass mode
a4eb1414fd zephyr: tcpc: implement i2c transactions in rt1718s emulator
d8c8d452f7 zephyr: tcpc: add rt1718s as basic tcpc emulator

BRANCH=None
BUG=b:257320026 b:273854897 b:276229973 b:276468569 b:276947804
BUG=b:273722902 b:272518464 b:271118112 b:276458241
TEST=`make -j buildall`

Cq-Depend: chromium:4410221
Force-Relevant-Builds: all
Change-Id: I87dfb3549a3f228c1d4067965561a351999aa2c8
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>

5 files changed, 503 insertions, 0 deletions

diff --git a/zephyr/program/myst/src/common.c b/zephyr/program/myst/src/common.c
new file mode 100644
index 0000000000..c78d28bdaa
--- /dev/null
+++ b/zephyr/program/myst/src/common.c
@@ -0,0 +1,8 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(myst, CONFIG_MYST_LOG_LEVEL);
diff --git a/zephyr/program/myst/src/power_signals.c b/zephyr/program/myst/src/power_signals.c
new file mode 100644
index 0000000000..83b27cf87e
--- /dev/null
+++ b/zephyr/program/myst/src/power_signals.c
@@ -0,0 +1,215 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ap_power/ap_power.h"
+#include "charger.h"
+#include "chipset.h"
+#include "config.h"
+#include "driver/amd_stb.h"
+#include "gpio/gpio_int.h"
+#include "gpio_signal.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "power.h"
+#include "power/amd_x86.h"
+#include "throttle_ap.h"
+#include "timer.h"
+
+/* Power Signal Input List */
+/* TODO: b/218904113: Convert to using Zephyr GPIOs */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+/* looks like we don't have this on Myst.. but POWER_SIGNAL_COUNT is needed */
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+static void handle_prochot(bool asserted, void *data);
+
+const struct prochot_cfg prochot_cfg = {
+	.gpio_prochot_in = GPIO_CPU_PROCHOT,
+	.callback = handle_prochot,
+};
+
+/* Chipset hooks */
+static void baseboard_suspend_change(struct ap_power_ev_callback *cb,
+				     struct ap_power_ev_data data)
+{
+	switch (data.event) {
+	default:
+		return;
+
+	case AP_POWER_SUSPEND:
+		/* Disable display backlight and retimer */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				1);
+		break;
+
+	case AP_POWER_RESUME:
+		/* Enable retimer and display backlight */
+		gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_disable_disp_bl),
+				0);
+		/* Any retimer tuning can be done after the retimer turns on */
+		break;
+	}
+}
+
+static void check_charger_prochot(void)
+{
+	print_charger_prochot(CHARGER_SOLO);
+}
+DECLARE_DEFERRED(check_charger_prochot);
+
+static void handle_prochot(bool asserted, void *data)
+{
+	if (asserted) {
+		ccprints("Prochot asserted externally");
+		hook_call_deferred(&check_charger_prochot_data, 0);
+	} else
+		ccprints("Prochot deasserted externally");
+}
+
+static void baseboard_init(void)
+{
+	static struct ap_power_ev_callback cb;
+
+	/* Setup a suspend/resume callback */
+	ap_power_ev_init_callback(&cb, baseboard_suspend_change,
+				  AP_POWER_RESUME | AP_POWER_SUSPEND);
+	ap_power_ev_add_callback(&cb);
+	/* Enable Power Group interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_groupc_s0));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pg_lpddr_s3));
+
+	/* Enable thermtrip interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_soc_thermtrip));
+
+	/* Enable prochot interrupt */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_prochot));
+	throttle_ap_config_prochot(&prochot_cfg);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_POST_I2C);
+
+/**
+ * b/275949288: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.  This can be as long as ~65ms after cold boot.  Then wait an
+ * additional delay of T1a defined in the EDS before changing the power button.
+ */
+#define RSMRST_WAIT_DELAY 65
+#define EDS_PWR_BTN_RSMRST_T1A_DELAY 16
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level &&
+	    !gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l))) {
+		start = get_time();
+		do {
+			usleep(500);
+			if (gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				    gpio_ec_soc_rsmrst_l)))
+				break;
+		} while (time_since32(start) < (RSMRST_WAIT_DELAY * MSEC));
+
+		if (!gpio_pin_get_dt(
+			    GPIO_DT_FROM_NODELABEL(gpio_ec_soc_rsmrst_l)))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(EDS_PWR_BTN_RSMRST_T1A_DELAY);
+	}
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_mech_pwr_btn_odl),
+			level);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_soc_pwr_pgood(enum gpio_signal unused)
+{
+	gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_ec_soc_pwr_good),
+			gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+				gpio_pg_pcore_s0_r_od)) &&
+				gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(
+					gpio_pg_groupc_s0_od)));
+}
+
+void baseboard_s0_pgood(enum gpio_signal signal)
+{
+	baseboard_set_soc_pwr_pgood(signal);
+
+	/* Chain off power signal interrupt handler for PG_PCORE_S0_R_OD */
+	power_signal_interrupt(signal);
+}
+
+/* Note: signal parameter unused */
+void baseboard_set_en_pwr_pcore(enum gpio_signal unused)
+{
+	/*
+	 * EC must AND signals PG_LPDDR5_S3_OD, PG_GROUPC_S0_OD, and
+	 * EN_PWR_S0_R
+	 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_pg_pcore_s0_r_od),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_lpddr5_s3_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_groupc_s0_od)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0)));
+
+	/* Update EC_SOC_PWR_GOOD based on our results */
+	baseboard_set_soc_pwr_pgood(unused);
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_pin_set_dt(
+		GPIO_DT_FROM_NODELABEL(gpio_en_pwr_s0),
+		gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_slp_s3_l)) &&
+			gpio_pin_get_dt(
+				GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5)));
+
+	/* Change EN_PWR_PCORE_S0_R if needed*/
+	baseboard_set_en_pwr_pcore(signal);
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_s5_pgood(enum gpio_signal signal)
+{
+	/* Continue to our signal AND-ing and power interrupt */
+	baseboard_en_pwr_s0(signal);
+}
+
+void baseboard_set_en_pwr_s3(enum gpio_signal signal)
+{
+	/* Chain off the normal power signal interrupt handler */
+	power_signal_interrupt(signal);
+}
+
+void baseboard_soc_thermtrip(enum gpio_signal signal)
+{
+	ccprints("SoC thermtrip reported, shutting down");
+	chipset_force_shutdown(CHIPSET_SHUTDOWN_THERMAL);
+}
diff --git a/zephyr/program/myst/src/stt.c b/zephyr/program/myst/src/stt.c
new file mode 100644
index 0000000000..f739155ee6
--- /dev/null
+++ b/zephyr/program/myst/src/stt.c
@@ -0,0 +1,39 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Support code for STT temperature reporting */
+
+#include "chipset.h"
+#include "driver/temp_sensor/f75303.h"
+#include "temp_sensor/pct2075.h"
+#include "temp_sensor/temp_sensor.h"
+
+int board_get_soc_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(soc_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(soc_f75303)),
+				 temp_mk);
+#endif
+}
+
+int board_get_ambient_temp_mk(int *temp_mk)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+
+#ifdef CONFIG_TEMP_SENSOR_PCT2075
+	return pct2075_get_val_mk(PCT2075_SENSOR_ID(DT_NODELABEL(amb_pct2075)),
+				  temp_mk);
+#else
+	return f75303_get_val_mk(F75303_SENSOR_ID(DT_NODELABEL(amb_f75303)),
+				 temp_mk);
+#endif
+}
diff --git a/zephyr/program/myst/src/usb_pd_policy.c b/zephyr/program/myst/src/usb_pd_policy.c
new file mode 100644
index 0000000000..9e656e815f
--- /dev/null
+++ b/zephyr/program/myst/src/usb_pd_policy.c
@@ -0,0 +1,79 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Myst boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "ioexpander.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#include <zephyr/drivers/gpio.h>
+
+int pd_check_vconn_swap(int port)
+{
+	/*
+	 * Do not allow vconn swap 5V rail is off
+	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
+	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
+	 */
+	return gpio_pin_get_dt(GPIO_DT_FROM_NODELABEL(gpio_pg_pwr_s5));
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 1);
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
+int board_vbus_source_enabled(int port)
+{
+	return tcpm_get_src_ctrl(port);
+}
+
+/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
+int board_is_sourcing_vbus(int port)
+{
+	return board_vbus_source_enabled(port);
+}
diff --git a/zephyr/program/myst/src/usbc_config.c b/zephyr/program/myst/src/usbc_config.c
new file mode 100644
index 0000000000..c3aafd9da9
--- /dev/null
+++ b/zephyr/program/myst/src/usbc_config.c
@@ -0,0 +1,162 @@
+/* Copyright 2023 The ChromiumOS Authors
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Myst family-specific USB-C configuration */
+
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state.h"
+#include "charge_state_v2.h"
+#include "charger.h"
+#include "cros_board_info.h"
+#include "cros_cbi.h"
+#include "driver/charger/isl9241.h"
+#include "driver/tcpm/rt1718s.h"
+#include "driver/usb_mux/amd_fp6.h"
+#include "gpio/gpio_int.h"
+#include "hooks.h"
+#include "power.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc/usb_muxes.h"
+#include "usbc_ppc.h"
+
+#include <zephyr/drivers/gpio.h>
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ##args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ##args)
+
+/* USB-A ports */
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
+
+/* USB-C ports */
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
+BUILD_ASSERT(USBC_PORT_COUNT == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+static void usbc_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c0_ppc));
+	gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_usb_c1_ppc));
+
+	/* Enable SBU fault interrupts */
+	gpio_enable_dt_interrupt(
+		GPIO_INT_FROM_NODELABEL(int_usb_c0_c1_sbu_fault));
+}
+DECLARE_HOOK(HOOK_INIT, usbc_interrupt_init, HOOK_PRIO_POST_I2C);
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 && port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Check if the port is sourcing VBUS. */
+	if (tcpm_get_src_ctrl(port)) {
+		CPRINTSUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+void sbu_fault_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * TODO: b/275609315
+	 * Determine if the fault happened on C0 or C1
+	 */
+	int port = 0;
+
+	CPRINTSUSB("C%d: SBU fault", port);
+	pd_handle_overcurrent(port);
+}
+
+void usb_pd_soc_interrupt(enum gpio_signal signal)
+{
+	/*
+	 * This interrupt is unexpected with our use of the SoC mux, so just log
+	 * it as a point of interest.
+	 */
+	CPRINTSUSB("SOC PD Interrupt");
+}
+
+/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
+static void charger_prochot_init_isl9241(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, CONFIG_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, charger_prochot_init_isl9241, HOOK_PRIO_DEFAULT);
+
+void board_reset_pd_mcu(void)
+{
+	/* No reset line for TCPC0 */
+	/* No reset line for TCPC1 */
+}
+
+#define SAFE_RESET_VBUS_DELAY_MS 900
+#define SAFE_RESET_VBUS_MV 5000
+void board_hibernate(void)
+{
+	int port;
+	enum ec_error_list ret;
+
+	/*
+	 * If we are charging, then drop the Vbus level down to 5V to ensure
+	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
+	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
+	 * (b/79218851, b/143778351, b/147007265)
+	 */
+	port = charge_manager_get_active_charge_port();
+	if (port != CHARGE_PORT_NONE) {
+		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
+
+		/* Give PD task and PPC chip time to get to 5V */
+		msleep(SAFE_RESET_VBUS_DELAY_MS);
+	}
+
+	/* Try to put our battery fuel gauge into sleep mode */
+	ret = battery_sleep_fuel_gauge();
+	if ((ret != EC_SUCCESS) && (ret != EC_ERROR_UNIMPLEMENTED))
+		cprints(CC_SYSTEM, "Failed to send battery sleep command");
+}