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| author | Sooraj Govindan <sooraj.govindan@intel.com> | 2020-02-07 19:35:25 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-19 21:57:57 +0000 |
| commit | 2396f0e9bcd6fe2ac3fa60920771882299c2d7e5 (patch) | |
| tree | 79b47923020198bca950534a81e87fb2dacacadb /power | |
| parent | 0340484f40f22e3e26aaf490c292363be3697445 (diff) | |
| download | chrome-ec-2396f0e9bcd6fe2ac3fa60920771882299c2d7e5.tar.gz | |
waddledoo:Handle EC_AP_PCH_PWROK_OD and ALL_SYS_PWRGD
As per Waddledoo power sequencing requirements,
1. ALL_SYS_PWRGD should be driven based on DRAM power good and
the PP1050_ST power good.
2. the EC needs to assert EC_AP_PCH_PWROK_OD, with a 2ms minimum
delay after receiving the DRAM power good and the PP1050_ST power good.
3. Enable CONFIG_BACKLIGHT_LID
BUG=b:147257114
BRANCH=None
TEST=make -j BOARD=waddledoo; flash waddledoo, verify that
DUT can boot to S0.
Change-Id: I5ad226faa15cfe8ae569524decf405bbd378a28c
Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044250
Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/icelake.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/power/icelake.c b/power/icelake.c index 2a2d484b85..c020b5541f 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -82,6 +82,11 @@ __overridable int intel_x86_get_pg_ec_all_sys_pwrgd(void) return gpio_get_level(GPIO_PG_EC_ALL_SYS_PWRGD); } +__overridable void board_jsl_all_sys_pwrgd(int value) +{ + +} + void chipset_force_shutdown(enum chipset_shutdown_reason reason) { int timeout_ms = 50; @@ -161,11 +166,12 @@ static void enable_pp5000_rail(void) } #ifdef CONFIG_CHIPSET_JASPERLAKE -static void assert_ec_ap_vccst_pwrgd(void) +static void assert_ec_ap_vccst_pwrgd_pch_pwrok(void) { GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 1); + GPIO_SET_LEVEL(GPIO_EC_AP_PCH_PWROK_OD, 1); } -DECLARE_DEFERRED(assert_ec_ap_vccst_pwrgd); +DECLARE_DEFERRED(assert_ec_ap_vccst_pwrgd_pch_pwrok); #endif /* CONFIG_CHIPSET_JASPERLAKE */ enum power_state power_handle_state(enum power_state state) @@ -189,14 +195,19 @@ enum power_state power_handle_state(enum power_state state) #ifdef CONFIG_CHIPSET_JASPERLAKE /* - * Assert VCCST power good when ALL_SYS_PWRGD is received with a 2ms - * delay minimum. + * Set ALL_SYS_PWRGD after receiving both PG_DRAM and PG_PP1050_ST. + * Assert VCCST power good and PCH_PWROK, when ALL_SYS_PWRGD is + * received with a 2ms delay minimum. */ if (all_sys_pwrgd_in && !gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { - hook_call_deferred(&assert_ec_ap_vccst_pwrgd_data, 2 * MSEC); + board_jsl_all_sys_pwrgd(all_sys_pwrgd_in); + hook_call_deferred(&assert_ec_ap_vccst_pwrgd_pch_pwrok_data, + 2 * MSEC); } else if (!all_sys_pwrgd_in && gpio_get_level(GPIO_EC_AP_VCCST_PWRGD_OD)) { GPIO_SET_LEVEL(GPIO_EC_AP_VCCST_PWRGD_OD, 0); + GPIO_SET_LEVEL(GPIO_EC_AP_PCH_PWROK_OD, 0); + board_jsl_all_sys_pwrgd(all_sys_pwrgd_in); } #endif /* CONFIG_CHIPSET_JASPERLAKE */ |