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| author | Furquan Shaikh <furquan@chromium.org> | 2017-09-23 01:15:53 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-03 17:28:28 -0700 |
| commit | 04db902fee7dc7ae615fbb22454dc247a534c1f0 (patch) | |
| tree | 4edb40bb519b0ce9acae506b0d899ed529649ae3 /power | |
| parent | 81682e06bc94d1b9e702b9794349bd34594896b3 (diff) | |
| download | chrome-ec-04db902fee7dc7ae615fbb22454dc247a534c1f0.tar.gz | |
intel_x86: Enable/disable SLP_S0 signal based on S0ix entry/exit
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/intel_x86.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/power/intel_x86.c b/power/intel_x86.c index 6c182344c4..c1f49353fd 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -464,6 +464,13 @@ power_board_handle_host_sleep_event(enum host_sleep_event state) void power_chipset_handle_host_sleep_event(enum host_sleep_event state) { power_board_handle_host_sleep_event(state); + +#ifdef CONFIG_POWER_S0IX + if (state == HOST_SLEEP_EVENT_S0IX_SUSPEND) + power_signal_enable_interrupt(sleep_sig[SYS_SLEEP_S0IX]); + else + power_signal_disable_interrupt(sleep_sig[SYS_SLEEP_S0IX]); +#endif } #endif |