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| author | Randall Spangler <rspangler@chromium.org> | 2014-01-07 09:24:34 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-01-08 02:19:29 +0000 |
| commit | 59602b41e834155cb79125063dc41c7e1e259986 (patch) | |
| tree | 5baf15f6176a798d3b5aca46e903bdd38e19d762 /power | |
| parent | 5a4b239981a76aa9e98325bc082c67cbdfe487de (diff) | |
| download | chrome-ec-59602b41e834155cb79125063dc41c7e1e259986.tar.gz | |
rambi: Remove duplicate EC_PWROK workaround for proto 1.5
After this change, only Rambi 2.0 boards will boot properly.
This cleanup is necessary before supporting other Baytrail systems.
BUG=chrome-os-partner:24414
BRANCH=rambi
TEST=as soon as I get a 2.0 board
Change-Id: Ic9e3afcee9dae5c0b7f31a7aa4500b2572ba92c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181754
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/baytrail.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/power/baytrail.c b/power/baytrail.c index fff9ae33ca..b8144b717d 100644 --- a/power/baytrail.c +++ b/power/baytrail.c @@ -60,11 +60,6 @@ void chipset_force_shutdown(void) * transitions to G3. */ gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - /* - * TODO(crosbug.com/p/24424): Remove duplicate SYS_PWROK output when we - * finish transitioning from proto 1.5 to proto 2.0. - */ - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 0); gpio_set_level(GPIO_PCH_RSMRST_L, 0); } @@ -86,10 +81,8 @@ void chipset_reset(int cold_reset) /* PWROK must deassert for at least 3 RTC clocks = 91 us */ gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 0); udelay(100); gpio_set_level(GPIO_PCH_SYS_PWROK, 1); - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 1); } else { /* @@ -135,7 +128,6 @@ enum x86_state x86_chipset_init(void) gpio_set_level(GPIO_PP5000_EN, 0); gpio_set_level(GPIO_PCH_RSMRST_L, 0); gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 0); wireless_enable(0); } } @@ -283,7 +275,6 @@ enum x86_state x86_handle_state(enum x86_state state) /* Set SYS and CORE PWROK */ gpio_set_level(GPIO_PCH_SYS_PWROK, 1); - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 1); gpio_set_level(GPIO_PCH_CORE_PWROK, 1); return X86_S0; @@ -293,7 +284,6 @@ enum x86_state x86_handle_state(enum x86_state state) /* Clear SYS and CORE PWROK */ gpio_set_level(GPIO_PCH_SYS_PWROK, 0); - gpio_set_level(GPIO_PCH_SYS_PWROK_NEW, 0); gpio_set_level(GPIO_PCH_CORE_PWROK, 0); /* Wait 40ns */ |