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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2017-01-06 09:22:54 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-06 20:38:59 -0800 |
| commit | 4fa1c8b9e3dd89bb069ce0d2478dc12b542ba66b (patch) | |
| tree | 55af5d07492393197ff7a0eba29c39480d20f190 /power | |
| parent | 8a681c8e60159dfd23047346ac93e585420b4146 (diff) | |
| download | chrome-ec-4fa1c8b9e3dd89bb069ce0d2478dc12b542ba66b.tar.gz | |
apollolake: Add support to enable eSPI signals
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Change-Id: I6d90d647a6e19c627aa68ddd8a203d6be8b2e32d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/425820
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/apollolake.c | 38 |
1 files changed, 32 insertions, 6 deletions
diff --git a/power/apollolake.c b/power/apollolake.c index b93a1e25c2..b0d2916df6 100644 --- a/power/apollolake.c +++ b/power/apollolake.c @@ -46,6 +46,32 @@ static int throttle_cpu; /* Throttle CPU? */ static int forcing_coldreset; /* Forced coldreset in progress? */ static int power_s5_up; /* Chipset is sequencing up or down */ +enum sys_sleep_state { + SYS_SLEEP_S5, + SYS_SLEEP_S4, + SYS_SLEEP_S3 +}; + +/* Get system sleep state through GPIOs or VWs */ +static int chipset_get_sleep_signal(enum sys_sleep_state state) +{ +#ifdef CONFIG_ESPI_VW_SIGNALS + if (state == SYS_SLEEP_S4) + return espi_vw_get_wire(VW_SLP_S4_L); + else if (state == SYS_SLEEP_S3) + return espi_vw_get_wire(VW_SLP_S3_L); +#else + if (state == SYS_SLEEP_S4) + return gpio_get_level(GPIO_PCH_SLP_S4_L); + else if (state == SYS_SLEEP_S3) + return gpio_get_level(GPIO_PCH_SLP_S3_L); +#endif + + /* We should never run here */ + ASSERT(0); + return 0; +} + __attribute__((weak)) void chipset_do_shutdown(void) { /* Need to implement board specific shutdown */ @@ -198,7 +224,7 @@ static enum power_state _power_handle_state(enum power_state state) /* Required rail went away */ chipset_force_shutdown(); return POWER_S5G3; - } else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1) { + } else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 1) { /* Power up to next state */ return POWER_S5S3; } @@ -209,10 +235,10 @@ static enum power_state _power_handle_state(enum power_state state) /* Required rail went away */ chipset_force_shutdown(); return POWER_S3S5; - } else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) { + } else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1) { /* Power up to next state */ return POWER_S3S0; - } else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) { + } else if (chipset_get_sleep_signal(SYS_SLEEP_S4) == 0) { /* Power down to next state */ return POWER_S3S5; } @@ -225,10 +251,10 @@ static enum power_state _power_handle_state(enum power_state state) #ifdef CONFIG_POWER_S0IX } else if ((power_get_host_sleep_state() == HOST_SLEEP_EVENT_S0IX_SUSPEND) && - (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) { + (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) { return POWER_S0S0ix; #endif - } else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) { + } else if (chipset_get_sleep_signal(SYS_SLEEP_S3) == 0) { /* Power down to next state */ return POWER_S0S3; } @@ -242,7 +268,7 @@ static enum power_state _power_handle_state(enum power_state state) */ if ((power_get_host_sleep_state() == HOST_SLEEP_EVENT_S0IX_RESUME) && - (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1)) { + (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) { return POWER_S0ixS0; } |