diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2017-01-11 11:50:53 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-21 10:03:45 -0800 |
| commit | 6550e44ed7effb61e9090f954de54ea6c74994bb (patch) | |
| tree | 4a321ed4d30fee1de63a9c2d6e5c9a33532cae70 /power | |
| parent | 927b2e754f772965e2de285c5c7ab3dc191aba51 (diff) | |
| download | chrome-ec-6550e44ed7effb61e9090f954de54ea6c74994bb.tar.gz | |
intel_x86: Handle unexpected power loss in S0iX
Picked the code from Glados branch.
Change-Id: I0f24f717f712dcd46e3ddca2a8c86888739f3deb
Reviewed-on: https://chromium-review.googlesource.com/390343
BUG=chrome-os-partner:61645
BRANCH=none
TEST=Manually tested on Reef. Reef exits from S0iX upon issuing
'apreset warm' & 'apreset cold' from the ec console.
Change-Id: Ie5fa4ad79b7c78344e99fcbf4ba2b5b800f9934c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/427393
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'power')
| -rw-r--r-- | power/intel_x86.c | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/power/intel_x86.c b/power/intel_x86.c index 3fe3e68736..13f2be53ac 100644 --- a/power/intel_x86.c +++ b/power/intel_x86.c @@ -136,6 +136,16 @@ static void s0ix_lpc_disable_wake_mask_for_lid_open(void) ; } } + +static void handle_chipset_reset(void) +{ + if (chipset_in_state(CHIPSET_STATE_STANDBY)) { + CPRINTS("chipset reset: exit s0ix"); + power_reset_host_sleep_state(HOST_SLEEP_EVENT_S0IX_RESUME); + task_wake(TASK_ID_CHIPSET); + } +} +DECLARE_HOOK(HOOK_CHIPSET_RESET, handle_chipset_reset, HOOK_PRIO_FIRST); #endif void chipset_throttle_cpu(int throttle) @@ -217,14 +227,12 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state) #ifdef CONFIG_POWER_S0IX case POWER_S0ix: - /* - * TODO: crosbug.com/p/61645 - * Add code to handle unexpected power loss. - */ if ((power_get_host_sleep_state() == HOST_SLEEP_EVENT_S0IX_RESUME) && (chipset_get_sleep_signal(SYS_SLEEP_S3) == 1)) { return POWER_S0ixS0; + } else if (!power_has_signals(IN_PGOOD_ALL_CORE)) { + return POWER_S0; } break; |