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| author | Mary Ruthven <mruthven@chromium.org> | 2021-11-04 00:31:56 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-10 23:32:50 +0000 |
| commit | e1312234bd8534983e6d268b6ea624be0ef2ce9f (patch) | |
| tree | 9d4411f4eeaf049ecf5199df586c8d9435c83dbc /power/skylake.h | |
| parent | ac9fd1a3d0332cad93446c5750b67122d4cf559d (diff) | |
| download | chrome-ec-e1312234bd8534983e6d268b6ea624be0ef2ce9f.tar.gz | |
remove power code
Nothing in the platform/cr50 uses power code. Remove it.
BUG=b:200823466
TEST=make buildall -j
Change-Id: Ic6ef286632fd997de93170485a16b9d5f8a72d37
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3273180
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Diffstat (limited to 'power/skylake.h')
| -rw-r--r-- | power/skylake.h | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/power/skylake.h b/power/skylake.h deleted file mode 100644 index c8a656c6c5..0000000000 --- a/power/skylake.h +++ /dev/null @@ -1,57 +0,0 @@ -/* Copyright 2016 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* Skylake IMVP8 / ROP PMIC chipset power control module for Chrome EC */ - -#ifndef __CROS_EC_SKYLAKE_H -#define __CROS_EC_SKYLAKE_H - -/* - * Input state flags. - * TODO: Normalize the power signal masks from board defines to SoC headers. - */ -#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED) -#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED) -#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED) - -#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \ - IN_PCH_SLP_S4_DEASSERTED | \ - IN_PCH_SLP_SUS_DEASSERTED) - -/* - * DPWROK is NC / stuffing option on initial boards. - * TODO(shawnn): Figure out proper control signals. - */ -#define IN_PGOOD_ALL_CORE 0 - -#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) - -#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED - -#define CHARGER_INITIALIZED_DELAY_MS 100 -#define CHARGER_INITIALIZED_TRIES 40 - -/* Power signals list */ -enum power_signal { -#ifdef CONFIG_POWER_S0IX - X86_SLP_S0_DEASSERTED, -#endif - X86_SLP_S3_DEASSERTED, - X86_SLP_S4_DEASSERTED, - X86_SLP_SUS_DEASSERTED, - X86_RSMRST_L_PWRGD, - X86_PMIC_DPWROK, - - /* Number of X86 signals */ - POWER_SIGNAL_COUNT -}; - -/* - * Board can define this function to indicate to the skylake - * power code that it does not have working reset flags. - */ -int board_has_working_reset_flags(void); - -#endif /* __CROS_EC_SKYLAKE_H */ |