power/rk3399: Add CHIPSET_POWER_SEQ_VERSION == 3

This change is for Nefario rev0.
Compared to version 1, we merge some pp900 power rails and
disable power for some accessories in S3.

Fixed the conflict with CL:572211.

BUG=b:63408169
BRANCH=none
TEST=build nefario

Change-Id: Ibe67f86c8b51f7d1efd15d301692f63831a93876
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/588332
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>

1 files changed, 63 insertions, 11 deletions

diff --git a/power/rk3399.c b/power/rk3399.c
index 956685783d..31860b0700 100644
--- a/power/rk3399.c
+++ b/power/rk3399.c
@@ -12,6 +12,7 @@
  * Version 1: Control signals PP900_PLL_EN and PP900_PMU_EN
  *	      are merged with PP900_USB_EN.
  * Version 2: Simplified power tree, fewer control signals.
+ * Version 3: Close to version 1 but more components disabled in S3.
  */
 
 #include "charge_state.h"
@@ -81,14 +82,26 @@ BUILD_ASSERT(GPIO_COUNT < 256);
  * The entries in the table are handled sequentially from the top
  * to the bottom.
  */
-static const struct power_seq_op s5s3_power_seq[] = {
+
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+static const struct power_seq_op s5s3_power_seq[] = {
 	{ GPIO_PP900_S3_EN, 1, 2 },
 	{ GPIO_SYS_RST_L, 0, 0 },
 	{ GPIO_PP3300_S3_EN, 1, 2 },
 	{ GPIO_PP1800_S3_EN, 1, 2 },
 	{ GPIO_PP1250_S3_EN, 1, 2 },
+};
+#elif CONFIG_CHIPSET_POWER_SEQ_VERSION == 3
+static const struct power_seq_op s5s3_power_seq[] = {
+	{ GPIO_PP900_S3_EN, 1, 2 },
+	{ GPIO_PP1800_PMU_EN_L, 0, 2 },
+	{ GPIO_LPDDR_PWR_EN, 1, 2 },
+	{ GPIO_PP1800_USB_EN_L, 0, 2 },
+	{ GPIO_PP3300_USB_EN_L, 0, 2 },
+	{ GPIO_PP5000_EN, 1, 2 },
+};
 #else
+static const struct power_seq_op s5s3_power_seq[] = {
 	{ GPIO_PPVAR_LOGIC_EN, 1, 0 },
 	{ GPIO_PP900_AP_EN, 1, 0 },
 	{ GPIO_PP900_PCIE_EN, 1, 2 },
@@ -105,25 +118,39 @@ static const struct power_seq_op s5s3_power_seq[] = {
 	{ GPIO_PP5000_EN, 1, 0 },
 	{ GPIO_PP3300_TRACKPAD_EN_L, 0, 1 },
 	{ GPIO_PP1800_LID_EN_L, 0, 0 },
-	{ GPIO_PP1800_SIXAXIS_EN_L, 0, 2},
-	{ GPIO_PP1800_SENSOR_EN_L, 0, 0},
-#endif
+	{ GPIO_PP1800_SIXAXIS_EN_L, 0, 2 },
+	{ GPIO_PP1800_SENSOR_EN_L, 0, 0 },
 };
+#endif
 
 /* The power sequence for POWER_S3S0 */
-static const struct power_seq_op s3s0_power_seq[] = {
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+static const struct power_seq_op s3s0_power_seq[] = {
 	{ GPIO_AP_CORE_EN, 1, 2 },
-	{ GPIO_PP1800_S0_EN, 1, 0},
+	{ GPIO_PP1800_S0_EN, 1, 0 },
+};
+#elif CONFIG_CHIPSET_POWER_SEQ_VERSION == 3
+static const struct power_seq_op s3s0_power_seq[] = {
+	{ GPIO_PP900_S0_EN, 1, 2 },
+	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 },
+	{ GPIO_AP_CORE_EN, 1, 2 },
+	{ GPIO_PP1800_S0_EN_L, 0, 2 },
+	{ GPIO_PP3300_S0_EN_L, 0, 2 },
+	{ GPIO_PP3300_TRACKPAD_EN_L, 0, 1 },
+	{ GPIO_PP1800_LID_EN_L, 0, 0 },
+	{ GPIO_PP1800_SIXAXIS_EN_L, 0, 2 },
+	{ GPIO_PP1800_SENSOR_EN_L, 0, 0 },
+};
 #else
+static const struct power_seq_op s3s0_power_seq[] = {
 	{ GPIO_PPVAR_CLOGIC_EN, 1, 2 },
 	{ GPIO_PP900_DDRPLL_EN, 1, 2 },
 	{ GPIO_PP1800_AP_AVDD_EN_L, 0, 2 },
 	{ GPIO_AP_CORE_EN, 1, 2 },
 	{ GPIO_PP1800_S0_EN_L, 0, 2 },
 	{ GPIO_PP3300_S0_EN_L, 0, 0 },
-#endif
 };
+#endif
 
 #ifdef S3_USB_WAKE
 /* Sigs that may already be on in S3, if we need to wake-on-USB */
@@ -135,19 +162,33 @@ static const struct power_seq_op s3s0_usb_wake_power_seq[] = {
 #endif
 
 /* The power sequence for POWER_S0S3 */
-static const struct power_seq_op s0s3_power_seq[] = {
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+static const struct power_seq_op s0s3_power_seq[] = {
 	{ GPIO_PP1800_S0_EN, 0, 1 },
 	{ GPIO_AP_CORE_EN, 0, 20 },
+};
+#elif CONFIG_CHIPSET_POWER_SEQ_VERSION == 3
+static const struct power_seq_op s0s3_power_seq[] = {
+	{ GPIO_PP1800_SENSOR_EN_L, 1, 0 },
+	{ GPIO_PP1800_SIXAXIS_EN_L, 1, 0 },
+	{ GPIO_PP1800_LID_EN_L, 1, 0 },
+	{ GPIO_PP3300_TRACKPAD_EN_L, 1, 0 },
+	{ GPIO_PP3300_S0_EN_L, 1, 20 },
+	{ GPIO_PP1800_S0_EN_L, 1, 1 },
+	{ GPIO_AP_CORE_EN, 0, 20 },
+	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
+	{ GPIO_PP900_S0_EN, 0, 0 },
+};
 #else
+static const struct power_seq_op s0s3_power_seq[] = {
 	{ GPIO_PP3300_S0_EN_L, 1, 20 },
 	{ GPIO_PP1800_S0_EN_L, 1, 1 },
 	{ GPIO_AP_CORE_EN, 0, 20 },
 	{ GPIO_PP1800_AP_AVDD_EN_L, 1, 1 },
 	{ GPIO_PP900_DDRPLL_EN, 0, 1 },
 	{ GPIO_PPVAR_CLOGIC_EN, 0, 0 },
-#endif
 };
+#endif
 
 #ifdef S3_USB_WAKE
 /* Sigs that need to be left on in S3, if we need to wake-on-USB */
@@ -159,13 +200,24 @@ static const struct power_seq_op s0s3_usb_wake_power_seq[] = {
 #endif
 
 /* The power sequence for POWER_S3S5 */
-static const struct power_seq_op s3s5_power_seq[] = {
 #if CONFIG_CHIPSET_POWER_SEQ_VERSION == 2
+static const struct power_seq_op s3s5_power_seq[] = {
 	{ GPIO_PP1250_S3_EN, 0, 2 },
 	{ GPIO_PP1800_S3_EN, 0, 2 },
 	{ GPIO_PP3300_S3_EN, 0, 2 },
 	{ GPIO_PP900_S3_EN, 0, 0 },
+};
+#elif CONFIG_CHIPSET_POWER_SEQ_VERSION == 3
+static const struct power_seq_op s3s5_power_seq[] = {
+	{ GPIO_PP5000_EN, 0, 0 },
+	{ GPIO_PP3300_USB_EN_L, 1, 20 },
+	{ GPIO_PP1800_USB_EN_L, 1, 10 },
+	{ GPIO_LPDDR_PWR_EN, 0, 20 },
+	{ GPIO_PP1800_PMU_EN_L, 1, 2 },
+	{ GPIO_PP900_S3_EN, 0, 0 },
+};
 #else
+static const struct power_seq_op s3s5_power_seq[] = {
 	{ GPIO_PP1800_SENSOR_EN_L, 1, 0},
 	{ GPIO_PP1800_SIXAXIS_EN_L, 1, 0},
 	{ GPIO_PP1800_LID_EN_L, 1, 0 },
@@ -183,8 +235,8 @@ static const struct power_seq_op s3s5_power_seq[] = {
 	{ GPIO_PP900_PCIE_EN, 0, 0 },
 	{ GPIO_PP900_AP_EN, 0, 0 },
 	{ GPIO_PPVAR_LOGIC_EN, 0, 0 },
-#endif
 };
+#endif
 
 static int forcing_shutdown;