intel_x86: Move chipset reset logic to common code

Chipset reset logic chipset_reset() is same for APL, GLK,
SKL, KBL and CNL hence move it to common code.

BUG=b:72426192
BRANCH=none
TEST=make buildall -j

Change-Id: I289e9807d53e397e62d650289e80b6ce25fe399e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974471
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

1 files changed, 31 insertions, 0 deletions

diff --git a/power/intel_x86.c b/power/intel_x86.c
index 2e983c514c..73cac45613 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -509,3 +509,34 @@ void power_chipset_handle_host_sleep_event(enum host_sleep_event state)
 }
 
 #endif
+
+void chipset_reset(int cold_reset)
+{
+	/*
+	 * Irrespective of cold_reset value, always toggle SYS_RESET_L to
+	 * perform a chipset reset. RCIN# which was used earlier to trigger
+	 * a warm reset is known to not work in certain cases where the CPU
+	 * is in a bad state (crbug.com/721853).
+	 *
+	 * The EC cannot control warm vs cold reset of the chipset using
+	 * SYS_RESET_L; it's more of a request.
+	 */
+	CPRINTS("%s", __func__);
+
+	/*
+	 * Toggling SYS_RESET_L will not have any impact when it's already
+	 * low (i,e. Chipset is in reset state).
+	 */
+	if (gpio_get_level(GPIO_SYS_RESET_L) == 0) {
+		CPRINTS("Chipset is in reset state");
+		return;
+	}
+
+	gpio_set_level(GPIO_SYS_RESET_L, 0);
+	/*
+	 * Debounce time for SYS_RESET_L is 16 ms. Wait twice that period
+	 * to be safe.
+	 */
+	udelay(32 * MSEC);
+	gpio_set_level(GPIO_SYS_RESET_L, 1);
+}