diff options
| author | Kyoung Kim <kyoung.il.kim@intel.com> | 2015-10-01 19:22:01 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-19 20:01:58 -0800 |
| commit | ebf92ecc839a6361605eb4c3ac7cb44fa4eb603a (patch) | |
| tree | a7ef9a393bc55799e9b61b9b4a9d5b613fedc216 /power/common.c | |
| parent | 8704de934edc294c1efb3115cb8192bbc7f0dc65 (diff) | |
| download | chrome-ec-ebf92ecc839a6361605eb4c3ac7cb44fa4eb603a.tar.gz | |
Kunimitsu: Add S0ix on SLP_S0 assertion
On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep
and EC is eligable to enter heavy sleep idle task.
Wakeup from S0ix by lid open, any key press, power button or track pad
will be done by PCH block by asserting SLP_S0.
At S0ix, 1 msec pulse will be generated every 8sec and this signal
should be ignored since this is NOT S0ix entry/exit related and defered
interrupt for SLP_S0 were added.
BRANCH=master
BUG=none
TEST=in OS shell, run following commands.
Following command is valid with coreboot with S0ix patches.
"echo freeze > /sys/power/state"
then,
Measure EC power consumption and compare it with one in S0.
And on EC console, there should be NO periodic message, "power
state 4 = S0ix, in 0x001d" every 8 sec.
Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/307947
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/common.c')
| -rw-r--r-- | power/common.c | 35 |
1 files changed, 33 insertions, 2 deletions
diff --git a/power/common.c b/power/common.c index c75865ea53..380b3410fe 100644 --- a/power/common.c +++ b/power/common.c @@ -38,12 +38,19 @@ static const char * const state_names[] = { "S5", "S3", "S0", +#ifdef CONFIG_POWER_S0IX + "S0ix", +#endif "G3->S5", "S5->S3", "S3->S0", "S0->S3", "S3->S5", "S5->G3", +#ifdef CONFIG_POWER_S0IX + "S0ix->S0", + "S0->S0ix", +#endif }; static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */ @@ -64,6 +71,15 @@ static uint32_t hibernate_delay = CONFIG_HIBERNATE_DELAY_SEC; static int pause_in_s5; #endif +static int power_signal_get_level(enum gpio_signal signal) +{ +#ifdef CONFIG_POWER_S0IX + return chipset_get_ps_debounced_level(signal); +#else + return gpio_get_level(signal); +#endif +} + /** * Update input signals mask */ @@ -74,7 +90,7 @@ static void power_update_signals(void) int i; for (i = 0; i < POWER_SIGNAL_COUNT; i++, s++) { - if (gpio_get_level(s->gpio) == s->level) + if (power_signal_get_level(s->gpio) == s->level) inew |= 1 << i; } @@ -229,7 +245,13 @@ static enum power_state power_common_state(enum power_state state) power_wait_signals(0); task_wait_event(-1); break; - +#ifdef CONFIG_POWER_S0IX + case POWER_S0ix: + /* Wait for a message */ + power_wait_signals(0); + task_wait_event(-1); + break; +#endif default: /* No common functionality for transition states */ break; @@ -279,6 +301,15 @@ int chipset_in_state(int state_mask) case POWER_S0: need_mask = CHIPSET_STATE_ON; break; +#ifdef CONFIG_POWER_S0IX + case POWER_S0ixS0: + case POWER_S0S0ix: + need_mask = CHIPSET_STATE_ON | CHIPSET_STATE_STANDBY; + break; + case POWER_S0ix: + need_mask = CHIPSET_STATE_STANDBY; + break; +#endif } /* Return non-zero if all needed bits are present */ |