diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2017-07-25 11:33:15 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-07-25 20:08:32 -0700 |
| commit | 61a80d620ac5c332cf601f202200cd60ce13fb48 (patch) | |
| tree | 1548944e83d7fd0e21cc33069356c2aae1f18de7 /power/cannonlake.h | |
| parent | d483c289a91c84f8f2af3a8618383f5f738d02e1 (diff) | |
| download | chrome-ec-61a80d620ac5c332cf601f202200cd60ce13fb48.tar.gz | |
CNL: Use SYS_RST_L for warm/cold chipset reset.
The EC cannot control warm vs cold reset of the chipset using the
SYS_RST_L pin; it's just a reset request. This commit changes the
behaviour of chipset_reset to assert SYS_RST_L regardless if a cold or a
warm reset is requested.
BUG=b:63508740
BRANCH=None
TEST=make -j buildall; Flash a modified image on npcx7_evb, verify that
no panics or asserts are hit.
Change-Id: Idfd6f556bf909c7df4e8bd50a79b60719478cde7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/585573
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'power/cannonlake.h')
| -rw-r--r-- | power/cannonlake.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/power/cannonlake.h b/power/cannonlake.h index da67c7cbb8..404558441f 100644 --- a/power/cannonlake.h +++ b/power/cannonlake.h @@ -17,8 +17,7 @@ IN_PCH_SLP_S4_DEASSERTED | \ IN_PCH_SLP_SUS_DEASSERTED) -/* TODO(aaboagye): Should this be PMIC_DPWROK ? */ -#define IN_PGOOD_ALL_CORE 0 +#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK) #define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED) |